Fix bug in gen_cvt_ftoi1. Add test 107_stack_safe for this fix.
[tinycc.git] / x86_64-gen.c
blob62a1c64d546c1ded1c14b8e42b44e81aedd2a1dd
1 /*
2 * x86-64 code generator for TCC
4 * Copyright (c) 2008 Shinichiro Hamaji
6 * Based on i386-gen.c by Fabrice Bellard
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifdef TARGET_DEFS_ONLY
25 /* number of available registers */
26 #define NB_REGS 25
27 #define NB_ASM_REGS 16
28 #define CONFIG_TCC_ASM
30 /* a register can belong to several classes. The classes must be
31 sorted from more general to more precise (see gv2() code which does
32 assumptions on it). */
33 #define RC_INT 0x0001 /* generic integer register */
34 #define RC_FLOAT 0x0002 /* generic float register */
35 #define RC_RAX 0x0004
36 #define RC_RCX 0x0008
37 #define RC_RDX 0x0010
38 #define RC_ST0 0x0080 /* only for long double */
39 #define RC_R8 0x0100
40 #define RC_R9 0x0200
41 #define RC_R10 0x0400
42 #define RC_R11 0x0800
43 #define RC_XMM0 0x1000
44 #define RC_XMM1 0x2000
45 #define RC_XMM2 0x4000
46 #define RC_XMM3 0x8000
47 #define RC_XMM4 0x10000
48 #define RC_XMM5 0x20000
49 #define RC_XMM6 0x40000
50 #define RC_XMM7 0x80000
51 #define RC_IRET RC_RAX /* function return: integer register */
52 #define RC_LRET RC_RDX /* function return: second integer register */
53 #define RC_FRET RC_XMM0 /* function return: float register */
54 #define RC_QRET RC_XMM1 /* function return: second float register */
56 /* pretty names for the registers */
57 enum {
58 TREG_RAX = 0,
59 TREG_RCX = 1,
60 TREG_RDX = 2,
61 TREG_RSP = 4,
62 TREG_RSI = 6,
63 TREG_RDI = 7,
65 TREG_R8 = 8,
66 TREG_R9 = 9,
67 TREG_R10 = 10,
68 TREG_R11 = 11,
70 TREG_XMM0 = 16,
71 TREG_XMM1 = 17,
72 TREG_XMM2 = 18,
73 TREG_XMM3 = 19,
74 TREG_XMM4 = 20,
75 TREG_XMM5 = 21,
76 TREG_XMM6 = 22,
77 TREG_XMM7 = 23,
79 TREG_ST0 = 24,
81 TREG_MEM = 0x20
84 #define REX_BASE(reg) (((reg) >> 3) & 1)
85 #define REG_VALUE(reg) ((reg) & 7)
87 /* return registers for function */
88 #define REG_IRET TREG_RAX /* single word int return register */
89 #define REG_LRET TREG_RDX /* second word return register (for long long) */
90 #define REG_FRET TREG_XMM0 /* float return register */
91 #define REG_QRET TREG_XMM1 /* second float return register */
93 /* defined if function parameters must be evaluated in reverse order */
94 #define INVERT_FUNC_PARAMS
96 /* pointer size, in bytes */
97 #define PTR_SIZE 8
99 /* long double size and alignment, in bytes */
100 #define LDOUBLE_SIZE 16
101 #define LDOUBLE_ALIGN 16
102 /* maximum alignment (for aligned attribute support) */
103 #define MAX_ALIGN 16
105 /******************************************************/
106 #else /* ! TARGET_DEFS_ONLY */
107 /******************************************************/
108 #include "tcc.h"
109 #include <assert.h>
111 ST_DATA const int reg_classes[NB_REGS] = {
112 /* eax */ RC_INT | RC_RAX,
113 /* ecx */ RC_INT | RC_RCX,
114 /* edx */ RC_INT | RC_RDX,
120 RC_R8,
121 RC_R9,
122 RC_R10,
123 RC_R11,
128 /* xmm0 */ RC_FLOAT | RC_XMM0,
129 /* xmm1 */ RC_FLOAT | RC_XMM1,
130 /* xmm2 */ RC_FLOAT | RC_XMM2,
131 /* xmm3 */ RC_FLOAT | RC_XMM3,
132 /* xmm4 */ RC_FLOAT | RC_XMM4,
133 /* xmm5 */ RC_FLOAT | RC_XMM5,
134 /* xmm6 an xmm7 are included so gv() can be used on them,
135 but they are not tagged with RC_FLOAT because they are
136 callee saved on Windows */
137 RC_XMM6,
138 RC_XMM7,
139 /* st0 */ RC_ST0
142 static unsigned long func_sub_sp_offset;
143 static int func_ret_sub;
145 /* XXX: make it faster ? */
146 ST_FUNC void g(int c)
148 int ind1;
149 if (nocode_wanted)
150 return;
151 ind1 = ind + 1;
152 if (ind1 > cur_text_section->data_allocated)
153 section_realloc(cur_text_section, ind1);
154 cur_text_section->data[ind] = c;
155 ind = ind1;
158 ST_FUNC void o(unsigned int c)
160 while (c) {
161 g(c);
162 c = c >> 8;
166 ST_FUNC void gen_le16(int v)
168 g(v);
169 g(v >> 8);
172 ST_FUNC void gen_le32(int c)
174 g(c);
175 g(c >> 8);
176 g(c >> 16);
177 g(c >> 24);
180 ST_FUNC void gen_le64(int64_t c)
182 g(c);
183 g(c >> 8);
184 g(c >> 16);
185 g(c >> 24);
186 g(c >> 32);
187 g(c >> 40);
188 g(c >> 48);
189 g(c >> 56);
192 static void orex(int ll, int r, int r2, int b)
194 if ((r & VT_VALMASK) >= VT_CONST)
195 r = 0;
196 if ((r2 & VT_VALMASK) >= VT_CONST)
197 r2 = 0;
198 if (ll || REX_BASE(r) || REX_BASE(r2))
199 o(0x40 | REX_BASE(r) | (REX_BASE(r2) << 2) | (ll << 3));
200 o(b);
203 /* output a symbol and patch all calls to it */
204 ST_FUNC void gsym_addr(int t, int a)
206 while (t) {
207 unsigned char *ptr = cur_text_section->data + t;
208 uint32_t n = read32le(ptr); /* next value */
209 write32le(ptr, a < 0 ? -a : a - t - 4);
210 t = n;
214 static int is64_type(int t)
216 return ((t & VT_BTYPE) == VT_PTR ||
217 (t & VT_BTYPE) == VT_FUNC ||
218 (t & VT_BTYPE) == VT_LLONG);
221 /* instruction + 4 bytes data. Return the address of the data */
222 static int oad(int c, int s)
224 int t;
225 if (nocode_wanted)
226 return s;
227 o(c);
228 t = ind;
229 gen_le32(s);
230 return t;
233 /* generate jmp to a label */
234 #define gjmp2(instr,lbl) oad(instr,lbl)
236 ST_FUNC void gen_addr32(int r, Sym *sym, int c)
238 if (r & VT_SYM)
239 greloca(cur_text_section, sym, ind, R_X86_64_32S, c), c=0;
240 gen_le32(c);
243 /* output constant with relocation if 'r & VT_SYM' is true */
244 ST_FUNC void gen_addr64(int r, Sym *sym, int64_t c)
246 if (r & VT_SYM)
247 greloca(cur_text_section, sym, ind, R_X86_64_64, c), c=0;
248 gen_le64(c);
251 /* output constant with relocation if 'r & VT_SYM' is true */
252 ST_FUNC void gen_addrpc32(int r, Sym *sym, int c)
254 if (r & VT_SYM)
255 greloca(cur_text_section, sym, ind, R_X86_64_PC32, c-4), c=4;
256 gen_le32(c-4);
259 /* output got address with relocation */
260 static void gen_gotpcrel(int r, Sym *sym, int c)
262 #ifdef TCC_TARGET_PE
263 tcc_error("internal error: no GOT on PE: %s %x %x | %02x %02x %02x\n",
264 get_tok_str(sym->v, NULL), c, r,
265 cur_text_section->data[ind-3],
266 cur_text_section->data[ind-2],
267 cur_text_section->data[ind-1]
269 #endif
270 greloca(cur_text_section, sym, ind, R_X86_64_GOTPCREL, -4);
271 gen_le32(0);
272 if (c) {
273 /* we use add c, %xxx for displacement */
274 orex(1, r, 0, 0x81);
275 o(0xc0 + REG_VALUE(r));
276 gen_le32(c);
280 static void gen_modrm_impl(int op_reg, int r, Sym *sym, int c, int is_got)
282 op_reg = REG_VALUE(op_reg) << 3;
283 if ((r & VT_VALMASK) == VT_CONST) {
284 /* constant memory reference */
285 if (!(r & VT_SYM)) {
286 /* Absolute memory reference */
287 o(0x04 | op_reg); /* [sib] | destreg */
288 oad(0x25, c); /* disp32 */
289 } else {
290 o(0x05 | op_reg); /* (%rip)+disp32 | destreg */
291 if (is_got) {
292 gen_gotpcrel(r, sym, c);
293 } else {
294 gen_addrpc32(r, sym, c);
297 } else if ((r & VT_VALMASK) == VT_LOCAL) {
298 /* currently, we use only ebp as base */
299 if (c == (char)c) {
300 /* short reference */
301 o(0x45 | op_reg);
302 g(c);
303 } else {
304 oad(0x85 | op_reg, c);
306 } else if ((r & VT_VALMASK) >= TREG_MEM) {
307 if (c) {
308 g(0x80 | op_reg | REG_VALUE(r));
309 gen_le32(c);
310 } else {
311 g(0x00 | op_reg | REG_VALUE(r));
313 } else {
314 g(0x00 | op_reg | REG_VALUE(r));
318 /* generate a modrm reference. 'op_reg' contains the additional 3
319 opcode bits */
320 static void gen_modrm(int op_reg, int r, Sym *sym, int c)
322 gen_modrm_impl(op_reg, r, sym, c, 0);
325 /* generate a modrm reference. 'op_reg' contains the additional 3
326 opcode bits */
327 static void gen_modrm64(int opcode, int op_reg, int r, Sym *sym, int c)
329 int is_got;
330 is_got = (op_reg & TREG_MEM) && !(sym->type.t & VT_STATIC);
331 orex(1, r, op_reg, opcode);
332 gen_modrm_impl(op_reg, r, sym, c, is_got);
336 /* load 'r' from value 'sv' */
337 void load(int r, SValue *sv)
339 int v, t, ft, fc, fr;
340 SValue v1;
342 #ifdef TCC_TARGET_PE
343 SValue v2;
344 sv = pe_getimport(sv, &v2);
345 #endif
347 fr = sv->r;
348 ft = sv->type.t & ~VT_DEFSIGN;
349 fc = sv->c.i;
350 if (fc != sv->c.i && (fr & VT_SYM))
351 tcc_error("64 bit addend in load");
353 ft &= ~(VT_VOLATILE | VT_CONSTANT);
355 #ifndef TCC_TARGET_PE
356 /* we use indirect access via got */
357 if ((fr & VT_VALMASK) == VT_CONST && (fr & VT_SYM) &&
358 (fr & VT_LVAL) && !(sv->sym->type.t & VT_STATIC)) {
359 /* use the result register as a temporal register */
360 int tr = r | TREG_MEM;
361 if (is_float(ft)) {
362 /* we cannot use float registers as a temporal register */
363 tr = get_reg(RC_INT) | TREG_MEM;
365 gen_modrm64(0x8b, tr, fr, sv->sym, 0);
367 /* load from the temporal register */
368 fr = tr | VT_LVAL;
370 #endif
372 v = fr & VT_VALMASK;
373 if (fr & VT_LVAL) {
374 int b, ll;
375 if (v == VT_LLOCAL) {
376 v1.type.t = VT_PTR;
377 v1.r = VT_LOCAL | VT_LVAL;
378 v1.c.i = fc;
379 fr = r;
380 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
381 fr = get_reg(RC_INT);
382 load(fr, &v1);
384 if (fc != sv->c.i) {
385 /* If the addends doesn't fit into a 32bit signed
386 we must use a 64bit move. We've checked above
387 that this doesn't have a sym associated. */
388 v1.type.t = VT_LLONG;
389 v1.r = VT_CONST;
390 v1.c.i = sv->c.i;
391 fr = r;
392 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
393 fr = get_reg(RC_INT);
394 load(fr, &v1);
395 fc = 0;
397 ll = 0;
398 /* Like GCC we can load from small enough properly sized
399 structs and unions as well.
400 XXX maybe move to generic operand handling, but should
401 occur only with asm, so tccasm.c might also be a better place */
402 if ((ft & VT_BTYPE) == VT_STRUCT) {
403 int align;
404 switch (type_size(&sv->type, &align)) {
405 case 1: ft = VT_BYTE; break;
406 case 2: ft = VT_SHORT; break;
407 case 4: ft = VT_INT; break;
408 case 8: ft = VT_LLONG; break;
409 default:
410 tcc_error("invalid aggregate type for register load");
411 break;
414 if ((ft & VT_BTYPE) == VT_FLOAT) {
415 b = 0x6e0f66;
416 r = REG_VALUE(r); /* movd */
417 } else if ((ft & VT_BTYPE) == VT_DOUBLE) {
418 b = 0x7e0ff3; /* movq */
419 r = REG_VALUE(r);
420 } else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
421 b = 0xdb, r = 5; /* fldt */
422 } else if ((ft & VT_TYPE) == VT_BYTE || (ft & VT_TYPE) == VT_BOOL) {
423 b = 0xbe0f; /* movsbl */
424 } else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
425 b = 0xb60f; /* movzbl */
426 } else if ((ft & VT_TYPE) == VT_SHORT) {
427 b = 0xbf0f; /* movswl */
428 } else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
429 b = 0xb70f; /* movzwl */
430 } else {
431 assert(((ft & VT_BTYPE) == VT_INT)
432 || ((ft & VT_BTYPE) == VT_LLONG)
433 || ((ft & VT_BTYPE) == VT_PTR)
434 || ((ft & VT_BTYPE) == VT_FUNC)
436 ll = is64_type(ft);
437 b = 0x8b;
439 if (ll) {
440 gen_modrm64(b, r, fr, sv->sym, fc);
441 } else {
442 orex(ll, fr, r, b);
443 gen_modrm(r, fr, sv->sym, fc);
445 } else {
446 if (v == VT_CONST) {
447 if (fr & VT_SYM) {
448 #ifdef TCC_TARGET_PE
449 orex(1,0,r,0x8d);
450 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
451 gen_addrpc32(fr, sv->sym, fc);
452 #else
453 if (sv->sym->type.t & VT_STATIC) {
454 orex(1,0,r,0x8d);
455 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
456 gen_addrpc32(fr, sv->sym, fc);
457 } else {
458 orex(1,0,r,0x8b);
459 o(0x05 + REG_VALUE(r) * 8); /* mov xx(%rip), r */
460 gen_gotpcrel(r, sv->sym, fc);
462 #endif
463 } else if (is64_type(ft)) {
464 orex(1,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
465 gen_le64(sv->c.i);
466 } else {
467 orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
468 gen_le32(fc);
470 } else if (v == VT_LOCAL) {
471 orex(1,0,r,0x8d); /* lea xxx(%ebp), r */
472 gen_modrm(r, VT_LOCAL, sv->sym, fc);
473 } else if (v == VT_CMP) {
474 if (fc & 0x100)
476 v = vtop->cmp_r;
477 fc &= ~0x100;
478 /* This was a float compare. If the parity bit is
479 set the result was unordered, meaning false for everything
480 except TOK_NE, and true for TOK_NE. */
481 orex(0, r, 0, 0xb0 + REG_VALUE(r)); /* mov $0/1,%al */
482 g(v ^ fc ^ (v == TOK_NE));
483 o(0x037a + (REX_BASE(r) << 8));
485 orex(0,r,0, 0x0f); /* setxx %br */
486 o(fc);
487 o(0xc0 + REG_VALUE(r));
488 orex(0,r,0, 0x0f);
489 o(0xc0b6 + REG_VALUE(r) * 0x900); /* movzbl %al, %eax */
490 } else if (v == VT_JMP || v == VT_JMPI) {
491 t = v & 1;
492 orex(0,r,0,0);
493 oad(0xb8 + REG_VALUE(r), t); /* mov $1, r */
494 o(0x05eb + (REX_BASE(r) << 8)); /* jmp after */
495 gsym(fc);
496 orex(0,r,0,0);
497 oad(0xb8 + REG_VALUE(r), t ^ 1); /* mov $0, r */
498 } else if (v != r) {
499 if ((r >= TREG_XMM0) && (r <= TREG_XMM7)) {
500 if (v == TREG_ST0) {
501 /* gen_cvt_ftof(VT_DOUBLE); */
502 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
503 /* movsd -0x10(%rsp),%xmmN */
504 o(0x100ff2);
505 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
506 o(0xf024);
507 } else {
508 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
509 if ((ft & VT_BTYPE) == VT_FLOAT) {
510 o(0x100ff3);
511 } else {
512 assert((ft & VT_BTYPE) == VT_DOUBLE);
513 o(0x100ff2);
515 o(0xc0 + REG_VALUE(v) + REG_VALUE(r)*8);
517 } else if (r == TREG_ST0) {
518 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
519 /* gen_cvt_ftof(VT_LDOUBLE); */
520 /* movsd %xmmN,-0x10(%rsp) */
521 o(0x110ff2);
522 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
523 o(0xf024);
524 o(0xf02444dd); /* fldl -0x10(%rsp) */
525 } else {
526 orex(1,r,v, 0x89);
527 o(0xc0 + REG_VALUE(r) + REG_VALUE(v) * 8); /* mov v, r */
533 /* store register 'r' in lvalue 'v' */
534 void store(int r, SValue *v)
536 int fr, bt, ft, fc;
537 int op64 = 0;
538 /* store the REX prefix in this variable when PIC is enabled */
539 int pic = 0;
541 #ifdef TCC_TARGET_PE
542 SValue v2;
543 v = pe_getimport(v, &v2);
544 #endif
546 fr = v->r & VT_VALMASK;
547 ft = v->type.t;
548 fc = v->c.i;
549 if (fc != v->c.i && (fr & VT_SYM))
550 tcc_error("64 bit addend in store");
551 ft &= ~(VT_VOLATILE | VT_CONSTANT);
552 bt = ft & VT_BTYPE;
554 #ifndef TCC_TARGET_PE
555 /* we need to access the variable via got */
556 if (fr == VT_CONST && (v->r & VT_SYM)) {
557 /* mov xx(%rip), %r11 */
558 o(0x1d8b4c);
559 gen_gotpcrel(TREG_R11, v->sym, v->c.i);
560 pic = is64_type(bt) ? 0x49 : 0x41;
562 #endif
564 /* XXX: incorrect if float reg to reg */
565 if (bt == VT_FLOAT) {
566 o(0x66);
567 o(pic);
568 o(0x7e0f); /* movd */
569 r = REG_VALUE(r);
570 } else if (bt == VT_DOUBLE) {
571 o(0x66);
572 o(pic);
573 o(0xd60f); /* movq */
574 r = REG_VALUE(r);
575 } else if (bt == VT_LDOUBLE) {
576 o(0xc0d9); /* fld %st(0) */
577 o(pic);
578 o(0xdb); /* fstpt */
579 r = 7;
580 } else {
581 if (bt == VT_SHORT)
582 o(0x66);
583 o(pic);
584 if (bt == VT_BYTE || bt == VT_BOOL)
585 orex(0, 0, r, 0x88);
586 else if (is64_type(bt))
587 op64 = 0x89;
588 else
589 orex(0, 0, r, 0x89);
591 if (pic) {
592 /* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
593 if (op64)
594 o(op64);
595 o(3 + (r << 3));
596 } else if (op64) {
597 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
598 gen_modrm64(op64, r, v->r, v->sym, fc);
599 } else if (fr != r) {
600 /* XXX: don't we really come here? */
601 abort();
602 o(0xc0 + fr + r * 8); /* mov r, fr */
604 } else {
605 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
606 gen_modrm(r, v->r, v->sym, fc);
607 } else if (fr != r) {
608 /* XXX: don't we really come here? */
609 abort();
610 o(0xc0 + fr + r * 8); /* mov r, fr */
615 /* 'is_jmp' is '1' if it is a jump */
616 static void gcall_or_jmp(int is_jmp)
618 int r;
619 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
620 ((vtop->r & VT_SYM) && (vtop->c.i-4) == (int)(vtop->c.i-4))) {
621 /* constant symbolic case -> simple relocation */
622 #ifdef TCC_TARGET_PE
623 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PC32, (int)(vtop->c.i-4));
624 #else
625 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PLT32, (int)(vtop->c.i-4));
626 #endif
627 oad(0xe8 + is_jmp, 0); /* call/jmp im */
628 } else {
629 /* otherwise, indirect call */
630 r = TREG_R11;
631 load(r, vtop);
632 o(0x41); /* REX */
633 o(0xff); /* call/jmp *r */
634 o(0xd0 + REG_VALUE(r) + (is_jmp << 4));
638 #if defined(CONFIG_TCC_BCHECK)
639 #ifndef TCC_TARGET_PE
640 static addr_t func_bound_offset;
641 static unsigned long func_bound_ind;
642 #endif
644 static void gen_static_call(int v)
646 Sym *sym = external_global_sym(v, &func_old_type);
647 oad(0xe8, 0);
648 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
651 /* generate a bounded pointer addition */
652 ST_FUNC void gen_bounded_ptr_add(void)
654 /* save all temporary registers */
655 save_regs(0);
657 /* prepare fast x86_64 function call */
658 gv(RC_RAX);
659 o(0xc68948); // mov %rax,%rsi ## second arg in %rsi, this must be size
660 vtop--;
662 gv(RC_RAX);
663 o(0xc78948); // mov %rax,%rdi ## first arg in %rdi, this must be ptr
664 vtop--;
666 /* do a fast function call */
667 gen_static_call(TOK___bound_ptr_add);
669 /* returned pointer is in rax */
670 vtop++;
671 vtop->r = TREG_RAX | VT_BOUNDED;
674 /* relocation offset of the bounding function call point */
675 vtop->c.i = (cur_text_section->reloc->data_offset - sizeof(ElfW(Rela)));
678 /* patch pointer addition in vtop so that pointer dereferencing is
679 also tested */
680 ST_FUNC void gen_bounded_ptr_deref(void)
682 addr_t func;
683 int size, align;
684 ElfW(Rela) *rel;
685 Sym *sym;
687 size = 0;
688 /* XXX: put that code in generic part of tcc */
689 if (!is_float(vtop->type.t)) {
690 if (vtop->r & VT_LVAL_BYTE)
691 size = 1;
692 else if (vtop->r & VT_LVAL_SHORT)
693 size = 2;
695 if (!size)
696 size = type_size(&vtop->type, &align);
697 switch(size) {
698 case 1: func = TOK___bound_ptr_indir1; break;
699 case 2: func = TOK___bound_ptr_indir2; break;
700 case 4: func = TOK___bound_ptr_indir4; break;
701 case 8: func = TOK___bound_ptr_indir8; break;
702 case 12: func = TOK___bound_ptr_indir12; break;
703 case 16: func = TOK___bound_ptr_indir16; break;
704 default:
705 tcc_error("unhandled size when dereferencing bounded pointer");
706 func = 0;
707 break;
710 sym = external_global_sym(func, &func_old_type);
711 if (!sym->c)
712 put_extern_sym(sym, NULL, 0, 0);
714 /* patch relocation */
715 /* XXX: find a better solution ? */
717 rel = (ElfW(Rela) *)(cur_text_section->reloc->data + vtop->c.i);
718 rel->r_info = ELF64_R_INFO(sym->c, ELF64_R_TYPE(rel->r_info));
720 #endif
722 #ifdef TCC_TARGET_PE
724 #define REGN 4
725 static const uint8_t arg_regs[REGN] = {
726 TREG_RCX, TREG_RDX, TREG_R8, TREG_R9
729 /* Prepare arguments in R10 and R11 rather than RCX and RDX
730 because gv() will not ever use these */
731 static int arg_prepare_reg(int idx) {
732 if (idx == 0 || idx == 1)
733 /* idx=0: r10, idx=1: r11 */
734 return idx + 10;
735 else
736 return arg_regs[idx];
739 static int func_scratch, func_alloca;
741 /* Generate function call. The function address is pushed first, then
742 all the parameters in call order. This functions pops all the
743 parameters and the function address. */
745 static void gen_offs_sp(int b, int r, int d)
747 orex(1,0,r & 0x100 ? 0 : r, b);
748 if (d == (char)d) {
749 o(0x2444 | (REG_VALUE(r) << 3));
750 g(d);
751 } else {
752 o(0x2484 | (REG_VALUE(r) << 3));
753 gen_le32(d);
757 static int using_regs(int size)
759 return !(size > 8 || (size & (size - 1)));
762 /* Return the number of registers needed to return the struct, or 0 if
763 returning via struct pointer. */
764 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
766 int size, align;
767 *ret_align = 1; // Never have to re-align return values for x86-64
768 *regsize = 8;
769 size = type_size(vt, &align);
770 if (!using_regs(size))
771 return 0;
772 if (size == 8)
773 ret->t = VT_LLONG;
774 else if (size == 4)
775 ret->t = VT_INT;
776 else if (size == 2)
777 ret->t = VT_SHORT;
778 else
779 ret->t = VT_BYTE;
780 ret->ref = NULL;
781 return 1;
784 static int is_sse_float(int t) {
785 int bt;
786 bt = t & VT_BTYPE;
787 return bt == VT_DOUBLE || bt == VT_FLOAT;
790 static int gfunc_arg_size(CType *type) {
791 int align;
792 if (type->t & (VT_ARRAY|VT_BITFIELD))
793 return 8;
794 return type_size(type, &align);
797 void gfunc_call(int nb_args)
799 int size, r, args_size, i, d, bt, struct_size;
800 int arg;
802 args_size = (nb_args < REGN ? REGN : nb_args) * PTR_SIZE;
803 arg = nb_args;
805 /* for struct arguments, we need to call memcpy and the function
806 call breaks register passing arguments we are preparing.
807 So, we process arguments which will be passed by stack first. */
808 struct_size = args_size;
809 for(i = 0; i < nb_args; i++) {
810 SValue *sv;
812 --arg;
813 sv = &vtop[-i];
814 bt = (sv->type.t & VT_BTYPE);
815 size = gfunc_arg_size(&sv->type);
817 if (using_regs(size))
818 continue; /* arguments smaller than 8 bytes passed in registers or on stack */
820 if (bt == VT_STRUCT) {
821 /* align to stack align size */
822 size = (size + 15) & ~15;
823 /* generate structure store */
824 r = get_reg(RC_INT);
825 gen_offs_sp(0x8d, r, struct_size);
826 struct_size += size;
828 /* generate memcpy call */
829 vset(&sv->type, r | VT_LVAL, 0);
830 vpushv(sv);
831 vstore();
832 --vtop;
833 } else if (bt == VT_LDOUBLE) {
834 gv(RC_ST0);
835 gen_offs_sp(0xdb, 0x107, struct_size);
836 struct_size += 16;
840 if (func_scratch < struct_size)
841 func_scratch = struct_size;
843 arg = nb_args;
844 struct_size = args_size;
846 for(i = 0; i < nb_args; i++) {
847 --arg;
848 bt = (vtop->type.t & VT_BTYPE);
850 size = gfunc_arg_size(&vtop->type);
851 if (!using_regs(size)) {
852 /* align to stack align size */
853 size = (size + 15) & ~15;
854 if (arg >= REGN) {
855 d = get_reg(RC_INT);
856 gen_offs_sp(0x8d, d, struct_size);
857 gen_offs_sp(0x89, d, arg*8);
858 } else {
859 d = arg_prepare_reg(arg);
860 gen_offs_sp(0x8d, d, struct_size);
862 struct_size += size;
863 } else {
864 if (is_sse_float(vtop->type.t)) {
865 if (tcc_state->nosse)
866 tcc_error("SSE disabled");
867 if (arg >= REGN) {
868 gv(RC_XMM0);
869 /* movq %xmm0, j*8(%rsp) */
870 gen_offs_sp(0xd60f66, 0x100, arg*8);
871 } else {
872 /* Load directly to xmmN register */
873 gv(RC_XMM0 << arg);
874 d = arg_prepare_reg(arg);
875 /* mov %xmmN, %rxx */
876 o(0x66);
877 orex(1,d,0, 0x7e0f);
878 o(0xc0 + arg*8 + REG_VALUE(d));
880 } else {
881 if (bt == VT_STRUCT) {
882 vtop->type.ref = NULL;
883 vtop->type.t = size > 4 ? VT_LLONG : size > 2 ? VT_INT
884 : size > 1 ? VT_SHORT : VT_BYTE;
887 r = gv(RC_INT);
888 if (arg >= REGN) {
889 gen_offs_sp(0x89, r, arg*8);
890 } else {
891 d = arg_prepare_reg(arg);
892 orex(1,d,r,0x89); /* mov */
893 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
897 vtop--;
899 save_regs(0);
900 /* Copy R10 and R11 into RCX and RDX, respectively */
901 if (nb_args > 0) {
902 o(0xd1894c); /* mov %r10, %rcx */
903 if (nb_args > 1) {
904 o(0xda894c); /* mov %r11, %rdx */
908 gcall_or_jmp(0);
910 if ((vtop->r & VT_SYM) && vtop->sym->v == TOK_alloca) {
911 /* need to add the "func_scratch" area after alloca */
912 o(0x48); func_alloca = oad(0x05, func_alloca); /* sub $NN, %rax */
915 /* other compilers don't clear the upper bits when returning char/short */
916 bt = vtop->type.ref->type.t & (VT_BTYPE | VT_UNSIGNED);
917 if (bt == (VT_BYTE | VT_UNSIGNED) || (bt & VT_TYPE) == VT_BOOL)
918 o(0xc0b60f); /* movzbl %al, %eax */
919 else if (bt == VT_BYTE)
920 o(0xc0be0f); /* movsbl %al, %eax */
921 else if (bt == VT_SHORT)
922 o(0x98); /* cwtl */
923 else if (bt == (VT_SHORT | VT_UNSIGNED))
924 o(0xc0b70f); /* movzbl %al, %eax */
925 #if 0 /* handled in gen_cast() */
926 else if (bt == VT_INT)
927 o(0x9848); /* cltq */
928 else if (bt == (VT_INT | VT_UNSIGNED))
929 o(0xc089); /* mov %eax,%eax */
930 #endif
931 vtop--;
935 #define FUNC_PROLOG_SIZE 11
937 /* generate function prolog of type 't' */
938 void gfunc_prolog(CType *func_type)
940 int addr, reg_param_index, bt, size;
941 Sym *sym;
942 CType *type;
944 func_ret_sub = 0;
945 func_scratch = 0;
946 func_alloca = 0;
947 loc = 0;
949 addr = PTR_SIZE * 2;
950 ind += FUNC_PROLOG_SIZE;
951 func_sub_sp_offset = ind;
952 reg_param_index = 0;
954 sym = func_type->ref;
956 /* if the function returns a structure, then add an
957 implicit pointer parameter */
958 func_vt = sym->type;
959 func_var = (sym->f.func_type == FUNC_ELLIPSIS);
960 size = gfunc_arg_size(&func_vt);
961 if (!using_regs(size)) {
962 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
963 func_vc = addr;
964 reg_param_index++;
965 addr += 8;
968 /* define parameters */
969 while ((sym = sym->next) != NULL) {
970 type = &sym->type;
971 bt = type->t & VT_BTYPE;
972 size = gfunc_arg_size(type);
973 if (!using_regs(size)) {
974 if (reg_param_index < REGN) {
975 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
977 sym_push(sym->v & ~SYM_FIELD, type,
978 VT_LLOCAL | lvalue_type(type->t), addr);
979 } else {
980 if (reg_param_index < REGN) {
981 /* save arguments passed by register */
982 if ((bt == VT_FLOAT) || (bt == VT_DOUBLE)) {
983 if (tcc_state->nosse)
984 tcc_error("SSE disabled");
985 o(0xd60f66); /* movq */
986 gen_modrm(reg_param_index, VT_LOCAL, NULL, addr);
987 } else {
988 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
991 sym_push(sym->v & ~SYM_FIELD, type,
992 VT_LOCAL | lvalue_type(type->t), addr);
994 addr += 8;
995 reg_param_index++;
998 while (reg_param_index < REGN) {
999 if (func_type->ref->f.func_type == FUNC_ELLIPSIS) {
1000 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
1001 addr += 8;
1003 reg_param_index++;
1007 /* generate function epilog */
1008 void gfunc_epilog(void)
1010 int v, saved_ind;
1012 o(0xc9); /* leave */
1013 if (func_ret_sub == 0) {
1014 o(0xc3); /* ret */
1015 } else {
1016 o(0xc2); /* ret n */
1017 g(func_ret_sub);
1018 g(func_ret_sub >> 8);
1021 saved_ind = ind;
1022 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1023 /* align local size to word & save local variables */
1024 func_scratch = (func_scratch + 15) & -16;
1025 v = (func_scratch + -loc + 15) & -16;
1027 if (v >= 4096) {
1028 Sym *sym = external_global_sym(TOK___chkstk, &func_old_type);
1029 oad(0xb8, v); /* mov stacksize, %eax */
1030 oad(0xe8, 0); /* call __chkstk, (does the stackframe too) */
1031 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
1032 o(0x90); /* fill for FUNC_PROLOG_SIZE = 11 bytes */
1033 } else {
1034 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1035 o(0xec8148); /* sub rsp, stacksize */
1036 gen_le32(v);
1039 /* add the "func_scratch" area after each alloca seen */
1040 gsym_addr(func_alloca, -func_scratch);
1042 cur_text_section->data_offset = saved_ind;
1043 pe_add_unwind_data(ind, saved_ind, v);
1044 ind = cur_text_section->data_offset;
1047 #else
1049 static void gadd_sp(int val)
1051 if (val == (char)val) {
1052 o(0xc48348);
1053 g(val);
1054 } else {
1055 oad(0xc48148, val); /* add $xxx, %rsp */
1059 typedef enum X86_64_Mode {
1060 x86_64_mode_none,
1061 x86_64_mode_memory,
1062 x86_64_mode_integer,
1063 x86_64_mode_sse,
1064 x86_64_mode_x87
1065 } X86_64_Mode;
1067 static X86_64_Mode classify_x86_64_merge(X86_64_Mode a, X86_64_Mode b)
1069 if (a == b)
1070 return a;
1071 else if (a == x86_64_mode_none)
1072 return b;
1073 else if (b == x86_64_mode_none)
1074 return a;
1075 else if ((a == x86_64_mode_memory) || (b == x86_64_mode_memory))
1076 return x86_64_mode_memory;
1077 else if ((a == x86_64_mode_integer) || (b == x86_64_mode_integer))
1078 return x86_64_mode_integer;
1079 else if ((a == x86_64_mode_x87) || (b == x86_64_mode_x87))
1080 return x86_64_mode_memory;
1081 else
1082 return x86_64_mode_sse;
1085 static X86_64_Mode classify_x86_64_inner(CType *ty)
1087 X86_64_Mode mode;
1088 Sym *f;
1090 switch (ty->t & VT_BTYPE) {
1091 case VT_VOID: return x86_64_mode_none;
1093 case VT_INT:
1094 case VT_BYTE:
1095 case VT_SHORT:
1096 case VT_LLONG:
1097 case VT_BOOL:
1098 case VT_PTR:
1099 case VT_FUNC:
1100 return x86_64_mode_integer;
1102 case VT_FLOAT:
1103 case VT_DOUBLE: return x86_64_mode_sse;
1105 case VT_LDOUBLE: return x86_64_mode_x87;
1107 case VT_STRUCT:
1108 f = ty->ref;
1110 mode = x86_64_mode_none;
1111 for (f = f->next; f; f = f->next)
1112 mode = classify_x86_64_merge(mode, classify_x86_64_inner(&f->type));
1114 return mode;
1116 assert(0);
1117 return 0;
1120 static X86_64_Mode classify_x86_64_arg(CType *ty, CType *ret, int *psize, int *palign, int *reg_count)
1122 X86_64_Mode mode;
1123 int size, align, ret_t = 0;
1125 if (ty->t & (VT_BITFIELD|VT_ARRAY)) {
1126 *psize = 8;
1127 *palign = 8;
1128 *reg_count = 1;
1129 ret_t = ty->t;
1130 mode = x86_64_mode_integer;
1131 } else {
1132 size = type_size(ty, &align);
1133 *psize = (size + 7) & ~7;
1134 *palign = (align + 7) & ~7;
1136 if (size > 16) {
1137 mode = x86_64_mode_memory;
1138 } else {
1139 mode = classify_x86_64_inner(ty);
1140 switch (mode) {
1141 case x86_64_mode_integer:
1142 if (size > 8) {
1143 *reg_count = 2;
1144 ret_t = VT_QLONG;
1145 } else {
1146 *reg_count = 1;
1147 ret_t = (size > 4) ? VT_LLONG : VT_INT;
1149 break;
1151 case x86_64_mode_x87:
1152 *reg_count = 1;
1153 ret_t = VT_LDOUBLE;
1154 break;
1156 case x86_64_mode_sse:
1157 if (size > 8) {
1158 *reg_count = 2;
1159 ret_t = VT_QFLOAT;
1160 } else {
1161 *reg_count = 1;
1162 ret_t = (size > 4) ? VT_DOUBLE : VT_FLOAT;
1164 break;
1165 default: break; /* nothing to be done for x86_64_mode_memory and x86_64_mode_none*/
1170 if (ret) {
1171 ret->ref = NULL;
1172 ret->t = ret_t;
1175 return mode;
1178 ST_FUNC int classify_x86_64_va_arg(CType *ty)
1180 /* This definition must be synced with stdarg.h */
1181 enum __va_arg_type {
1182 __va_gen_reg, __va_float_reg, __va_stack
1184 int size, align, reg_count;
1185 X86_64_Mode mode = classify_x86_64_arg(ty, NULL, &size, &align, &reg_count);
1186 switch (mode) {
1187 default: return __va_stack;
1188 case x86_64_mode_integer: return __va_gen_reg;
1189 case x86_64_mode_sse: return __va_float_reg;
1193 /* Return the number of registers needed to return the struct, or 0 if
1194 returning via struct pointer. */
1195 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
1197 int size, align, reg_count;
1198 *ret_align = 1; // Never have to re-align return values for x86-64
1199 *regsize = 8;
1200 return (classify_x86_64_arg(vt, ret, &size, &align, &reg_count) != x86_64_mode_memory);
1203 #define REGN 6
1204 static const uint8_t arg_regs[REGN] = {
1205 TREG_RDI, TREG_RSI, TREG_RDX, TREG_RCX, TREG_R8, TREG_R9
1208 static int arg_prepare_reg(int idx) {
1209 if (idx == 2 || idx == 3)
1210 /* idx=2: r10, idx=3: r11 */
1211 return idx + 8;
1212 else
1213 return arg_regs[idx];
1216 /* Generate function call. The function address is pushed first, then
1217 all the parameters in call order. This functions pops all the
1218 parameters and the function address. */
1219 void gfunc_call(int nb_args)
1221 X86_64_Mode mode;
1222 CType type;
1223 int size, align, r, args_size, stack_adjust, i, reg_count, bt;
1224 int nb_reg_args = 0;
1225 int nb_sse_args = 0;
1226 int sse_reg, gen_reg;
1227 char _onstack[nb_args ? nb_args : 1], *onstack = _onstack;
1229 /* calculate the number of integer/float register arguments, remember
1230 arguments to be passed via stack (in onstack[]), and also remember
1231 if we have to align the stack pointer to 16 (onstack[i] == 2). Needs
1232 to be done in a left-to-right pass over arguments. */
1233 stack_adjust = 0;
1234 for(i = nb_args - 1; i >= 0; i--) {
1235 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1236 if (mode == x86_64_mode_sse && nb_sse_args + reg_count <= 8) {
1237 nb_sse_args += reg_count;
1238 onstack[i] = 0;
1239 } else if (mode == x86_64_mode_integer && nb_reg_args + reg_count <= REGN) {
1240 nb_reg_args += reg_count;
1241 onstack[i] = 0;
1242 } else if (mode == x86_64_mode_none) {
1243 onstack[i] = 0;
1244 } else {
1245 if (align == 16 && (stack_adjust &= 15)) {
1246 onstack[i] = 2;
1247 stack_adjust = 0;
1248 } else
1249 onstack[i] = 1;
1250 stack_adjust += size;
1254 if (nb_sse_args && tcc_state->nosse)
1255 tcc_error("SSE disabled but floating point arguments passed");
1257 /* fetch cpu flag before generating any code */
1258 if (vtop >= vstack && (vtop->r & VT_VALMASK) == VT_CMP)
1259 gv(RC_INT);
1261 /* for struct arguments, we need to call memcpy and the function
1262 call breaks register passing arguments we are preparing.
1263 So, we process arguments which will be passed by stack first. */
1264 gen_reg = nb_reg_args;
1265 sse_reg = nb_sse_args;
1266 args_size = 0;
1267 stack_adjust &= 15;
1268 for (i = 0; i < nb_args;) {
1269 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1270 if (!onstack[i]) {
1271 ++i;
1272 continue;
1274 /* Possibly adjust stack to align SSE boundary. We're processing
1275 args from right to left while allocating happens left to right
1276 (stack grows down), so the adjustment needs to happen _after_
1277 an argument that requires it. */
1278 if (stack_adjust) {
1279 o(0x50); /* push %rax; aka sub $8,%rsp */
1280 args_size += 8;
1281 stack_adjust = 0;
1283 if (onstack[i] == 2)
1284 stack_adjust = 1;
1286 vrotb(i+1);
1288 switch (vtop->type.t & VT_BTYPE) {
1289 case VT_STRUCT:
1290 /* allocate the necessary size on stack */
1291 o(0x48);
1292 oad(0xec81, size); /* sub $xxx, %rsp */
1293 /* generate structure store */
1294 r = get_reg(RC_INT);
1295 orex(1, r, 0, 0x89); /* mov %rsp, r */
1296 o(0xe0 + REG_VALUE(r));
1297 vset(&vtop->type, r | VT_LVAL, 0);
1298 vswap();
1299 vstore();
1300 break;
1302 case VT_LDOUBLE:
1303 gv(RC_ST0);
1304 oad(0xec8148, size); /* sub $xxx, %rsp */
1305 o(0x7cdb); /* fstpt 0(%rsp) */
1306 g(0x24);
1307 g(0x00);
1308 break;
1310 case VT_FLOAT:
1311 case VT_DOUBLE:
1312 assert(mode == x86_64_mode_sse);
1313 r = gv(RC_FLOAT);
1314 o(0x50); /* push $rax */
1315 /* movq %xmmN, (%rsp) */
1316 o(0xd60f66);
1317 o(0x04 + REG_VALUE(r)*8);
1318 o(0x24);
1319 break;
1321 default:
1322 assert(mode == x86_64_mode_integer);
1323 /* simple type */
1324 /* XXX: implicit cast ? */
1325 r = gv(RC_INT);
1326 orex(0,r,0,0x50 + REG_VALUE(r)); /* push r */
1327 break;
1329 args_size += size;
1331 vpop();
1332 --nb_args;
1333 onstack++;
1336 /* XXX This should be superfluous. */
1337 save_regs(0); /* save used temporary registers */
1339 /* then, we prepare register passing arguments.
1340 Note that we cannot set RDX and RCX in this loop because gv()
1341 may break these temporary registers. Let's use R10 and R11
1342 instead of them */
1343 assert(gen_reg <= REGN);
1344 assert(sse_reg <= 8);
1345 for(i = 0; i < nb_args; i++) {
1346 mode = classify_x86_64_arg(&vtop->type, &type, &size, &align, &reg_count);
1347 /* Alter stack entry type so that gv() knows how to treat it */
1348 vtop->type = type;
1349 if (mode == x86_64_mode_sse) {
1350 if (reg_count == 2) {
1351 sse_reg -= 2;
1352 gv(RC_FRET); /* Use pair load into xmm0 & xmm1 */
1353 if (sse_reg) { /* avoid redundant movaps %xmm0, %xmm0 */
1354 /* movaps %xmm0, %xmmN */
1355 o(0x280f);
1356 o(0xc0 + (sse_reg << 3));
1357 /* movaps %xmm1, %xmmN */
1358 o(0x280f);
1359 o(0xc1 + ((sse_reg+1) << 3));
1361 } else {
1362 assert(reg_count == 1);
1363 --sse_reg;
1364 /* Load directly to register */
1365 gv(RC_XMM0 << sse_reg);
1367 } else if (mode == x86_64_mode_integer) {
1368 /* simple type */
1369 /* XXX: implicit cast ? */
1370 int d;
1371 gen_reg -= reg_count;
1372 r = gv(RC_INT);
1373 d = arg_prepare_reg(gen_reg);
1374 orex(1,d,r,0x89); /* mov */
1375 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
1376 if (reg_count == 2) {
1377 d = arg_prepare_reg(gen_reg+1);
1378 orex(1,d,vtop->r2,0x89); /* mov */
1379 o(0xc0 + REG_VALUE(vtop->r2) * 8 + REG_VALUE(d));
1382 vtop--;
1384 assert(gen_reg == 0);
1385 assert(sse_reg == 0);
1387 /* We shouldn't have many operands on the stack anymore, but the
1388 call address itself is still there, and it might be in %eax
1389 (or edx/ecx) currently, which the below writes would clobber.
1390 So evict all remaining operands here. */
1391 save_regs(0);
1393 /* Copy R10 and R11 into RDX and RCX, respectively */
1394 if (nb_reg_args > 2) {
1395 o(0xd2894c); /* mov %r10, %rdx */
1396 if (nb_reg_args > 3) {
1397 o(0xd9894c); /* mov %r11, %rcx */
1401 if (vtop->type.ref->f.func_type != FUNC_NEW) /* implies FUNC_OLD or FUNC_ELLIPSIS */
1402 oad(0xb8, nb_sse_args < 8 ? nb_sse_args : 8); /* mov nb_sse_args, %eax */
1403 gcall_or_jmp(0);
1404 if (args_size)
1405 gadd_sp(args_size);
1406 /* other compilers don't clear the upper bits when returning char/short,
1407 TCC does so for convenience. When we'd stay purely within TCC compiled
1408 code we wouldn't need this, but for compatibility we have to extend.
1409 Ideally TCC wouldn't extend at return statements to not do double
1410 extensions, or would understand sub-int types during expression
1411 evaluation. */
1412 bt = vtop->type.ref->type.t & (VT_BTYPE | VT_UNSIGNED);
1413 if (bt == (VT_BYTE | VT_UNSIGNED) || (bt & VT_TYPE) == VT_BOOL)
1414 o(0xc0b60f); /* movzbl %al, %eax */
1415 else if (bt == VT_BYTE)
1416 o(0xc0be0f); /* movsbl %al, %eax */
1417 else if (bt == VT_SHORT)
1418 o(0x98); /* cwtl */
1419 else if (bt == (VT_SHORT | VT_UNSIGNED))
1420 o(0xc0b70f); /* movzwl %al, %eax */
1421 vtop--;
1425 #define FUNC_PROLOG_SIZE 11
1427 static void push_arg_reg(int i) {
1428 loc -= 8;
1429 gen_modrm64(0x89, arg_regs[i], VT_LOCAL, NULL, loc);
1432 /* generate function prolog of type 't' */
1433 void gfunc_prolog(CType *func_type)
1435 X86_64_Mode mode;
1436 int i, addr, align, size, reg_count;
1437 int param_addr = 0, reg_param_index, sse_param_index;
1438 Sym *sym;
1439 CType *type;
1441 sym = func_type->ref;
1442 addr = PTR_SIZE * 2;
1443 loc = 0;
1444 ind += FUNC_PROLOG_SIZE;
1445 func_sub_sp_offset = ind;
1446 func_ret_sub = 0;
1448 if (sym->f.func_type == FUNC_ELLIPSIS) {
1449 int seen_reg_num, seen_sse_num, seen_stack_size;
1450 seen_reg_num = seen_sse_num = 0;
1451 /* frame pointer and return address */
1452 seen_stack_size = PTR_SIZE * 2;
1453 /* count the number of seen parameters */
1454 sym = func_type->ref;
1455 while ((sym = sym->next) != NULL) {
1456 type = &sym->type;
1457 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1458 switch (mode) {
1459 default:
1460 stack_arg:
1461 seen_stack_size = ((seen_stack_size + align - 1) & -align) + size;
1462 break;
1464 case x86_64_mode_integer:
1465 if (seen_reg_num + reg_count > REGN)
1466 goto stack_arg;
1467 seen_reg_num += reg_count;
1468 break;
1470 case x86_64_mode_sse:
1471 if (seen_sse_num + reg_count > 8)
1472 goto stack_arg;
1473 seen_sse_num += reg_count;
1474 break;
1478 loc -= 16;
1479 /* movl $0x????????, -0x10(%rbp) */
1480 o(0xf045c7);
1481 gen_le32(seen_reg_num * 8);
1482 /* movl $0x????????, -0xc(%rbp) */
1483 o(0xf445c7);
1484 gen_le32(seen_sse_num * 16 + 48);
1485 /* movl $0x????????, -0x8(%rbp) */
1486 o(0xf845c7);
1487 gen_le32(seen_stack_size);
1489 /* save all register passing arguments */
1490 for (i = 0; i < 8; i++) {
1491 loc -= 16;
1492 if (!tcc_state->nosse) {
1493 o(0xd60f66); /* movq */
1494 gen_modrm(7 - i, VT_LOCAL, NULL, loc);
1496 /* movq $0, loc+8(%rbp) */
1497 o(0x85c748);
1498 gen_le32(loc + 8);
1499 gen_le32(0);
1501 for (i = 0; i < REGN; i++) {
1502 push_arg_reg(REGN-1-i);
1506 sym = func_type->ref;
1507 reg_param_index = 0;
1508 sse_param_index = 0;
1510 /* if the function returns a structure, then add an
1511 implicit pointer parameter */
1512 func_vt = sym->type;
1513 mode = classify_x86_64_arg(&func_vt, NULL, &size, &align, &reg_count);
1514 if (mode == x86_64_mode_memory) {
1515 push_arg_reg(reg_param_index);
1516 func_vc = loc;
1517 reg_param_index++;
1519 /* define parameters */
1520 while ((sym = sym->next) != NULL) {
1521 type = &sym->type;
1522 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1523 switch (mode) {
1524 case x86_64_mode_sse:
1525 if (tcc_state->nosse)
1526 tcc_error("SSE disabled but floating point arguments used");
1527 if (sse_param_index + reg_count <= 8) {
1528 /* save arguments passed by register */
1529 loc -= reg_count * 8;
1530 param_addr = loc;
1531 for (i = 0; i < reg_count; ++i) {
1532 o(0xd60f66); /* movq */
1533 gen_modrm(sse_param_index, VT_LOCAL, NULL, param_addr + i*8);
1534 ++sse_param_index;
1536 } else {
1537 addr = (addr + align - 1) & -align;
1538 param_addr = addr;
1539 addr += size;
1541 break;
1543 case x86_64_mode_memory:
1544 case x86_64_mode_x87:
1545 addr = (addr + align - 1) & -align;
1546 param_addr = addr;
1547 addr += size;
1548 break;
1550 case x86_64_mode_integer: {
1551 if (reg_param_index + reg_count <= REGN) {
1552 /* save arguments passed by register */
1553 loc -= reg_count * 8;
1554 param_addr = loc;
1555 for (i = 0; i < reg_count; ++i) {
1556 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, param_addr + i*8);
1557 ++reg_param_index;
1559 } else {
1560 addr = (addr + align - 1) & -align;
1561 param_addr = addr;
1562 addr += size;
1564 break;
1566 default: break; /* nothing to be done for x86_64_mode_none */
1568 sym_push(sym->v & ~SYM_FIELD, type,
1569 VT_LOCAL | lvalue_type(type->t), param_addr);
1572 #ifdef CONFIG_TCC_BCHECK
1573 /* leave some room for bound checking code */
1574 if (tcc_state->do_bounds_check) {
1575 func_bound_offset = lbounds_section->data_offset;
1576 func_bound_ind = ind;
1577 oad(0xb8, 0); /* lbound section pointer */
1578 o(0xc78948); /* mov %rax,%rdi ## first arg in %rdi, this must be ptr */
1579 oad(0xb8, 0); /* call to function */
1581 #endif
1584 /* generate function epilog */
1585 void gfunc_epilog(void)
1587 int v, saved_ind;
1589 #ifdef CONFIG_TCC_BCHECK
1590 if (tcc_state->do_bounds_check
1591 && func_bound_offset != lbounds_section->data_offset)
1593 addr_t saved_ind;
1594 addr_t *bounds_ptr;
1595 Sym *sym_data;
1597 /* add end of table info */
1598 bounds_ptr = section_ptr_add(lbounds_section, sizeof(addr_t));
1599 *bounds_ptr = 0;
1601 /* generate bound local allocation */
1602 sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
1603 func_bound_offset, lbounds_section->data_offset);
1604 saved_ind = ind;
1605 ind = func_bound_ind;
1606 greloca(cur_text_section, sym_data, ind + 1, R_X86_64_64, 0);
1607 ind = ind + 5 + 3;
1608 gen_static_call(TOK___bound_local_new);
1609 ind = saved_ind;
1611 /* generate bound check local freeing */
1612 o(0x5250); /* save returned value, if any */
1613 greloca(cur_text_section, sym_data, ind + 1, R_X86_64_64, 0);
1614 oad(0xb8, 0); /* mov xxx, %rax */
1615 o(0xc78948); /* mov %rax,%rdi # first arg in %rdi, this must be ptr */
1616 gen_static_call(TOK___bound_local_delete);
1617 o(0x585a); /* restore returned value, if any */
1619 #endif
1620 o(0xc9); /* leave */
1621 if (func_ret_sub == 0) {
1622 o(0xc3); /* ret */
1623 } else {
1624 o(0xc2); /* ret n */
1625 g(func_ret_sub);
1626 g(func_ret_sub >> 8);
1628 /* align local size to word & save local variables */
1629 v = (-loc + 15) & -16;
1630 saved_ind = ind;
1631 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1632 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1633 o(0xec8148); /* sub rsp, stacksize */
1634 gen_le32(v);
1635 ind = saved_ind;
1638 #endif /* not PE */
1640 ST_FUNC void gen_fill_nops(int bytes)
1642 while (bytes--)
1643 g(0x90);
1646 /* generate a jump to a label */
1647 int gjmp(int t)
1649 return gjmp2(0xe9, t);
1652 /* generate a jump to a fixed address */
1653 void gjmp_addr(int a)
1655 int r;
1656 r = a - ind - 2;
1657 if (r == (char)r) {
1658 g(0xeb);
1659 g(r);
1660 } else {
1661 oad(0xe9, a - ind - 5);
1665 ST_FUNC int gjmp_append(int n, int t)
1667 void *p;
1668 /* insert vtop->c jump list in t */
1669 if (n) {
1670 uint32_t n1 = n, n2;
1671 while ((n2 = read32le(p = cur_text_section->data + n1)))
1672 n1 = n2;
1673 write32le(p, t);
1674 t = n;
1676 return t;
1679 ST_FUNC int gjmp_cond(int op, int t)
1681 if (op & 0x100)
1683 /* This was a float compare. If the parity flag is set
1684 the result was unordered. For anything except != this
1685 means false and we don't jump (anding both conditions).
1686 For != this means true (oring both).
1687 Take care about inverting the test. We need to jump
1688 to our target if the result was unordered and test wasn't NE,
1689 otherwise if unordered we don't want to jump. */
1690 int v = vtop->cmp_r;
1691 op &= ~0x100;
1692 if (op ^ v ^ (v != TOK_NE))
1693 o(0x067a); /* jp +6 */
1694 else
1696 g(0x0f);
1697 t = gjmp2(0x8a, t); /* jp t */
1700 g(0x0f);
1701 t = gjmp2(op - 16, t);
1702 return t;
1705 /* generate an integer binary operation */
1706 void gen_opi(int op)
1708 int r, fr, opc, c;
1709 int ll, uu, cc;
1711 ll = is64_type(vtop[-1].type.t);
1712 uu = (vtop[-1].type.t & VT_UNSIGNED) != 0;
1713 cc = (vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST;
1715 switch(op) {
1716 case '+':
1717 case TOK_ADDC1: /* add with carry generation */
1718 opc = 0;
1719 gen_op8:
1720 if (cc && (!ll || (int)vtop->c.i == vtop->c.i)) {
1721 /* constant case */
1722 vswap();
1723 r = gv(RC_INT);
1724 vswap();
1725 c = vtop->c.i;
1726 if (c == (char)c) {
1727 /* XXX: generate inc and dec for smaller code ? */
1728 orex(ll, r, 0, 0x83);
1729 o(0xc0 | (opc << 3) | REG_VALUE(r));
1730 g(c);
1731 } else {
1732 orex(ll, r, 0, 0x81);
1733 oad(0xc0 | (opc << 3) | REG_VALUE(r), c);
1735 } else {
1736 gv2(RC_INT, RC_INT);
1737 r = vtop[-1].r;
1738 fr = vtop[0].r;
1739 orex(ll, r, fr, (opc << 3) | 0x01);
1740 o(0xc0 + REG_VALUE(r) + REG_VALUE(fr) * 8);
1742 vtop--;
1743 if (op >= TOK_ULT && op <= TOK_GT)
1744 vset_VT_CMP(op);
1745 break;
1746 case '-':
1747 case TOK_SUBC1: /* sub with carry generation */
1748 opc = 5;
1749 goto gen_op8;
1750 case TOK_ADDC2: /* add with carry use */
1751 opc = 2;
1752 goto gen_op8;
1753 case TOK_SUBC2: /* sub with carry use */
1754 opc = 3;
1755 goto gen_op8;
1756 case '&':
1757 opc = 4;
1758 goto gen_op8;
1759 case '^':
1760 opc = 6;
1761 goto gen_op8;
1762 case '|':
1763 opc = 1;
1764 goto gen_op8;
1765 case '*':
1766 gv2(RC_INT, RC_INT);
1767 r = vtop[-1].r;
1768 fr = vtop[0].r;
1769 orex(ll, fr, r, 0xaf0f); /* imul fr, r */
1770 o(0xc0 + REG_VALUE(fr) + REG_VALUE(r) * 8);
1771 vtop--;
1772 break;
1773 case TOK_SHL:
1774 opc = 4;
1775 goto gen_shift;
1776 case TOK_SHR:
1777 opc = 5;
1778 goto gen_shift;
1779 case TOK_SAR:
1780 opc = 7;
1781 gen_shift:
1782 opc = 0xc0 | (opc << 3);
1783 if (cc) {
1784 /* constant case */
1785 vswap();
1786 r = gv(RC_INT);
1787 vswap();
1788 orex(ll, r, 0, 0xc1); /* shl/shr/sar $xxx, r */
1789 o(opc | REG_VALUE(r));
1790 g(vtop->c.i & (ll ? 63 : 31));
1791 } else {
1792 /* we generate the shift in ecx */
1793 gv2(RC_INT, RC_RCX);
1794 r = vtop[-1].r;
1795 orex(ll, r, 0, 0xd3); /* shl/shr/sar %cl, r */
1796 o(opc | REG_VALUE(r));
1798 vtop--;
1799 break;
1800 case TOK_UDIV:
1801 case TOK_UMOD:
1802 uu = 1;
1803 goto divmod;
1804 case '/':
1805 case '%':
1806 case TOK_PDIV:
1807 uu = 0;
1808 divmod:
1809 /* first operand must be in eax */
1810 /* XXX: need better constraint for second operand */
1811 gv2(RC_RAX, RC_RCX);
1812 r = vtop[-1].r;
1813 fr = vtop[0].r;
1814 vtop--;
1815 save_reg(TREG_RDX);
1816 orex(ll, 0, 0, uu ? 0xd231 : 0x99); /* xor %edx,%edx : cqto */
1817 orex(ll, fr, 0, 0xf7); /* div fr, %eax */
1818 o((uu ? 0xf0 : 0xf8) + REG_VALUE(fr));
1819 if (op == '%' || op == TOK_UMOD)
1820 r = TREG_RDX;
1821 else
1822 r = TREG_RAX;
1823 vtop->r = r;
1824 break;
1825 default:
1826 opc = 7;
1827 goto gen_op8;
1831 void gen_opl(int op)
1833 gen_opi(op);
1836 /* generate a floating point operation 'v = t1 op t2' instruction. The
1837 two operands are guaranteed to have the same floating point type */
1838 /* XXX: need to use ST1 too */
1839 void gen_opf(int op)
1841 int a, ft, fc, swapped, r;
1842 int float_type =
1843 (vtop->type.t & VT_BTYPE) == VT_LDOUBLE ? RC_ST0 : RC_FLOAT;
1845 /* convert constants to memory references */
1846 if ((vtop[-1].r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
1847 vswap();
1848 gv(float_type);
1849 vswap();
1851 if ((vtop[0].r & (VT_VALMASK | VT_LVAL)) == VT_CONST)
1852 gv(float_type);
1854 /* must put at least one value in the floating point register */
1855 if ((vtop[-1].r & VT_LVAL) &&
1856 (vtop[0].r & VT_LVAL)) {
1857 vswap();
1858 gv(float_type);
1859 vswap();
1861 swapped = 0;
1862 /* swap the stack if needed so that t1 is the register and t2 is
1863 the memory reference */
1864 if (vtop[-1].r & VT_LVAL) {
1865 vswap();
1866 swapped = 1;
1868 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1869 if (op >= TOK_ULT && op <= TOK_GT) {
1870 /* load on stack second operand */
1871 load(TREG_ST0, vtop);
1872 save_reg(TREG_RAX); /* eax is used by FP comparison code */
1873 if (op == TOK_GE || op == TOK_GT)
1874 swapped = !swapped;
1875 else if (op == TOK_EQ || op == TOK_NE)
1876 swapped = 0;
1877 if (swapped)
1878 o(0xc9d9); /* fxch %st(1) */
1879 if (op == TOK_EQ || op == TOK_NE)
1880 o(0xe9da); /* fucompp */
1881 else
1882 o(0xd9de); /* fcompp */
1883 o(0xe0df); /* fnstsw %ax */
1884 if (op == TOK_EQ) {
1885 o(0x45e480); /* and $0x45, %ah */
1886 o(0x40fC80); /* cmp $0x40, %ah */
1887 } else if (op == TOK_NE) {
1888 o(0x45e480); /* and $0x45, %ah */
1889 o(0x40f480); /* xor $0x40, %ah */
1890 op = TOK_NE;
1891 } else if (op == TOK_GE || op == TOK_LE) {
1892 o(0x05c4f6); /* test $0x05, %ah */
1893 op = TOK_EQ;
1894 } else {
1895 o(0x45c4f6); /* test $0x45, %ah */
1896 op = TOK_EQ;
1898 vtop--;
1899 vset_VT_CMP(op);
1900 } else {
1901 /* no memory reference possible for long double operations */
1902 load(TREG_ST0, vtop);
1903 swapped = !swapped;
1905 switch(op) {
1906 default:
1907 case '+':
1908 a = 0;
1909 break;
1910 case '-':
1911 a = 4;
1912 if (swapped)
1913 a++;
1914 break;
1915 case '*':
1916 a = 1;
1917 break;
1918 case '/':
1919 a = 6;
1920 if (swapped)
1921 a++;
1922 break;
1924 ft = vtop->type.t;
1925 fc = vtop->c.i;
1926 o(0xde); /* fxxxp %st, %st(1) */
1927 o(0xc1 + (a << 3));
1928 vtop--;
1930 } else {
1931 if (op >= TOK_ULT && op <= TOK_GT) {
1932 /* if saved lvalue, then we must reload it */
1933 r = vtop->r;
1934 fc = vtop->c.i;
1935 if ((r & VT_VALMASK) == VT_LLOCAL) {
1936 SValue v1;
1937 r = get_reg(RC_INT);
1938 v1.type.t = VT_PTR;
1939 v1.r = VT_LOCAL | VT_LVAL;
1940 v1.c.i = fc;
1941 load(r, &v1);
1942 fc = 0;
1945 if (op == TOK_EQ || op == TOK_NE) {
1946 swapped = 0;
1947 } else {
1948 if (op == TOK_LE || op == TOK_LT)
1949 swapped = !swapped;
1950 if (op == TOK_LE || op == TOK_GE) {
1951 op = 0x93; /* setae */
1952 } else {
1953 op = 0x97; /* seta */
1957 if (swapped) {
1958 gv(RC_FLOAT);
1959 vswap();
1961 assert(!(vtop[-1].r & VT_LVAL));
1963 if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
1964 o(0x66);
1965 if (op == TOK_EQ || op == TOK_NE)
1966 o(0x2e0f); /* ucomisd */
1967 else
1968 o(0x2f0f); /* comisd */
1970 if (vtop->r & VT_LVAL) {
1971 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
1972 } else {
1973 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
1976 vtop--;
1977 vset_VT_CMP(op | 0x100);
1978 vtop->cmp_r = op;
1979 } else {
1980 assert((vtop->type.t & VT_BTYPE) != VT_LDOUBLE);
1981 switch(op) {
1982 default:
1983 case '+':
1984 a = 0;
1985 break;
1986 case '-':
1987 a = 4;
1988 break;
1989 case '*':
1990 a = 1;
1991 break;
1992 case '/':
1993 a = 6;
1994 break;
1996 ft = vtop->type.t;
1997 fc = vtop->c.i;
1998 assert((ft & VT_BTYPE) != VT_LDOUBLE);
2000 r = vtop->r;
2001 /* if saved lvalue, then we must reload it */
2002 if ((vtop->r & VT_VALMASK) == VT_LLOCAL) {
2003 SValue v1;
2004 r = get_reg(RC_INT);
2005 v1.type.t = VT_PTR;
2006 v1.r = VT_LOCAL | VT_LVAL;
2007 v1.c.i = fc;
2008 load(r, &v1);
2009 fc = 0;
2012 assert(!(vtop[-1].r & VT_LVAL));
2013 if (swapped) {
2014 assert(vtop->r & VT_LVAL);
2015 gv(RC_FLOAT);
2016 vswap();
2019 if ((ft & VT_BTYPE) == VT_DOUBLE) {
2020 o(0xf2);
2021 } else {
2022 o(0xf3);
2024 o(0x0f);
2025 o(0x58 + a);
2027 if (vtop->r & VT_LVAL) {
2028 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
2029 } else {
2030 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
2033 vtop--;
2038 /* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
2039 and 'long long' cases. */
2040 void gen_cvt_itof(int t)
2042 if ((t & VT_BTYPE) == VT_LDOUBLE) {
2043 save_reg(TREG_ST0);
2044 gv(RC_INT);
2045 if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
2046 /* signed long long to float/double/long double (unsigned case
2047 is handled generically) */
2048 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2049 o(0x242cdf); /* fildll (%rsp) */
2050 o(0x08c48348); /* add $8, %rsp */
2051 } else if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2052 (VT_INT | VT_UNSIGNED)) {
2053 /* unsigned int to float/double/long double */
2054 o(0x6a); /* push $0 */
2055 g(0x00);
2056 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2057 o(0x242cdf); /* fildll (%rsp) */
2058 o(0x10c48348); /* add $16, %rsp */
2059 } else {
2060 /* int to float/double/long double */
2061 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2062 o(0x2404db); /* fildl (%rsp) */
2063 o(0x08c48348); /* add $8, %rsp */
2065 vtop->r = TREG_ST0;
2066 } else {
2067 int r = get_reg(RC_FLOAT);
2068 gv(RC_INT);
2069 o(0xf2 + ((t & VT_BTYPE) == VT_FLOAT?1:0));
2070 if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2071 (VT_INT | VT_UNSIGNED) ||
2072 (vtop->type.t & VT_BTYPE) == VT_LLONG) {
2073 o(0x48); /* REX */
2075 o(0x2a0f);
2076 o(0xc0 + (vtop->r & VT_VALMASK) + REG_VALUE(r)*8); /* cvtsi2sd */
2077 vtop->r = r;
2081 /* convert from one floating point type to another */
2082 void gen_cvt_ftof(int t)
2084 int ft, bt, tbt;
2086 ft = vtop->type.t;
2087 bt = ft & VT_BTYPE;
2088 tbt = t & VT_BTYPE;
2090 if (bt == VT_FLOAT) {
2091 gv(RC_FLOAT);
2092 if (tbt == VT_DOUBLE) {
2093 o(0x140f); /* unpcklps */
2094 o(0xc0 + REG_VALUE(vtop->r)*9);
2095 o(0x5a0f); /* cvtps2pd */
2096 o(0xc0 + REG_VALUE(vtop->r)*9);
2097 } else if (tbt == VT_LDOUBLE) {
2098 save_reg(RC_ST0);
2099 /* movss %xmm0,-0x10(%rsp) */
2100 o(0x110ff3);
2101 o(0x44 + REG_VALUE(vtop->r)*8);
2102 o(0xf024);
2103 o(0xf02444d9); /* flds -0x10(%rsp) */
2104 vtop->r = TREG_ST0;
2106 } else if (bt == VT_DOUBLE) {
2107 gv(RC_FLOAT);
2108 if (tbt == VT_FLOAT) {
2109 o(0x140f66); /* unpcklpd */
2110 o(0xc0 + REG_VALUE(vtop->r)*9);
2111 o(0x5a0f66); /* cvtpd2ps */
2112 o(0xc0 + REG_VALUE(vtop->r)*9);
2113 } else if (tbt == VT_LDOUBLE) {
2114 save_reg(RC_ST0);
2115 /* movsd %xmm0,-0x10(%rsp) */
2116 o(0x110ff2);
2117 o(0x44 + REG_VALUE(vtop->r)*8);
2118 o(0xf024);
2119 o(0xf02444dd); /* fldl -0x10(%rsp) */
2120 vtop->r = TREG_ST0;
2122 } else {
2123 int r;
2124 gv(RC_ST0);
2125 r = get_reg(RC_FLOAT);
2126 if (tbt == VT_DOUBLE) {
2127 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
2128 /* movsd -0x10(%rsp),%xmm0 */
2129 o(0x100ff2);
2130 o(0x44 + REG_VALUE(r)*8);
2131 o(0xf024);
2132 vtop->r = r;
2133 } else if (tbt == VT_FLOAT) {
2134 o(0xf0245cd9); /* fstps -0x10(%rsp) */
2135 /* movss -0x10(%rsp),%xmm0 */
2136 o(0x100ff3);
2137 o(0x44 + REG_VALUE(r)*8);
2138 o(0xf024);
2139 vtop->r = r;
2144 /* convert fp to int 't' type */
2145 void gen_cvt_ftoi(int t)
2147 int ft, bt, size, r;
2148 ft = vtop->type.t;
2149 bt = ft & VT_BTYPE;
2150 if (bt == VT_LDOUBLE) {
2151 gen_cvt_ftof(VT_DOUBLE);
2152 bt = VT_DOUBLE;
2155 gv(RC_FLOAT);
2156 if (t != VT_INT)
2157 size = 8;
2158 else
2159 size = 4;
2161 r = get_reg(RC_INT);
2162 if (bt == VT_FLOAT) {
2163 o(0xf3);
2164 } else if (bt == VT_DOUBLE) {
2165 o(0xf2);
2166 } else {
2167 assert(0);
2169 orex(size == 8, r, 0, 0x2c0f); /* cvttss2si or cvttsd2si */
2170 o(0xc0 + REG_VALUE(vtop->r) + REG_VALUE(r)*8);
2171 vtop->r = r;
2174 /* computed goto support */
2175 void ggoto(void)
2177 gcall_or_jmp(1);
2178 vtop--;
2181 /* Save the stack pointer onto the stack and return the location of its address */
2182 ST_FUNC void gen_vla_sp_save(int addr) {
2183 /* mov %rsp,addr(%rbp)*/
2184 gen_modrm64(0x89, TREG_RSP, VT_LOCAL, NULL, addr);
2187 /* Restore the SP from a location on the stack */
2188 ST_FUNC void gen_vla_sp_restore(int addr) {
2189 gen_modrm64(0x8b, TREG_RSP, VT_LOCAL, NULL, addr);
2192 #ifdef TCC_TARGET_PE
2193 /* Save result of gen_vla_alloc onto the stack */
2194 ST_FUNC void gen_vla_result(int addr) {
2195 /* mov %rax,addr(%rbp)*/
2196 gen_modrm64(0x89, TREG_RAX, VT_LOCAL, NULL, addr);
2198 #endif
2200 /* Subtract from the stack pointer, and push the resulting value onto the stack */
2201 ST_FUNC void gen_vla_alloc(CType *type, int align) {
2202 #ifdef TCC_TARGET_PE
2203 /* alloca does more than just adjust %rsp on Windows */
2204 vpush_global_sym(&func_old_type, TOK_alloca);
2205 vswap(); /* Move alloca ref past allocation size */
2206 gfunc_call(1);
2207 #else
2208 int r;
2209 r = gv(RC_INT); /* allocation size */
2210 /* sub r,%rsp */
2211 o(0x2b48);
2212 o(0xe0 | REG_VALUE(r));
2213 /* We align to 16 bytes rather than align */
2214 /* and ~15, %rsp */
2215 o(0xf0e48348);
2216 vpop();
2217 #endif
2221 /* end of x86-64 code generator */
2222 /*************************************************************/
2223 #endif /* ! TARGET_DEFS_ONLY */
2224 /******************************************************/