2 * A64 code generator for TCC
4 * Copyright (c) 2014-2015 Edmund Grimley Evans
6 * Copying and distribution of this file, with or without modification,
7 * are permitted in any medium without royalty provided the copyright
8 * notice and this notice are preserved. This file is offered as-is,
9 * without any warranty.
12 #ifdef TARGET_DEFS_ONLY
14 // Number of registers available to allocator:
15 #define NB_REGS 28 // x0-x18, x30, v0-v7
17 #define TREG_R(x) (x) // x = 0..18
19 #define TREG_F(x) (x + 20) // x = 0..7
21 // Register classes sorted from more general to more precise:
22 #define RC_INT (1 << 0)
23 #define RC_FLOAT (1 << 1)
24 #define RC_R(x) (1 << (2 + (x))) // x = 0..18
25 #define RC_R30 (1 << 21)
26 #define RC_F(x) (1 << (22 + (x))) // x = 0..7
28 #define RC_IRET (RC_R(0)) // int return register class
29 #define RC_FRET (RC_F(0)) // float return register class
31 #define REG_IRET (TREG_R(0)) // int return register number
32 #define REG_FRET (TREG_F(0)) // float return register number
36 #define LDOUBLE_SIZE 16
37 #define LDOUBLE_ALIGN 16
41 #define CHAR_IS_UNSIGNED
43 /* define if return values need to be extended explicitely
44 at caller side (for interfacing with non-TCC compilers) */
46 /******************************************************/
47 #else /* ! TARGET_DEFS_ONLY */
48 /******************************************************/
53 ST_DATA
const int reg_classes
[NB_REGS
] = {
73 RC_R30
, // not in RC_INT as we make special use of x30
84 #define IS_FREG(x) ((x) >= TREG_F(0))
86 static uint32_t intr(int r
)
88 assert(TREG_R(0) <= r
&& r
<= TREG_R30
);
89 return r
< TREG_R30
? r
: 30;
92 static uint32_t fltr(int r
)
94 assert(TREG_F(0) <= r
&& r
<= TREG_F(7));
98 // Add an instruction to text section:
99 ST_FUNC
void o(unsigned int c
)
104 if (ind1
> cur_text_section
->data_allocated
)
105 section_realloc(cur_text_section
, ind1
);
106 write32le(cur_text_section
->data
+ ind
, c
);
110 static int arm64_encode_bimm64(uint64_t x
)
120 if (x
>> 2 == (x
& (((uint64_t)1 << (64 - 2)) - 1)))
121 rep
= 2, x
&= ((uint64_t)1 << 2) - 1;
122 else if (x
>> 4 == (x
& (((uint64_t)1 << (64 - 4)) - 1)))
123 rep
= 4, x
&= ((uint64_t)1 << 4) - 1;
124 else if (x
>> 8 == (x
& (((uint64_t)1 << (64 - 8)) - 1)))
125 rep
= 8, x
&= ((uint64_t)1 << 8) - 1;
126 else if (x
>> 16 == (x
& (((uint64_t)1 << (64 - 16)) - 1)))
127 rep
= 16, x
&= ((uint64_t)1 << 16) - 1;
128 else if (x
>> 32 == (x
& (((uint64_t)1 << (64 - 32)) - 1)))
129 rep
= 32, x
&= ((uint64_t)1 << 32) - 1;
134 if (!(x
& (((uint64_t)1 << 32) - 1))) x
>>= 32, pos
+= 32;
135 if (!(x
& (((uint64_t)1 << 16) - 1))) x
>>= 16, pos
+= 16;
136 if (!(x
& (((uint64_t)1 << 8) - 1))) x
>>= 8, pos
+= 8;
137 if (!(x
& (((uint64_t)1 << 4) - 1))) x
>>= 4, pos
+= 4;
138 if (!(x
& (((uint64_t)1 << 2) - 1))) x
>>= 2, pos
+= 2;
139 if (!(x
& (((uint64_t)1 << 1) - 1))) x
>>= 1, pos
+= 1;
142 if (!(~x
& (((uint64_t)1 << 32) - 1))) x
>>= 32, len
+= 32;
143 if (!(~x
& (((uint64_t)1 << 16) - 1))) x
>>= 16, len
+= 16;
144 if (!(~x
& (((uint64_t)1 << 8) - 1))) x
>>= 8, len
+= 8;
145 if (!(~x
& (((uint64_t)1 << 4) - 1))) x
>>= 4, len
+= 4;
146 if (!(~x
& (((uint64_t)1 << 2) - 1))) x
>>= 2, len
+= 2;
147 if (!(~x
& (((uint64_t)1 << 1) - 1))) x
>>= 1, len
+= 1;
152 pos
= (pos
+ len
) & (rep
- 1);
155 return ((0x1000 & rep
<< 6) | (((rep
- 1) ^ 31) << 1 & 63) |
156 ((rep
- pos
) & (rep
- 1)) << 6 | (len
- 1));
159 static uint32_t arm64_movi(int r
, uint64_t x
)
164 return 0x52800000 | r
| x
<< 5; // movz w(r),#(x)
165 if (!(x
& ~(m
<< 16)))
166 return 0x52a00000 | r
| x
>> 11; // movz w(r),#(x >> 16),lsl #16
167 if (!(x
& ~(m
<< 32)))
168 return 0xd2c00000 | r
| x
>> 27; // movz x(r),#(x >> 32),lsl #32
169 if (!(x
& ~(m
<< 48)))
170 return 0xd2e00000 | r
| x
>> 43; // movz x(r),#(x >> 48),lsl #48
171 if ((x
& ~m
) == m
<< 16)
172 return (0x12800000 | r
|
173 (~x
<< 5 & 0x1fffe0)); // movn w(r),#(~x)
174 if ((x
& ~(m
<< 16)) == m
)
175 return (0x12a00000 | r
|
176 (~x
>> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
178 return (0x92800000 | r
|
179 (~x
<< 5 & 0x1fffe0)); // movn x(r),#(~x)
181 return (0x92a00000 | r
|
182 (~x
>> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
184 return (0x92c00000 | r
|
185 (~x
>> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
187 return (0x92e00000 | r
|
188 (~x
>> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
189 if (!(x
>> 32) && (e
= arm64_encode_bimm64(x
| x
<< 32)) >= 0)
190 return 0x320003e0 | r
| (uint32_t)e
<< 10; // movi w(r),#(x)
191 if ((e
= arm64_encode_bimm64(x
)) >= 0)
192 return 0xb20003e0 | r
| (uint32_t)e
<< 10; // movi x(r),#(x)
196 static void arm64_movimm(int r
, uint64_t x
)
199 if ((i
= arm64_movi(r
, x
)))
200 o(i
); // a single MOV
202 // MOVZ/MOVN and 1-3 MOVKs
204 uint32_t mov1
= 0xd2800000; // movz
206 for (i
= 0; i
< 64; i
+= 16) {
207 z
+= !(x
>> i
& 0xffff);
208 m
+= !(~x
>> i
& 0xffff);
212 mov1
= 0x92800000; // movn
214 for (i
= 0; i
< 64; i
+= 16)
215 if (x1
>> i
& 0xffff) {
216 o(mov1
| r
| (x1
>> i
& 0xffff) << 5 | i
<< 17);
217 // movz/movn x(r),#(*),lsl #(i)
220 for (i
+= 16; i
< 64; i
+= 16)
221 if (x1
>> i
& 0xffff)
222 o(0xf2800000 | r
| (x
>> i
& 0xffff) << 5 | i
<< 17);
223 // movk x(r),#(*),lsl #(i)
227 // Patch all branches in list pointed to by t to branch to a:
228 ST_FUNC
void gsym_addr(int t_
, int a_
)
233 unsigned char *ptr
= cur_text_section
->data
+ t
;
234 uint32_t next
= read32le(ptr
);
235 if (a
- t
+ 0x8000000 >= 0x10000000)
236 tcc_error("branch out of range");
237 write32le(ptr
, (a
- t
== 4 ? 0xd503201f : // nop
238 0x14000000 | ((a
- t
) >> 2 & 0x3ffffff))); // b
243 static int arm64_type_size(int t
)
246 * case values are in increasing order (from 1 to 11).
247 * which 'may' help compiler optimizers. See tcc.h
249 switch (t
& VT_BTYPE
) {
250 case VT_BYTE
: return 0;
251 case VT_SHORT
: return 1;
252 case VT_INT
: return 2;
253 case VT_LLONG
: return 3;
254 case VT_PTR
: return 3;
255 case VT_FUNC
: return 3;
256 case VT_STRUCT
: return 3;
257 case VT_FLOAT
: return 2;
258 case VT_DOUBLE
: return 3;
259 case VT_LDOUBLE
: return 4;
260 case VT_BOOL
: return 0;
266 static void arm64_spoff(int reg
, uint64_t off
)
268 uint32_t sub
= off
>> 63;
272 o(0x910003e0 | sub
<< 30 | reg
| off
<< 10);
273 // (add|sub) x(reg),sp,#(off)
275 arm64_movimm(30, off
); // use x30 for offset
276 o(0x8b3e63e0 | sub
<< 30 | reg
); // (add|sub) x(reg),sp,x30
280 static void arm64_ldrx(int sg
, int sz_
, int dst
, int bas
, uint64_t off
)
285 if (!(off
& ~((uint32_t)0xfff << sz
)))
286 o(0x39400000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
287 (uint32_t)!!sg
<< 23 | sz
<< 30); // ldr(*) x(dst),[x(bas),#(off)]
288 else if (off
< 256 || -off
<= 256)
289 o(0x38400000 | dst
| bas
<< 5 | (off
& 511) << 12 |
290 (uint32_t)!!sg
<< 23 | sz
<< 30); // ldur(*) x(dst),[x(bas),#(off)]
292 arm64_movimm(30, off
); // use x30 for offset
293 o(0x38206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
294 (uint32_t)(!!sg
+ 1) << 22 | sz
<< 30); // ldr(*) x(dst),[x(bas),x30]
298 static void arm64_ldrv(int sz_
, int dst
, int bas
, uint64_t off
)
301 if (!(off
& ~((uint32_t)0xfff << sz
)))
302 o(0x3d400000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
303 (sz
& 4) << 21 | (sz
& 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
304 else if (off
< 256 || -off
<= 256)
305 o(0x3c400000 | dst
| bas
<< 5 | (off
& 511) << 12 |
306 (sz
& 4) << 21 | (sz
& 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
308 arm64_movimm(30, off
); // use x30 for offset
309 o(0x3c606800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
310 sz
<< 30 | (sz
& 4) << 21); // ldr (s|d|q)(dst),[x(bas),x30]
314 static void arm64_ldrs(int reg_
, int size
)
317 // Use x30 for intermediate value in some cases.
319 default: assert(0); break;
321 arm64_ldrx(0, 0, reg
, reg
, 0);
324 arm64_ldrx(0, 1, reg
, reg
, 0);
327 arm64_ldrx(0, 1, 30, reg
, 0);
328 arm64_ldrx(0, 0, reg
, reg
, 2);
329 o(0x2a0043c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #16
332 arm64_ldrx(0, 2, reg
, reg
, 0);
335 arm64_ldrx(0, 2, 30, reg
, 0);
336 arm64_ldrx(0, 0, reg
, reg
, 4);
337 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
340 arm64_ldrx(0, 2, 30, reg
, 0);
341 arm64_ldrx(0, 1, reg
, reg
, 4);
342 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
345 arm64_ldrx(0, 2, 30, reg
, 0);
346 arm64_ldrx(0, 2, reg
, reg
, 3);
347 o(0x53087c00 | reg
| reg
<< 5); // lsr w(reg), w(reg), #8
348 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
351 arm64_ldrx(0, 3, reg
, reg
, 0);
354 arm64_ldrx(0, 0, reg
+ 1, reg
, 8);
355 arm64_ldrx(0, 3, reg
, reg
, 0);
358 arm64_ldrx(0, 1, reg
+ 1, reg
, 8);
359 arm64_ldrx(0, 3, reg
, reg
, 0);
362 arm64_ldrx(0, 2, reg
+ 1, reg
, 7);
363 o(0x53087c00 | (reg
+1) | (reg
+1) << 5); // lsr w(reg+1), w(reg+1), #8
364 arm64_ldrx(0, 3, reg
, reg
, 0);
367 arm64_ldrx(0, 2, reg
+ 1, reg
, 8);
368 arm64_ldrx(0, 3, reg
, reg
, 0);
371 arm64_ldrx(0, 3, reg
+ 1, reg
, 5);
372 o(0xd358fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #24
373 arm64_ldrx(0, 3, reg
, reg
, 0);
376 arm64_ldrx(0, 3, reg
+ 1, reg
, 6);
377 o(0xd350fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #16
378 arm64_ldrx(0, 3, reg
, reg
, 0);
381 arm64_ldrx(0, 3, reg
+ 1, reg
, 7);
382 o(0xd348fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #8
383 arm64_ldrx(0, 3, reg
, reg
, 0);
386 o(0xa9400000 | reg
| (reg
+1) << 10 | reg
<< 5);
387 // ldp x(reg),x(reg+1),[x(reg)]
392 static void arm64_strx(int sz_
, int dst
, int bas
, uint64_t off
)
395 if (!(off
& ~((uint32_t)0xfff << sz
)))
396 o(0x39000000 | dst
| bas
<< 5 | off
<< (10 - sz
) | sz
<< 30);
397 // str(*) x(dst),[x(bas],#(off)]
398 else if (off
< 256 || -off
<= 256)
399 o(0x38000000 | dst
| bas
<< 5 | (off
& 511) << 12 | sz
<< 30);
400 // stur(*) x(dst),[x(bas],#(off)]
402 arm64_movimm(30, off
); // use x30 for offset
403 o(0x38206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 | sz
<< 30);
404 // str(*) x(dst),[x(bas),x30]
408 static void arm64_strv(int sz_
, int dst
, int bas
, uint64_t off
)
411 if (!(off
& ~((uint32_t)0xfff << sz
)))
412 o(0x3d000000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
413 (sz
& 4) << 21 | (sz
& 3) << 30); // str (s|d|q)(dst),[x(bas),#(off)]
414 else if (off
< 256 || -off
<= 256)
415 o(0x3c000000 | dst
| bas
<< 5 | (off
& 511) << 12 |
416 (sz
& 4) << 21 | (sz
& 3) << 30); // stur (s|d|q)(dst),[x(bas),#(off)]
418 arm64_movimm(30, off
); // use x30 for offset
419 o(0x3c206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
420 sz
<< 30 | (sz
& 4) << 21); // str (s|d|q)(dst),[x(bas),x30]
424 static void arm64_sym(int r
, Sym
*sym
, unsigned long addend
)
426 // Currently TCC's linker does not generate COPY relocations for
427 // STT_OBJECTs when tcc is invoked with "-run". This typically
428 // results in "R_AARCH64_ADR_PREL_PG_HI21 relocation failed" when
429 // a program refers to stdin. A workaround is to avoid that
430 // relocation and use only relocations with unlimited range.
433 if (avoid_adrp
|| sym
->a
.weak
) {
434 // (GCC uses a R_AARCH64_ABS64 in this case.)
435 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G0_NC
, addend
);
436 o(0xd2800000 | r
); // mov x(rt),#0,lsl #0
437 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G1_NC
, addend
);
438 o(0xf2a00000 | r
); // movk x(rt),#0,lsl #16
439 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G2_NC
, addend
);
440 o(0xf2c00000 | r
); // movk x(rt),#0,lsl #32
441 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G3
, addend
);
442 o(0xf2e00000 | r
); // movk x(rt),#0,lsl #48
445 greloca(cur_text_section
, sym
, ind
, R_AARCH64_ADR_PREL_PG_HI21
, addend
);
447 greloca(cur_text_section
, sym
, ind
, R_AARCH64_ADD_ABS_LO12_NC
, addend
);
448 o(0x91000000 | r
| r
<< 5);
452 static void arm64_load_cmp(int r
, SValue
*sv
);
454 ST_FUNC
void load(int r
, SValue
*sv
)
456 int svtt
= sv
->type
.t
;
458 int svrv
= svr
& VT_VALMASK
;
459 uint64_t svcul
= (uint32_t)sv
->c
.i
;
460 svcul
= svcul
>> 31 & 1 ? svcul
- ((uint64_t)1 << 32) : svcul
;
462 if (svr
== (VT_LOCAL
| VT_LVAL
)) {
464 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 29, svcul
);
466 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
471 if ((svr
& ~VT_VALMASK
) == VT_LVAL
&& svrv
< VT_CONST
) {
473 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), intr(svrv
), 0);
475 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
476 intr(r
), intr(svrv
), 0);
480 if (svr
== (VT_CONST
| VT_LVAL
| VT_SYM
)) {
481 arm64_sym(30, sv
->sym
, svcul
); // use x30 for address
483 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 30, 0);
485 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
490 if (svr
== (VT_CONST
| VT_SYM
)) {
491 arm64_sym(intr(r
), sv
->sym
, svcul
);
495 if (svr
== VT_CONST
) {
496 if ((svtt
& VT_BTYPE
) != VT_VOID
)
497 arm64_movimm(intr(r
), arm64_type_size(svtt
) == 3 ?
498 sv
->c
.i
: (uint32_t)svcul
);
502 if (svr
< VT_CONST
) {
503 if (IS_FREG(r
) && IS_FREG(svr
))
504 if (svtt
== VT_LDOUBLE
)
505 o(0x4ea01c00 | fltr(r
) | fltr(svr
) << 5);
506 // mov v(r).16b,v(svr).16b
508 o(0x1e604000 | fltr(r
) | fltr(svr
) << 5); // fmov d(r),d(svr)
509 else if (!IS_FREG(r
) && !IS_FREG(svr
))
510 o(0xaa0003e0 | intr(r
) | intr(svr
) << 16); // mov x(r),x(svr)
516 if (svr
== VT_LOCAL
) {
518 o(0xd10003a0 | intr(r
) | -svcul
<< 10); // sub x(r),x29,#...
520 arm64_movimm(30, -svcul
); // use x30 for offset
521 o(0xcb0003a0 | intr(r
) | (uint32_t)30 << 16); // sub x(r),x29,x30
526 if (svr
== VT_JMP
|| svr
== VT_JMPI
) {
527 int t
= (svr
== VT_JMPI
);
528 arm64_movimm(intr(r
), t
);
529 o(0x14000002); // b .+8
531 arm64_movimm(intr(r
), t
^ 1);
535 if (svr
== (VT_LLOCAL
| VT_LVAL
)) {
536 arm64_ldrx(0, 3, 30, 29, svcul
); // use x30 for offset
538 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 30, 0);
540 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
546 arm64_load_cmp(r
, sv
);
550 printf("load(%x, (%x, %x, %llx))\n", r
, svtt
, sv
->r
, (long long)svcul
);
554 ST_FUNC
void store(int r
, SValue
*sv
)
556 int svtt
= sv
->type
.t
;
558 int svrv
= svr
& VT_VALMASK
;
559 uint64_t svcul
= (uint32_t)sv
->c
.i
;
560 svcul
= svcul
>> 31 & 1 ? svcul
- ((uint64_t)1 << 32) : svcul
;
562 if (svr
== (VT_LOCAL
| VT_LVAL
)) {
564 arm64_strv(arm64_type_size(svtt
), fltr(r
), 29, svcul
);
566 arm64_strx(arm64_type_size(svtt
), intr(r
), 29, svcul
);
570 if ((svr
& ~VT_VALMASK
) == VT_LVAL
&& svrv
< VT_CONST
) {
572 arm64_strv(arm64_type_size(svtt
), fltr(r
), intr(svrv
), 0);
574 arm64_strx(arm64_type_size(svtt
), intr(r
), intr(svrv
), 0);
578 if (svr
== (VT_CONST
| VT_LVAL
| VT_SYM
)) {
579 arm64_sym(30, sv
->sym
, svcul
); // use x30 for address
581 arm64_strv(arm64_type_size(svtt
), fltr(r
), 30, 0);
583 arm64_strx(arm64_type_size(svtt
), intr(r
), 30, 0);
587 printf("store(%x, (%x, %x, %llx))\n", r
, svtt
, sv
->r
, (long long)svcul
);
591 static void arm64_gen_bl_or_b(int b
)
593 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&& (vtop
->r
& VT_SYM
)) {
595 greloca(cur_text_section
, vtop
->sym
, ind
, R_AARCH64_CALL26
, 0);
596 o(0x94000000); // bl .
599 o(0xd61f0000 | (uint32_t)!b
<< 21 | intr(gv(RC_R30
)) << 5); // br/blr
602 static int arm64_hfa_aux(CType
*type
, int *fsize
, int num
)
604 if (is_float(type
->t
)) {
605 int a
, n
= type_size(type
, &a
);
606 if (num
>= 4 || (*fsize
&& *fsize
!= n
))
611 else if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
612 int is_struct
= 0; // rather than union
614 for (field
= type
->ref
->next
; field
; field
= field
->next
)
621 for (field
= type
->ref
->next
; field
; field
= field
->next
) {
622 if (field
->c
!= (num
- num0
) * *fsize
)
624 num
= arm64_hfa_aux(&field
->type
, fsize
, num
);
628 if (type
->ref
->c
!= (num
- num0
) * *fsize
)
634 for (field
= type
->ref
->next
; field
; field
= field
->next
) {
635 int num1
= arm64_hfa_aux(&field
->type
, fsize
, num0
);
638 num
= num1
< num
? num
: num1
;
640 if (type
->ref
->c
!= (num
- num0
) * *fsize
)
645 else if (type
->t
& VT_ARRAY
) {
649 num1
= arm64_hfa_aux(&type
->ref
->type
, fsize
, num
);
650 if (num1
== -1 || (num1
!= num
&& type
->ref
->c
> 4))
652 num1
= num
+ type
->ref
->c
* (num1
- num
);
660 static int arm64_hfa(CType
*type
, int *fsize
)
662 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
|| (type
->t
& VT_ARRAY
)) {
664 int n
= arm64_hfa_aux(type
, &sz
, 0);
665 if (0 < n
&& n
<= 4) {
674 static unsigned long arm64_pcs_aux(int n
, CType
**type
, unsigned long *a
)
676 int nx
= 0; // next integer register
677 int nv
= 0; // next vector register
678 unsigned long ns
= 32; // next stack offset
681 for (i
= 0; i
< n
; i
++) {
682 int hfa
= arm64_hfa(type
[i
], 0);
685 if ((type
[i
]->t
& VT_ARRAY
) ||
686 (type
[i
]->t
& VT_BTYPE
) == VT_FUNC
)
689 size
= type_size(type
[i
], &align
);
694 else if (size
> 16) {
695 // B.3: replace with pointer
697 a
[i
] = nx
++ << 1 | 1;
705 else if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
)
707 size
= (size
+ 7) & ~7;
710 if (is_float(type
[i
]->t
) && nv
< 8) {
711 a
[i
] = 16 + (nv
++ << 1);
716 if (hfa
&& nv
+ hfa
<= 8) {
717 a
[i
] = 16 + (nv
<< 1);
725 size
= (size
+ 7) & ~7;
729 if (hfa
|| (type
[i
]->t
& VT_BTYPE
) == VT_LDOUBLE
) {
731 ns
= (ns
+ align
- 1) & -align
;
735 if ((type
[i
]->t
& VT_BTYPE
) == VT_FLOAT
)
739 if (hfa
|| is_float(type
[i
]->t
)) {
746 if ((type
[i
]->t
& VT_BTYPE
) != VT_STRUCT
&& size
<= 8 && nx
< 8) {
756 if ((type
[i
]->t
& VT_BTYPE
) != VT_STRUCT
&& size
== 16 && nx
< 7) {
763 if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
&& size
<= (8 - nx
) * 8) {
765 nx
+= (size
+ 7) >> 3;
774 ns
= (ns
+ align
- 1) & -align
;
777 if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
) {
795 static unsigned long arm64_pcs(int n
, CType
**type
, unsigned long *a
)
800 if ((type
[0]->t
& VT_BTYPE
) == VT_VOID
)
803 arm64_pcs_aux(1, type
, a
);
804 assert(a
[0] == 0 || a
[0] == 1 || a
[0] == 16);
808 stack
= arm64_pcs_aux(n
, type
+ 1, a
+ 1);
812 for (i
= 0; i
<= n
; i
++) {
814 printf("arm64_pcs return: ");
816 printf("arm64_pcs arg %d: ", i
);
817 if (a
[i
] == (unsigned long)-1)
819 else if (a
[i
] == 1 && !i
)
820 printf("X8 pointer\n");
822 printf("X%lu%s\n", a
[i
] / 2, a
[i
] & 1 ? " pointer" : "");
824 printf("V%lu\n", a
[i
] / 2 - 8);
826 printf("stack %lu%s\n",
827 (a
[i
] - 32) & ~1, a
[i
] & 1 ? " pointer" : "");
834 ST_FUNC
void gfunc_call(int nb_args
)
838 unsigned long *a
, *a1
;
842 return_type
= &vtop
[-nb_args
].type
.ref
->type
;
843 if ((return_type
->t
& VT_BTYPE
) == VT_STRUCT
)
846 t
= tcc_malloc((nb_args
+ 1) * sizeof(*t
));
847 a
= tcc_malloc((nb_args
+ 1) * sizeof(*a
));
848 a1
= tcc_malloc((nb_args
+ 1) * sizeof(*a1
));
851 for (i
= 0; i
< nb_args
; i
++)
852 t
[nb_args
- i
] = &vtop
[-i
].type
;
854 stack
= arm64_pcs(nb_args
, t
, a
);
856 // Allocate space for structs replaced by pointer:
857 for (i
= nb_args
; i
; i
--)
859 SValue
*arg
= &vtop
[i
- nb_args
];
860 int align
, size
= type_size(&arg
->type
, &align
);
861 assert((arg
->type
.t
& VT_BTYPE
) == VT_STRUCT
);
862 stack
= (stack
+ align
- 1) & -align
;
867 stack
= (stack
+ 15) >> 4 << 4;
869 assert(stack
< 0x1000);
871 o(0xd10003ff | stack
<< 10); // sub sp,sp,#(n)
873 // First pass: set all values on stack
874 for (i
= nb_args
; i
; i
--) {
875 vpushv(vtop
- nb_args
+ i
);
878 // struct replaced by pointer
879 int r
= get_reg(RC_INT
);
880 arm64_spoff(intr(r
), a1
[i
]);
881 vset(&vtop
->type
, r
| VT_LVAL
, 0);
887 arm64_spoff(intr(r
), a1
[i
]);
888 arm64_strx(3, intr(r
), 31, (a
[i
] - 32) >> 1 << 1);
891 else if (a
[i
] >= 32) {
893 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
894 int r
= get_reg(RC_INT
);
895 arm64_spoff(intr(r
), a
[i
] - 32);
896 vset(&vtop
->type
, r
| VT_LVAL
, 0);
900 else if (is_float(vtop
->type
.t
)) {
902 arm64_strv(arm64_type_size(vtop
[0].type
.t
),
903 fltr(vtop
[0].r
), 31, a
[i
] - 32);
907 arm64_strx(arm64_type_size(vtop
[0].type
.t
),
908 intr(vtop
[0].r
), 31, a
[i
] - 32);
915 // Second pass: assign values to registers
916 for (i
= nb_args
; i
; i
--, vtop
--) {
917 if (a
[i
] < 16 && !(a
[i
] & 1)) {
918 // value in general-purpose registers
919 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
920 int align
, size
= type_size(&vtop
->type
, &align
);
921 vtop
->type
.t
= VT_PTR
;
924 arm64_ldrs(a
[i
] / 2, size
);
930 // struct replaced by pointer in register
931 arm64_spoff(a
[i
] / 2, a1
[i
]);
932 else if (a
[i
] < 32) {
933 // value in floating-point registers
934 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
935 uint32_t j
, sz
, n
= arm64_hfa(&vtop
->type
, &sz
);
936 vtop
->type
.t
= VT_PTR
;
939 for (j
= 0; j
< n
; j
++)
941 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
943 j
<< 10); // ldr ([sdq])(*),[x30,#(j * sz)]
946 gv(RC_F(a
[i
] / 2 - 8));
950 if ((return_type
->t
& VT_BTYPE
) == VT_STRUCT
) {
952 // indirect return: set x8 and discard the stack value
957 // return in registers: keep the address for after the call
962 arm64_gen_bl_or_b(0);
965 o(0x910003ff | stack
<< 10); // add sp,sp,#(n)
968 int rt
= return_type
->t
;
969 int bt
= rt
& VT_BTYPE
;
970 if (bt
== VT_STRUCT
&& !(a
[0] & 1)) {
971 // A struct was returned in registers, so write it out:
975 int align
, size
= type_size(return_type
, &align
);
978 o(0xa9000500); // stp x0,x1,[x8]
980 arm64_strx(size
> 4 ? 3 : size
> 2 ? 2 : size
> 1, 0, 8, 0);
983 else if (a
[0] == 16) {
984 uint32_t j
, sz
, n
= arm64_hfa(return_type
, &sz
);
985 for (j
= 0; j
< n
; j
++)
987 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
989 j
<< 10); // str ([sdq])(*),[x8,#(j * sz)]
999 static unsigned long arm64_func_va_list_stack
;
1000 static int arm64_func_va_list_gr_offs
;
1001 static int arm64_func_va_list_vr_offs
;
1002 static int arm64_func_sub_sp_offset
;
1004 ST_FUNC
void gfunc_prolog(Sym
*func_sym
)
1006 CType
*func_type
= &func_sym
->type
;
1013 func_vc
= 144; // offset of where x8 is stored
1015 for (sym
= func_type
->ref
; sym
; sym
= sym
->next
)
1017 t
= tcc_malloc(n
* sizeof(*t
));
1018 a
= tcc_malloc(n
* sizeof(*a
));
1020 for (sym
= func_type
->ref
; sym
; sym
= sym
->next
)
1021 t
[i
++] = &sym
->type
;
1023 arm64_func_va_list_stack
= arm64_pcs(n
- 1, t
, a
);
1025 o(0xa9b27bfd); // stp x29,x30,[sp,#-224]!
1026 o(0xad0087e0); // stp q0,q1,[sp,#16]
1027 o(0xad018fe2); // stp q2,q3,[sp,#48]
1028 o(0xad0297e4); // stp q4,q5,[sp,#80]
1029 o(0xad039fe6); // stp q6,q7,[sp,#112]
1030 o(0xa90923e8); // stp x8,x8,[sp,#144]
1031 o(0xa90a07e0); // stp x0,x1,[sp,#160]
1032 o(0xa90b0fe2); // stp x2,x3,[sp,#176]
1033 o(0xa90c17e4); // stp x4,x5,[sp,#192]
1034 o(0xa90d1fe6); // stp x6,x7,[sp,#208]
1036 arm64_func_va_list_gr_offs
= -64;
1037 arm64_func_va_list_vr_offs
= -128;
1039 for (i
= 1, sym
= func_type
->ref
->next
; sym
; i
++, sym
= sym
->next
) {
1040 int off
= (a
[i
] < 16 ? 160 + a
[i
] / 2 * 8 :
1041 a
[i
] < 32 ? 16 + (a
[i
] - 16) / 2 * 16 :
1042 224 + ((a
[i
] - 32) >> 1 << 1));
1043 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
1044 (a
[i
] & 1 ? VT_LLOCAL
: VT_LOCAL
) | VT_LVAL
,
1048 int align
, size
= type_size(&sym
->type
, &align
);
1049 arm64_func_va_list_gr_offs
= (a
[i
] / 2 - 7 +
1050 (!(a
[i
] & 1) && size
> 8)) * 8;
1052 else if (a
[i
] < 32) {
1053 uint32_t hfa
= arm64_hfa(&sym
->type
, 0);
1054 arm64_func_va_list_vr_offs
= (a
[i
] / 2 - 16 +
1055 (hfa
? hfa
: 1)) * 16;
1058 // HFAs of float and double need to be written differently:
1059 if (16 <= a
[i
] && a
[i
] < 32 && (sym
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
1060 uint32_t j
, sz
, k
= arm64_hfa(&sym
->type
, &sz
);
1062 for (j
= 0; j
< k
; j
++) {
1063 o(0x3d0003e0 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
1064 ((a
[i
] - 16) / 2 + j
) | (off
/ sz
+ j
) << 10);
1065 // str ([sdq])(*),[sp,#(j * sz)]
1073 o(0x910003fd); // mov x29,sp
1074 arm64_func_sub_sp_offset
= ind
;
1075 // In gfunc_epilog these will be replaced with code to decrement SP:
1076 o(0xd503201f); // nop
1077 o(0xd503201f); // nop
1081 ST_FUNC
void gen_va_start(void)
1084 --vtop
; // we don't need the "arg"
1086 r
= intr(gv(RC_INT
));
1088 if (arm64_func_va_list_stack
) {
1089 //xx could use add (immediate) here
1090 arm64_movimm(30, arm64_func_va_list_stack
+ 224);
1091 o(0x8b1e03be); // add x30,x29,x30
1094 o(0x910383be); // add x30,x29,#224
1095 o(0xf900001e | r
<< 5); // str x30,[x(r)]
1097 if (arm64_func_va_list_gr_offs
) {
1098 if (arm64_func_va_list_stack
)
1099 o(0x910383be); // add x30,x29,#224
1100 o(0xf900041e | r
<< 5); // str x30,[x(r),#8]
1103 if (arm64_func_va_list_vr_offs
) {
1104 o(0x910243be); // add x30,x29,#144
1105 o(0xf900081e | r
<< 5); // str x30,[x(r),#16]
1108 arm64_movimm(30, arm64_func_va_list_gr_offs
);
1109 o(0xb900181e | r
<< 5); // str w30,[x(r),#24]
1111 arm64_movimm(30, arm64_func_va_list_vr_offs
);
1112 o(0xb9001c1e | r
<< 5); // str w30,[x(r),#28]
1117 ST_FUNC
void gen_va_arg(CType
*t
)
1119 int align
, size
= type_size(t
, &align
);
1120 int fsize
, hfa
= arm64_hfa(t
, &fsize
);
1123 if (is_float(t
->t
)) {
1129 r0
= intr(gv(RC_INT
));
1130 r1
= get_reg(RC_INT
);
1131 vtop
[0].r
= r1
| VT_LVAL
;
1135 uint32_t n
= size
> 16 ? 8 : (size
+ 7) & -8;
1136 o(0xb940181e | r0
<< 5); // ldr w30,[x(r0),#24] // __gr_offs
1138 assert(0); // this path untested but needed for __uint128_t
1139 o(0x11003fde); // add w30,w30,#15
1140 o(0x121c6fde); // and w30,w30,#-16
1142 o(0x310003c0 | r1
| n
<< 10); // adds w(r1),w30,#(n)
1143 o(0x540000ad); // b.le .+20
1144 o(0xf9400000 | r1
| r0
<< 5); // ldr x(r1),[x(r0)] // __stack
1145 o(0x9100001e | r1
<< 5 | n
<< 10); // add x30,x(r1),#(n)
1146 o(0xf900001e | r0
<< 5); // str x30,[x(r0)] // __stack
1147 o(0x14000004); // b .+16
1148 o(0xb9001800 | r1
| r0
<< 5); // str w(r1),[x(r0),#24] // __gr_offs
1149 o(0xf9400400 | r1
| r0
<< 5); // ldr x(r1),[x(r0),#8] // __gr_top
1150 o(0x8b3ec000 | r1
| r1
<< 5); // add x(r1),x(r1),w30,sxtw
1152 o(0xf9400000 | r1
| r1
<< 5); // ldr x(r1),[x(r1)]
1155 uint32_t rsz
= hfa
<< 4;
1156 uint32_t ssz
= (size
+ 7) & -(uint32_t)8;
1158 o(0xb9401c1e | r0
<< 5); // ldr w30,[x(r0),#28] // __vr_offs
1159 o(0x310003c0 | r1
| rsz
<< 10); // adds w(r1),w30,#(rsz)
1160 b1
= ind
; o(0x5400000d); // b.le lab1
1161 o(0xf9400000 | r1
| r0
<< 5); // ldr x(r1),[x(r0)] // __stack
1163 o(0x91003c00 | r1
| r1
<< 5); // add x(r1),x(r1),#15
1164 o(0x927cec00 | r1
| r1
<< 5); // and x(r1),x(r1),#-16
1166 o(0x9100001e | r1
<< 5 | ssz
<< 10); // add x30,x(r1),#(ssz)
1167 o(0xf900001e | r0
<< 5); // str x30,[x(r0)] // __stack
1168 b2
= ind
; o(0x14000000); // b lab2
1170 write32le(cur_text_section
->data
+ b1
, 0x5400000d | (ind
- b1
) << 3);
1171 o(0xb9001c00 | r1
| r0
<< 5); // str w(r1),[x(r0),#28] // __vr_offs
1172 o(0xf9400800 | r1
| r0
<< 5); // ldr x(r1),[x(r0),#16] // __vr_top
1173 if (hfa
== 1 || fsize
== 16)
1174 o(0x8b3ec000 | r1
| r1
<< 5); // add x(r1),x(r1),w30,sxtw
1176 // We need to change the layout of this HFA.
1177 // Get some space on the stack using global variable "loc":
1178 loc
= (loc
- size
) & -(uint32_t)align
;
1179 o(0x8b3ec000 | 30 | r1
<< 5); // add x30,x(r1),w30,sxtw
1180 arm64_movimm(r1
, loc
);
1181 o(0x8b0003a0 | r1
| r1
<< 16); // add x(r1),x29,x(r1)
1182 o(0x4c402bdc | (uint32_t)fsize
<< 7 |
1183 (uint32_t)(hfa
== 2) << 15 |
1184 (uint32_t)(hfa
== 3) << 14); // ld1 {v28.(4s|2d),...},[x30]
1185 o(0x0d00801c | r1
<< 5 | (fsize
== 8) << 10 |
1186 (uint32_t)(hfa
!= 2) << 13 |
1187 (uint32_t)(hfa
!= 3) << 21); // st(hfa) {v28.(s|d),...}[0],[x(r1)]
1190 write32le(cur_text_section
->data
+ b2
, 0x14000000 | (ind
- b2
) >> 2);
1194 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
1195 int *align
, int *regsize
)
1200 ST_FUNC
void gfunc_return(CType
*func_type
)
1202 CType
*t
= func_type
;
1205 arm64_pcs(0, &t
, &a
);
1210 if ((func_type
->t
& VT_BTYPE
) == VT_STRUCT
) {
1211 int align
, size
= type_size(func_type
, &align
);
1214 arm64_ldrs(0, size
);
1220 CType type
= *func_type
;
1222 vset(&type
, VT_LOCAL
| VT_LVAL
, func_vc
);
1229 if ((func_type
->t
& VT_BTYPE
) == VT_STRUCT
) {
1230 uint32_t j
, sz
, n
= arm64_hfa(&vtop
->type
, &sz
);
1233 for (j
= 0; j
< n
; j
++)
1235 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
1236 j
| j
<< 10); // ldr ([sdq])(*),[x0,#(j * sz)]
1247 ST_FUNC
void gfunc_epilog(void)
1250 // Insert instructions to subtract size of stack frame from SP.
1251 unsigned char *ptr
= cur_text_section
->data
+ arm64_func_sub_sp_offset
;
1252 uint64_t diff
= (-loc
+ 15) & ~15;
1253 if (!(diff
>> 24)) {
1254 if (diff
& 0xfff) // sub sp,sp,#(diff & 0xfff)
1255 write32le(ptr
, 0xd10003ff | (diff
& 0xfff) << 10);
1256 if (diff
>> 12) // sub sp,sp,#(diff >> 12),lsl #12
1257 write32le(ptr
+ 4, 0xd14003ff | (diff
>> 12) << 10);
1260 // In this case we may subtract more than necessary,
1261 // but always less than 17/16 of what we were aiming for.
1264 while (diff
>> 20) {
1265 diff
= (diff
+ 0xffff) >> 16;
1268 while (diff
>> 16) {
1269 diff
= (diff
+ 1) >> 1;
1272 write32le(ptr
, 0xd2800010 | diff
<< 5 | i
<< 21);
1273 // mov x16,#(diff),lsl #(16 * i)
1274 write32le(ptr
+ 4, 0xcb3063ff | j
<< 10);
1275 // sub sp,sp,x16,lsl #(j)
1278 o(0x910003bf); // mov sp,x29
1279 o(0xa8ce7bfd); // ldp x29,x30,[sp],#224
1281 o(0xd65f03c0); // ret
1284 ST_FUNC
void gen_fill_nops(int bytes
)
1287 tcc_error("alignment of code section not multiple of 4");
1289 o(0xd503201f); // nop
1294 // Generate forward branch to label:
1295 ST_FUNC
int gjmp(int t
)
1304 // Generate branch to known address:
1305 ST_FUNC
void gjmp_addr(int a
)
1307 assert(a
- ind
+ 0x8000000 < 0x10000000);
1308 o(0x14000000 | ((a
- ind
) >> 2 & 0x3ffffff));
1311 ST_FUNC
int gjmp_append(int n
, int t
)
1314 /* insert vtop->c jump list in t */
1316 uint32_t n1
= n
, n2
;
1317 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
1325 void arm64_vset_VT_CMP(int op
)
1327 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
1328 vtop
->cmp_r
= vtop
->r
;
1333 static void arm64_gen_opil(int op
, uint32_t l
);
1335 static void arm64_load_cmp(int r
, SValue
*sv
)
1340 arm64_gen_opil('^', 0);
1348 ST_FUNC
int gjmp_cond(int op
, int t
)
1350 int bt
= vtop
->type
.t
& VT_BTYPE
;
1353 vtop
->r
= vtop
->cmp_r
;
1355 if (bt
== VT_LDOUBLE
) {
1356 uint32_t a
, b
, f
= fltr(gv(RC_FLOAT
));
1357 a
= get_reg(RC_INT
);
1360 b
= get_reg(RC_INT
);
1363 o(0x4e083c00 | a
| f
<< 5); // mov x(a),v(f).d[0]
1364 o(0x4e183c00 | b
| f
<< 5); // mov x(b),v(f).d[1]
1365 o(0xaa000400 | a
| a
<< 5 | b
<< 16); // orr x(a),x(a),x(b),lsl #1
1366 o(0xb4000040 | a
| !!inv
<< 24); // cbz/cbnz x(a),.+8
1369 else if (bt
== VT_FLOAT
|| bt
== VT_DOUBLE
) {
1370 uint32_t a
= fltr(gv(RC_FLOAT
));
1371 o(0x1e202008 | a
<< 5 | (bt
!= VT_FLOAT
) << 22); // fcmp
1372 o(0x54000040 | !!inv
); // b.eq/b.ne .+8
1375 uint32_t ll
= (bt
== VT_PTR
|| bt
== VT_LLONG
);
1376 uint32_t a
= intr(gv(RC_INT
));
1377 o(0x34000040 | a
| !!inv
<< 24 | ll
<< 31); // cbz/cbnz wA,.+8
1382 static int arm64_iconst(uint64_t *val
, SValue
*sv
)
1384 if ((sv
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) != VT_CONST
)
1388 int bt
= t
& VT_BTYPE
;
1389 *val
= ((bt
== VT_LLONG
|| bt
== VT_PTR
) ? sv
->c
.i
:
1391 (t
& VT_UNSIGNED
? 0 : -(sv
->c
.i
& 0x80000000)));
1396 static int arm64_gen_opic(int op
, uint32_t l
, int rev
, uint64_t val
,
1397 uint32_t x
, uint32_t a
)
1399 if (op
== '-' && !rev
) {
1403 val
= l
? val
: (uint32_t)val
;
1408 uint32_t s
= l
? val
>> 63 : val
>> 31;
1409 val
= s
? -val
: val
;
1410 val
= l
? val
: (uint32_t)val
;
1411 if (!(val
& ~(uint64_t)0xfff))
1412 o(0x11000000 | l
<< 31 | s
<< 30 | x
| a
<< 5 | val
<< 10);
1413 else if (!(val
& ~(uint64_t)0xfff000))
1414 o(0x11400000 | l
<< 31 | s
<< 30 | x
| a
<< 5 | val
>> 12 << 10);
1416 arm64_movimm(30, val
); // use x30
1417 o(0x0b1e0000 | l
<< 31 | s
<< 30 | x
| a
<< 5);
1424 o(0x4b0003e0 | l
<< 31 | x
| a
<< 16); // neg
1425 else if (val
== (l
? (uint64_t)-1 : (uint32_t)-1))
1426 o(0x2a2003e0 | l
<< 31 | x
| a
<< 16); // mvn
1428 arm64_movimm(30, val
); // use x30
1429 o(0x4b0003c0 | l
<< 31 | x
| a
<< 16); // sub
1434 if (val
== -1 || (val
== 0xffffffff && !l
)) {
1435 o(0x2a2003e0 | l
<< 31 | x
| a
<< 16); // mvn
1441 int e
= arm64_encode_bimm64(l
? val
: val
| val
<< 32);
1444 o((op
== '&' ? 0x12000000 :
1445 op
== '|' ? 0x32000000 : 0x52000000) |
1446 l
<< 31 | x
| a
<< 5 | (uint32_t)e
<< 10);
1453 uint32_t n
= 32 << l
;
1454 val
= val
& (n
- 1);
1459 else if (op
== TOK_SHL
)
1460 o(0x53000000 | l
<< 31 | l
<< 22 | x
| a
<< 5 |
1461 (n
- val
) << 16 | (n
- 1 - val
) << 10); // lsl
1463 o(0x13000000 | (op
== TOK_SHR
) << 30 | l
<< 31 | l
<< 22 |
1464 x
| a
<< 5 | val
<< 16 | (n
- 1) << 10); // lsr/asr
1472 static void arm64_gen_opil(int op
, uint32_t l
)
1476 // Special treatment for operations with a constant operand:
1481 if (arm64_iconst(0, &vtop
[0])) {
1485 if (arm64_iconst(&val
, &vtop
[-1])) {
1487 a
= intr(vtop
[0].r
);
1489 x
= get_reg(RC_INT
);
1491 if (arm64_gen_opic(op
, l
, rev
, val
, intr(x
), a
)) {
1502 gv2(RC_INT
, RC_INT
);
1503 assert(vtop
[-1].r
< VT_CONST
&& vtop
[0].r
< VT_CONST
);
1504 a
= intr(vtop
[-1].r
);
1505 b
= intr(vtop
[0].r
);
1507 x
= get_reg(RC_INT
);
1514 // Use x30 for quotient:
1515 o(0x1ac00c00 | l
<< 31 | 30 | a
<< 5 | b
<< 16); // sdiv
1516 o(0x1b008000 | l
<< 31 | x
| (uint32_t)30 << 5 |
1517 b
<< 16 | a
<< 10); // msub
1520 o(0x0a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // and
1523 o(0x1b007c00 | l
<< 31 | x
| a
<< 5 | b
<< 16); // mul
1526 o(0x0b000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // add
1529 o(0x4b000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // sub
1532 o(0x1ac00c00 | l
<< 31 | x
| a
<< 5 | b
<< 16); // sdiv
1535 o(0x4a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // eor
1538 o(0x2a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // orr
1541 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1542 o(0x1a9f17e0 | x
); // cset wA,eq
1545 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1546 o(0x1a9fb7e0 | x
); // cset wA,ge
1549 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1550 o(0x1a9fd7e0 | x
); // cset wA,gt
1553 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1554 o(0x1a9fc7e0 | x
); // cset wA,le
1557 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1558 o(0x1a9fa7e0 | x
); // cset wA,lt
1561 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1562 o(0x1a9f07e0 | x
); // cset wA,ne
1565 o(0x1ac02800 | l
<< 31 | x
| a
<< 5 | b
<< 16); // asr
1568 o(0x1ac02000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // lsl
1571 o(0x1ac02400 | l
<< 31 | x
| a
<< 5 | b
<< 16); // lsr
1575 o(0x1ac00800 | l
<< 31 | x
| a
<< 5 | b
<< 16); // udiv
1578 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1579 o(0x1a9f37e0 | x
); // cset wA,cs
1582 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1583 o(0x1a9f97e0 | x
); // cset wA,hi
1586 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1587 o(0x1a9f27e0 | x
); // cset wA,cc
1590 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1591 o(0x1a9f87e0 | x
); // cset wA,ls
1594 // Use x30 for quotient:
1595 o(0x1ac00800 | l
<< 31 | 30 | a
<< 5 | b
<< 16); // udiv
1596 o(0x1b008000 | l
<< 31 | x
| (uint32_t)30 << 5 |
1597 b
<< 16 | a
<< 10); // msub
1604 ST_FUNC
void gen_opi(int op
)
1606 arm64_gen_opil(op
, 0);
1607 arm64_vset_VT_CMP(op
);
1610 ST_FUNC
void gen_opl(int op
)
1612 arm64_gen_opil(op
, 1);
1613 arm64_vset_VT_CMP(op
);
1616 ST_FUNC
void gen_opf(int op
)
1618 uint32_t x
, a
, b
, dbl
;
1620 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
1621 CType type
= vtop
[0].type
;
1625 case '*': func
= TOK___multf3
; break;
1626 case '+': func
= TOK___addtf3
; break;
1627 case '-': func
= TOK___subtf3
; break;
1628 case '/': func
= TOK___divtf3
; break;
1629 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
1630 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
1631 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
1632 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
1633 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
1634 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
1635 default: assert(0); break;
1637 vpush_global_sym(&func_old_type
, func
);
1641 vtop
->r
= cond
< 0 ? REG_FRET
: REG_IRET
;
1645 o(0x7100001f); // cmp w0,#0
1646 o(0x1a9f07e0 | (uint32_t)cond
<< 12); // cset w0,(cond)
1651 dbl
= vtop
[0].type
.t
!= VT_FLOAT
;
1652 gv2(RC_FLOAT
, RC_FLOAT
);
1653 assert(vtop
[-1].r
< VT_CONST
&& vtop
[0].r
< VT_CONST
);
1654 a
= fltr(vtop
[-1].r
);
1655 b
= fltr(vtop
[0].r
);
1658 case TOK_EQ
: case TOK_NE
:
1659 case TOK_LT
: case TOK_GE
: case TOK_LE
: case TOK_GT
:
1660 x
= get_reg(RC_INT
);
1666 x
= get_reg(RC_FLOAT
);
1675 o(0x1e200800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fmul
1678 o(0x1e202800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fadd
1681 o(0x1e203800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fsub
1684 o(0x1e201800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fdiv
1687 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1688 o(0x1a9f17e0 | x
); // cset w(x),eq
1691 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1692 o(0x1a9fb7e0 | x
); // cset w(x),ge
1695 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1696 o(0x1a9fd7e0 | x
); // cset w(x),gt
1699 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1700 o(0x1a9f87e0 | x
); // cset w(x),ls
1703 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1704 o(0x1a9f57e0 | x
); // cset w(x),mi
1707 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1708 o(0x1a9f07e0 | x
); // cset w(x),ne
1713 arm64_vset_VT_CMP(op
);
1716 // Generate sign extension from 32 to 64 bits:
1717 ST_FUNC
void gen_cvt_sxtw(void)
1719 uint32_t r
= intr(gv(RC_INT
));
1720 o(0x93407c00 | r
| r
<< 5); // sxtw x(r),w(r)
1723 /* char/short to int conversion */
1724 ST_FUNC
void gen_cvt_csti(int t
)
1726 int r
= intr(gv(RC_INT
));
1728 | ((t
& VT_BTYPE
) == VT_SHORT
) << 13
1729 | (uint32_t)!!(t
& VT_UNSIGNED
) << 30
1730 | r
| r
<< 5); // [su]xt[bh] w(r),w(r)
1733 ST_FUNC
void gen_cvt_itof(int t
)
1735 if (t
== VT_LDOUBLE
) {
1736 int f
= vtop
->type
.t
;
1737 int func
= (f
& VT_BTYPE
) == VT_LLONG
?
1738 (f
& VT_UNSIGNED
? TOK___floatunditf
: TOK___floatditf
) :
1739 (f
& VT_UNSIGNED
? TOK___floatunsitf
: TOK___floatsitf
);
1740 vpush_global_sym(&func_old_type
, func
);
1749 int d
, n
= intr(gv(RC_INT
));
1750 int s
= !(vtop
->type
.t
& VT_UNSIGNED
);
1751 uint32_t l
= ((vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
);
1753 d
= get_reg(RC_FLOAT
);
1756 o(0x1e220000 | (uint32_t)!s
<< 16 |
1757 (uint32_t)(t
!= VT_FLOAT
) << 22 | fltr(d
) |
1758 l
<< 31 | n
<< 5); // [us]cvtf [sd](d),[wx](n)
1762 ST_FUNC
void gen_cvt_ftoi(int t
)
1764 if ((vtop
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
) {
1765 int func
= (t
& VT_BTYPE
) == VT_LLONG
?
1766 (t
& VT_UNSIGNED
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1767 (t
& VT_UNSIGNED
? TOK___fixunstfsi
: TOK___fixtfsi
);
1768 vpush_global_sym(&func_old_type
, func
);
1777 int d
, n
= fltr(gv(RC_FLOAT
));
1778 uint32_t l
= ((vtop
->type
.t
& VT_BTYPE
) != VT_FLOAT
);
1780 d
= get_reg(RC_INT
);
1784 (uint32_t)!!(t
& VT_UNSIGNED
) << 16 |
1785 (uint32_t)((t
& VT_BTYPE
) == VT_LLONG
) << 31 | intr(d
) |
1786 l
<< 22 | n
<< 5); // fcvtz[su] [wx](d),[sd](n)
1790 ST_FUNC
void gen_cvt_ftof(int t
)
1792 int f
= vtop
[0].type
.t
& VT_BTYPE
;
1793 assert(t
== VT_FLOAT
|| t
== VT_DOUBLE
|| t
== VT_LDOUBLE
);
1794 assert(f
== VT_FLOAT
|| f
== VT_DOUBLE
|| f
== VT_LDOUBLE
);
1798 if (t
== VT_LDOUBLE
|| f
== VT_LDOUBLE
) {
1799 int func
= (t
== VT_LDOUBLE
) ?
1800 (f
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1801 (t
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1802 vpush_global_sym(&func_old_type
, func
);
1812 assert(vtop
[0].r
< VT_CONST
);
1813 a
= fltr(vtop
[0].r
);
1815 x
= get_reg(RC_FLOAT
);
1821 o(0x1e22c000 | x
| a
<< 5); // fcvt d(x),s(a)
1823 o(0x1e624000 | x
| a
<< 5); // fcvt s(x),d(a)
1827 ST_FUNC
void ggoto(void)
1829 arm64_gen_bl_or_b(1);
1833 ST_FUNC
void gen_clear_cache(void)
1835 uint32_t beg
, end
, dsz
, isz
, p
, lab1
, b1
;
1836 gv2(RC_INT
, RC_INT
);
1838 vtop
->r
= get_reg(RC_INT
);
1840 vtop
->r
= get_reg(RC_INT
);
1842 vtop
->r
= get_reg(RC_INT
);
1843 beg
= intr(vtop
[-4].r
); // x0
1844 end
= intr(vtop
[-3].r
); // x1
1845 dsz
= intr(vtop
[-2].r
); // x2
1846 isz
= intr(vtop
[-1].r
); // x3
1847 p
= intr(vtop
[0].r
); // x4
1850 o(0xd53b0020 | isz
); // mrs x(isz),ctr_el0
1851 o(0x52800080 | p
); // mov w(p),#4
1852 o(0x53104c00 | dsz
| isz
<< 5); // ubfx w(dsz),w(isz),#16,#4
1853 o(0x1ac02000 | dsz
| p
<< 5 | dsz
<< 16); // lsl w(dsz),w(p),w(dsz)
1854 o(0x12000c00 | isz
| isz
<< 5); // and w(isz),w(isz),#15
1855 o(0x1ac02000 | isz
| p
<< 5 | isz
<< 16); // lsl w(isz),w(p),w(isz)
1856 o(0x51000400 | p
| dsz
<< 5); // sub w(p),w(dsz),#1
1857 o(0x8a240004 | p
| beg
<< 5 | p
<< 16); // bic x(p),x(beg),x(p)
1858 b1
= ind
; o(0x14000000); // b
1860 o(0xd50b7b20 | p
); // dc cvau,x(p)
1861 o(0x8b000000 | p
| p
<< 5 | dsz
<< 16); // add x(p),x(p),x(dsz)
1862 write32le(cur_text_section
->data
+ b1
, 0x14000000 | (ind
- b1
) >> 2);
1863 o(0xeb00001f | p
<< 5 | end
<< 16); // cmp x(p),x(end)
1864 o(0x54ffffa3 | ((lab1
- ind
) << 3 & 0xffffe0)); // b.cc lab1
1865 o(0xd5033b9f); // dsb ish
1866 o(0x51000400 | p
| isz
<< 5); // sub w(p),w(isz),#1
1867 o(0x8a240004 | p
| beg
<< 5 | p
<< 16); // bic x(p),x(beg),x(p)
1868 b1
= ind
; o(0x14000000); // b
1870 o(0xd50b7520 | p
); // ic ivau,x(p)
1871 o(0x8b000000 | p
| p
<< 5 | isz
<< 16); // add x(p),x(p),x(isz)
1872 write32le(cur_text_section
->data
+ b1
, 0x14000000 | (ind
- b1
) >> 2);
1873 o(0xeb00001f | p
<< 5 | end
<< 16); // cmp x(p),x(end)
1874 o(0x54ffffa3 | ((lab1
- ind
) << 3 & 0xffffe0)); // b.cc lab1
1875 o(0xd5033b9f); // dsb ish
1876 o(0xd5033fdf); // isb
1879 ST_FUNC
void gen_vla_sp_save(int addr
) {
1880 uint32_t r
= intr(get_reg(RC_INT
));
1881 o(0x910003e0 | r
); // mov x(r),sp
1882 arm64_strx(3, r
, 29, addr
);
1885 ST_FUNC
void gen_vla_sp_restore(int addr
) {
1886 // Use x30 because this function can be called when there
1887 // is a live return value in x0 but there is nothing on
1888 // the value stack to prevent get_reg from returning x0.
1890 arm64_ldrx(0, 3, r
, 29, addr
);
1891 o(0x9100001f | r
<< 5); // mov sp,x(r)
1894 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
) {
1895 uint32_t r
= intr(gv(RC_INT
));
1896 o(0x91003c00 | r
| r
<< 5); // add x(r),x(r),#15
1897 o(0x927cec00 | r
| r
<< 5); // bic x(r),x(r),#15
1898 o(0xcb2063ff | r
<< 16); // sub sp,sp,x(r)
1902 /* end of A64 code generator */
1903 /*************************************************************/
1905 /*************************************************************/