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riscv: implement stdarg functions
[tinycc.git] / riscv64-gen.c
blob3eb77e1a5401e8a7f0f0fa6864eb1bcfa804ef82
1 #ifdef TARGET_DEFS_ONLY
2
3 // Number of registers available to allocator:
4 #define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
5
6 #define TREG_R(x) (x) // x = 0..7
7 #define TREG_F(x) (x + 8) // x = 0..7
8
9 // Register classes sorted from more general to more precise:
10 #define RC_INT (1 << 0)
11 #define RC_FLOAT (1 << 1)
12 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
13 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
14
15 #define RC_IRET (RC_R(0)) // int return register class
16 #define RC_FRET (RC_F(0)) // float return register class
17
18 #define REG_IRET (TREG_R(0)) // int return register number
19 #define REG_FRET (TREG_F(0)) // float return register number
20
21 #define PTR_SIZE 8
22
23 #define LDOUBLE_SIZE 16
24 #define LDOUBLE_ALIGN 16
25
26 #define MAX_ALIGN 16
27
28 #define CHAR_IS_UNSIGNED
29
30 #else
31 #include "tcc.h"
32 #include <assert.h>
33
34 #define XLEN 8
35
36 #define TREG_RA 17
37 #define TREG_SP 18
38
39 ST_DATA const int reg_classes[NB_REGS] = {
40 RC_INT | RC_R(0),
41 RC_INT | RC_R(1),
42 RC_INT | RC_R(2),
43 RC_INT | RC_R(3),
44 RC_INT | RC_R(4),
45 RC_INT | RC_R(5),
46 RC_INT | RC_R(6),
47 RC_INT | RC_R(7),
48 RC_FLOAT | RC_F(0),
49 RC_FLOAT | RC_F(1),
50 RC_FLOAT | RC_F(2),
51 RC_FLOAT | RC_F(3),
52 RC_FLOAT | RC_F(4),
53 RC_FLOAT | RC_F(5),
54 RC_FLOAT | RC_F(6),
55 RC_FLOAT | RC_F(7),
56 0,
57 1 << TREG_RA,
58 1 << TREG_SP
59 };
60
61 static int ireg(int r)
62 {
63 if (r == TREG_RA)
64 return 1; // ra
65 if (r == TREG_SP)
66 return 2; // sp
67 assert(r >= 0 && r < 8);
68 return r + 10; // tccrX --> aX == x(10+X)
69 }
70
71 static int is_ireg(int r)
72 {
73 return r < 8 || r == TREG_RA || r == TREG_SP;
74 }
75
76 static int freg(int r)
77 {
78 assert(r >= 8 && r < 16);
79 return r - 8 + 10; // tccfX --> faX == f(10+X)
80 }
81
82 static int is_freg(int r)
83 {
84 return r >= 8 && r < 16;
85 }
86
87 ST_FUNC void o(unsigned int c)
88 {
89 int ind1 = ind + 4;
90 if (nocode_wanted)
91 return;
92 if (ind1 > cur_text_section->data_allocated)
93 section_realloc(cur_text_section, ind1);
94 write32le(cur_text_section->data + ind, c);
95 ind = ind1;
96 }
97
98 static void EI(uint32_t opcode, uint32_t func3,
99 uint32_t rd, uint32_t rs1, uint32_t imm)
100 {
101 assert(! ((imm + (1 << 11)) >> 12));
102 o(opcode | (func3 << 12) | (rd << 7) | (rs1 << 15) | (imm << 20));
103 }
104
105 static void ES(uint32_t opcode, uint32_t func3,
106 uint32_t rs1, uint32_t rs2, uint32_t imm)
107 {
108 assert(! ((imm + (1 << 11)) >> 12));
109 o(opcode | (func3 << 12) | ((imm & 0x1f) << 7) | (rs1 << 15)
110 | (rs2 << 20) | ((imm >> 5) << 25));
111 }
112
113 // Patch all branches in list pointed to by t to branch to a:
114 ST_FUNC void gsym_addr(int t_, int a_)
115 {
116 uint32_t t = t_;
117 uint32_t a = a_;
118 while (t) {
119 unsigned char *ptr = cur_text_section->data + t;
120 uint32_t next = read32le(ptr);
121 uint32_t r = a - t, imm;
122 if ((r + (1 << 21)) & ~((1U << 22) - 2))
123 tcc_error("out-of-range branch chain");
124 imm = (((r >> 12) & 0xff) << 12)
125 | (((r >> 11) & 1) << 20)
126 | (((r >> 1) & 0x3ff) << 21)
127 | (((r >> 20) & 1) << 31);
128 write32le(ptr, r == 4 ? 0x33 : 0x6f | imm); // nop || j imm
129 t = next;
130 }
131 }
132
133 ST_FUNC void load(int r, SValue *sv)
134 {
135 int fr = sv->r;
136 int v = fr & VT_VALMASK;
137 int rr = is_ireg(r) ? ireg(r) : freg(r);
138 int fc = sv->c.i;
139 int bt = sv->type.t & VT_BTYPE;
140 int align, size = type_size(&sv->type, &align);
141 if (fr & VT_LVAL) {
142 int func3, opcode = 0x03;
143 if (is_freg(r)) {
144 assert(bt == VT_DOUBLE || bt == VT_FLOAT);
145 opcode = 0x07;
146 func3 = bt == VT_DOUBLE ? 3 : 2;
147 } else {
148 assert(is_ireg(r));
149 if (bt == VT_FUNC)
150 size = PTR_SIZE;
151 func3 = size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3;
152 if (size < 8 && !is_float(sv->type.t) && (sv->type.t & VT_UNSIGNED))
153 func3 |= 4;
154 }
155 if (v == VT_LOCAL) {
156 int br = 8; // s0
157 if (fc != sv->c.i)
158 tcc_error("unimp: load1(giant local ofs) (0x%llx)", (long long)sv->c.i);
159 if (((unsigned)fc + (1 << 11)) >> 12) {
160 br = is_ireg(r) ? rr : ireg(get_reg(RC_INT));
161 o(0x37 | (br << 7) | ((0x800 + fc) & 0xfffff000)); //lui BR, upper(fc)
162 o(0x33 | (br << 7) | (br << 15) | (8 << 20)); // add BR, BR, s0
163 fc = fc << 20 >> 20;
164 }
165 EI(opcode, func3, rr, br, fc); // l[bhwd][u]/fl[wd] RR, fc(BR)
166 } else if (v < VT_CONST) {
167 /*if (((unsigned)fc + (1 << 11)) >> 12)
168 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
169 fc = 0; // XXX store ofs in LVAL(reg)
170 EI(opcode, func3, rr, ireg(v), fc); // l[bhwd][u] RR, 0(V)
171 } else if (v == VT_CONST && (fr & VT_SYM)) {
172 static Sym label;
173 int addend = 0, tempr;
174 if (1 || ((unsigned)fc + (1 << 11)) >> 12)
175 addend = fc, fc = 0;
176
177 greloca(cur_text_section, sv->sym, ind,
178 R_RISCV_PCREL_HI20, addend);
179 if (!label.v) {
180 label.v = tok_alloc(".L0 ", 4)->tok;
181 label.type.t = VT_VOID | VT_STATIC;
182 }
183 label.c = 0; /* force new local ELF symbol */
184 put_extern_sym(&label, cur_text_section, ind, 0);
185 tempr = is_ireg(r) ? rr : ireg(get_reg(RC_INT));
186 o(0x17 | (tempr << 7)); // auipc TR, 0 %pcrel_hi(sym)+addend
187 greloca(cur_text_section, &label, ind,
188 R_RISCV_PCREL_LO12_I, 0);
189 EI(opcode, func3, rr, tempr, fc); // l[bhwd][u] RR, fc(TR)
190 } else if (v == VT_LLOCAL) {
191 int br = 8, tempr = is_ireg(r) ? rr : ireg(get_reg(RC_INT));
192 if (fc != sv->c.i)
193 tcc_error("unimp: load2(giant local ofs) (0x%llx)", (long long)sv->c.i);
194 if (((unsigned)fc + (1 << 11)) >> 12) {
195 br = tempr;
196 o(0x37 | (br << 7) | ((0x800 + fc) & 0xfffff000)); //lui BR, upper(fc)
197 o(0x33 | (br << 7) | (br << 15) | (8 << 20)); // add BR, BR, s0
198 fc = fc << 20 >> 20;
199 }
200 EI(0x03, 3, tempr, br, fc); // ld TEMPR, fc(BR)
201 EI(opcode, func3, rr, tempr, 0); // l[bhwd][u] RR, 0(TEMPR)
202 } else {
203 tcc_error("unimp: load(non-local lval)");
204 }
205 } else if (v == VT_CONST) {
206 int rb = 0, do32bit = 8, doload = 0;
207 assert(!is_float(sv->type.t) && is_ireg(r) || bt == VT_LDOUBLE);
208 if (fr & VT_SYM) {
209 static Sym label;
210 if (sv->sym->type.t & VT_STATIC) { // XXX do this per linker relax
211 greloca(cur_text_section, sv->sym, ind,
212 R_RISCV_PCREL_HI20, sv->c.i);
213 fc = 0;
214 sv->c.i = 0;
215 } else {
216 if (((unsigned)fc + (1 << 11)) >> 12)
217 tcc_error("unimp: large addend for global address");
218 greloca(cur_text_section, sv->sym, ind,
219 R_RISCV_GOT_HI20, 0);
220 doload = 1;
221 }
222 if (!label.v) {
223 label.v = tok_alloc(".L0 ", 4)->tok;
224 label.type.t = VT_VOID | VT_STATIC;
225 }
226 label.c = 0; /* force new local ELF symbol */
227 put_extern_sym(&label, cur_text_section, ind, 0);
228 o(0x17 | (rr << 7)); // auipc RR, 0 %call(func)
229 greloca(cur_text_section, &label, ind,
230 R_RISCV_PCREL_LO12_I, 0);
231 rb = rr;
232 do32bit = 0;
233 }
234 if (is_float(sv->type.t) && bt != VT_LDOUBLE)
235 tcc_error("unimp: load(float)");
236 if (fc != sv->c.i) {
237 int64_t si = sv->c.i;
238 uint32_t pi;
239 si >>= 32;
240 if (si != 0) {
241 pi = si;
242 if (fc < 0)
243 pi++;
244 o(0x37 | (rr << 7) | (((pi + 0x800) & 0xfffff000))); // lui RR, up(up(fc))
245 EI(0x13, 0, rr, rr, (int)pi << 20 >> 20); // addi RR, RR, lo(up(fc))
246 EI(0x13, 1, rr, rr, 12); // slli RR, RR, 12
247 EI(0x13, 0, rr, rr, (fc + (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
248 EI(0x13, 1, rr, rr, 12); // slli RR, RR, 12
249 fc = fc << 12 >> 12;
250 EI(0x13, 0, rr, rr, fc >> 8); // addi RR, RR, lo1(lo(fc))
251 EI(0x13, 1, rr, rr, 8); // slli RR, RR, 8
252 fc &= 0xff;
253 rb = rr;
254 do32bit = 0;
255 } else {
256 /* A 32bit unsigned constant. lui always sign extends, so we need
257 tricks. */
258 pi = (uint32_t)sv->c.i;
259 o(0x37 | (rr << 7) | (((pi + 0x80000) & 0xfff00000) >> 8)); // lui RR, up(fc)>>8
260 EI(0x13, 0, rr, rr, (((pi + 0x200) & 0x000ffc00) >> 8) | (-((int)(pi + 0x200) & 0x80000) >> 8)); // addi RR, RR, mid(fc)
261 EI(0x13, 1, rr, rr, 8); // slli RR, RR, 8
262 fc = (pi & 0x3ff) | (-((int)(pi & 0x200)));
263 rb = rr;
264 do32bit = 0;
265 }
266 }
267 if (((unsigned)fc + (1 << 11)) >> 12)
268 o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)), rb = rr; //lui RR, upper(fc)
269 if (doload) {
270 EI(0x03, 3, rr, rr, 0); // ld RR, 0(RR)
271 if (fc)
272 EI(0x13 | do32bit, 0, rr, rr, fc << 20 >> 20); // addi[w] R, x0|R, FC
273 } else
274 EI(0x13 | do32bit, 0, rr, rb, fc << 20 >> 20); // addi[w] R, x0|R, FC
275 } else if (v == VT_LOCAL) {
276 int br = 8; // s0
277 assert(is_ireg(r));
278 if (fc != sv->c.i)
279 tcc_error("unimp: load(addr giant local ofs) (0xll%x)", (long long)sv->c.i);
280 if (((unsigned)fc + (1 << 11)) >> 12) {
281 o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)); //lui RR, upper(fc)
282 o(0x33 | (rr << 7) | (rr << 15) | (8 << 20)); // add RR, RR, s0
283 fc = fc << 20 >> 20;
284 br = rr;
285 }
286 EI(0x13, 0, rr, br, fc); // addi R, s0, FC
287 } else if (v < VT_CONST) {
288 /* reg-reg */
289 //assert(!fc); XXX support offseted regs
290 if (is_freg(r) && is_freg(v))
291 o(0x53 | (rr << 7) | (freg(v) << 15) | (freg(v) << 20) | ((bt == VT_DOUBLE ? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
292 else if (is_ireg(r) && is_ireg(v))
293 EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
294 else {
295 int func7 = is_ireg(r) ? 0x70 : 0x78;
296 if (size == 8)
297 func7 |= 1;
298 assert(size == 4 || size == 8);
299 o(0x53 | (rr << 7) | ((is_freg(v) ? freg(v) : ireg(v)) << 15)
300 | (func7 << 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
301 }
302 } else if (v == VT_CMP) { // we rely on cmp_r to be the correct result
303 EI(0x13, 0, rr, vtop->cmp_r, 0); // mv RR, CMP_R
304 } else if ((v & ~1) == VT_JMP) {
305 int t = v & 1;
306 assert(is_ireg(r));
307 EI(0x13, 0, rr, 0, t); // addi RR, x0, t
308 gjmp_addr(ind + 8);
309 gsym(fc);
310 EI(0x13, 0, rr, 0, t ^ 1); // addi RR, x0, !t
311 } else
312 tcc_error("unimp: load(non-const)");
313 }
314
315 ST_FUNC void store(int r, SValue *sv)
316 {
317 int fr = sv->r & VT_VALMASK;
318 int rr = is_ireg(r) ? ireg(r) : freg(r);
319 int fc = sv->c.i;
320 int ft = sv->type.t;
321 int bt = ft & VT_BTYPE;
322 int align, size = type_size(&sv->type, &align);
323 assert(!is_float(bt) || is_freg(r) || bt == VT_LDOUBLE);
324 /* long doubles are in two integer registers, but the load/store
325 primitives only deal with one, so do as if it's one reg. */
326 if (bt == VT_LDOUBLE)
327 size = align = 8;
328 if (bt == VT_STRUCT)
329 tcc_error("unimp: store(struct)");
330 if (size > 8)
331 tcc_error("unimp: large sized store");
332 assert(sv->r & VT_LVAL);
333 if (fr == VT_LOCAL) {
334 int br = 8; // s0
335 if (fc != sv->c.i)
336 tcc_error("unimp: store(giant local off) (0x%llx)", (long long)sv->c.i);
337 if (((unsigned)fc + (1 << 11)) >> 12) {
338 br = ireg(get_reg(RC_INT));
339 o(0x37 | (br << 7) | ((0x800 + fc) & 0xfffff000)); //lui BR, upper(fc)
340 o(0x33 | (br << 7) | (br << 15) | (8 << 20)); // add BR, BR, s0
341 fc = fc << 20 >> 20;
342 }
343 if (is_freg(r))
344 ES(0x27, size == 4 ? 2 : 3, br, rr, fc); // fs[wd] RR, fc(base)
345 else
346 ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
347 br, rr, fc); // s[bhwd] RR, fc(base)
348 } else if (fr < VT_CONST) {
349 int ptrreg = ireg(fr);
350 /*if (((unsigned)fc + (1 << 11)) >> 12)
351 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
352 fc = 0; // XXX support offsets regs
353 if (is_freg(r))
354 ES(0x27, size == 4 ? 2 : 3, ptrreg, rr, fc); // fs[wd] RR, fc(PTRREG)
355 else
356 ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
357 ptrreg, rr, fc); // s[bhwd] RR, fc(PTRREG)
358 } else if (sv->r == (VT_CONST | VT_SYM | VT_LVAL)) {
359 static Sym label;
360 int tempr, addend = 0;
361 if (1 || ((unsigned)fc + (1 << 11)) >> 12)
362 addend = fc, fc = 0;
363
364 tempr = ireg(get_reg(RC_INT));
365 greloca(cur_text_section, sv->sym, ind,
366 R_RISCV_PCREL_HI20, addend);
367 if (!label.v) {
368 label.v = tok_alloc(".L0 ", 4)->tok;
369 label.type.t = VT_VOID | VT_STATIC;
370 }
371 label.c = 0; /* force new local ELF symbol */
372 put_extern_sym(&label, cur_text_section, ind, 0);
373 o(0x17 | (tempr << 7)); // auipc TEMPR, 0 %pcrel_hi(sym)+addend
374 greloca(cur_text_section, &label, ind,
375 R_RISCV_PCREL_LO12_S, 0);
376 if (is_freg(r))
377 ES(0x27, size == 4 ? 2 : 3, tempr, rr, fc); // fs[wd] RR, fc(TEMPR)
378 else
379 ES(0x23, size == 1 ? 0 : size == 2 ? 1 : size == 4 ? 2 : 3,
380 tempr, rr, fc); // s[bhwd] RR, fc(TEMPR)
381 } else
382 tcc_error("implement me: %s(!local)", __FUNCTION__);
383 }
384
385 static void gcall(void)
386 {
387 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
388 ((vtop->r & VT_SYM) && vtop->c.i == (int)vtop->c.i)) {
389 /* constant symbolic case -> simple relocation */
390 greloca(cur_text_section, vtop->sym, ind,
391 R_RISCV_CALL_PLT, (int)vtop->c.i);
392 o(0x17 | (1 << 7)); // auipc ra, 0 %call(func)
393 o(0x80e7); // jalr ra, 0 %call(func)
394 } else if (vtop->r < VT_CONST) {
395 int r = ireg(vtop->r);
396 EI(0x67, 0, 1, r, 0); // jalr ra, 0(R)
397 } else {
398 int r = TREG_RA;
399 load(r, vtop);
400 r = ireg(r);
401 EI(0x67, 0, 1, r, 0); // jalr ra, 0(R)
402 }
403 }
404
405 ST_FUNC void gfunc_call(int nb_args)
406 {
407 int i, align, size, aireg, afreg;
408 int info[nb_args ? nb_args : 1];
409 int stack_adj = 0, tempspace = 0, ofs, splitofs = 0;
410 int force_stack = 0;
411 SValue *sv;
412 Sym *sa;
413 aireg = afreg = 0;
414 sa = vtop[-nb_args].type.ref->next;
415 for (i = 0; i < nb_args; i++) {
416 int *pareg, nregs, infreg = 0, byref = 0, tempofs;
417 sv = &vtop[1 + i - nb_args];
418 sv->type.t &= ~VT_ARRAY; // XXX this should be done in tccgen.c
419 size = type_size(&sv->type, &align);
420 if (size > 16) {
421 if (align < XLEN)
422 align = XLEN;
423 tempspace = (tempspace + align - 1) & -align;
424 tempofs = tempspace;
425 tempspace += size;
426 size = align = 8;
427 byref = 1;
428 }
429 if (size > 8)
430 nregs = 2;
431 else
432 nregs = 1;
433 if ((sv->type.t & VT_BTYPE) == VT_LDOUBLE) {
434 infreg = 0;
435 } else
436 infreg = sa && is_float(sv->type.t);
437 if (!infreg && !sa && align == 2*XLEN && size <= 2*XLEN)
438 aireg = (aireg + 1) & ~1;
439 pareg = infreg ? &afreg : &aireg;
440 if ((*pareg < 8) && !force_stack) {
441 info[i] = *pareg + (infreg ? 8 : 0);
442 (*pareg)++;
443 if (nregs == 1)
444 ;
445 else if (*pareg < 8)
446 (*pareg)++;
447 else {
448 info[i] |= 16;
449 stack_adj += 8;
450 }
451 } else {
452 info[i] = 32;
453 if (align < XLEN)
454 align = XLEN;
455 stack_adj += (size + align - 1) & -align;
456 if (!sa)
457 force_stack = 1;
458 }
459 if (byref)
460 info[i] |= 64 | (tempofs << 7);
461 if (sa)
462 sa = sa->next;
463 }
464 stack_adj = (stack_adj + 15) & -16;
465 tempspace = (tempspace + 15) & -16;
466 if (stack_adj + tempspace) {
467 EI(0x13, 0, 2, 2, -(stack_adj + tempspace)); // addi sp, sp, -adj
468 for (i = ofs = 0; i < nb_args; i++) {
469 if (info[i] >= 32) {
470 vrotb(nb_args - i);
471 size = type_size(&vtop->type, &align);
472 if (info[i] & 64) {
473 vset(&char_pointer_type, TREG_SP, 0);
474 vpushi(stack_adj + (info[i] >> 7));
475 gen_op('+');
476 vpushv(vtop); // this replaces the old argument
477 vrott(3);
478 indir();
479 vtop->type = vtop[-1].type;
480 vswap();
481 vstore();
482 vpop();
483 size = align = 8;
484 }
485 if (info[i] & 32) {
486 if (align < XLEN)
487 align = XLEN;
488 /* Once we support offseted regs we can do this:
489 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
490 to construct the lvalue for the outgoing stack slot,
491 until then we have to jump through hoops. */
492 vset(&char_pointer_type, TREG_SP, 0);
493 ofs = (ofs + align - 1) & -align;
494 vpushi(ofs);
495 gen_op('+');
496 indir();
497 vtop->type = vtop[-1].type;
498 vswap();
499 vstore();
500 vtop->r = vtop->r2 = VT_CONST; // this arg is done
501 ofs += size;
502 }
503 vrott(nb_args - i);
504 } else if (info[i] & 16) {
505 assert(!splitofs);
506 splitofs = ofs;
507 ofs += 8;
508 }
509 }
510 }
511 for (i = 0; i < nb_args; i++) {
512 int r = info[nb_args - 1 - i];
513 if (!(r & 32)) {
514 CType origtype;
515 r &= 15;
516 vrotb(i+1);
517 origtype = vtop->type;
518 size = type_size(&vtop->type, &align);
519 if (size > 8 && (vtop->type.t & VT_BTYPE) == VT_STRUCT)
520 vtop->type.t = VT_LDOUBLE; // force loading a pair of regs
521 gv(r < 8 ? RC_R(r) : RC_F(r - 8));
522 vtop->type = origtype;
523 if (size > 8) {
524 assert((vtop->type.t & VT_BTYPE) == VT_LDOUBLE
525 || (vtop->type.t & VT_BTYPE) == VT_STRUCT);
526 assert(vtop->r2 < VT_CONST);
527 if (info[nb_args - 1 - i] & 16) {
528 ES(0x23, 3, 2, ireg(vtop->r2), splitofs); // sd t0, ofs(sp)
529 } else if (vtop->r2 != 1 + vtop->r) {
530 assert(vtop->r < 7);
531 /* XXX we'd like to have 'gv' move directly into
532 the right class instead of us fixing it up. */
533 EI(0x13, 0, ireg(vtop->r) + 1, ireg(vtop->r2), 0); // mv Ra+1, RR2
534 vtop->r2 = 1 + vtop->r;
535 }
536 }
537 vrott(i+1);
538 }
539 }
540 vrotb(nb_args + 1);
541 gcall();
542 vtop -= nb_args + 1;
543 if (stack_adj + tempspace)
544 EI(0x13, 0, 2, 2, stack_adj + tempspace); // addi sp, sp, adj
545 }
546
547 static int func_sub_sp_offset, num_va_regs;
548
549 ST_FUNC void gfunc_prolog(CType *func_type)
550 {
551 int i, addr, align, size;
552 int param_addr = 0;
553 int aireg, afreg;
554 Sym *sym;
555 CType *type;
556
557 sym = func_type->ref;
558 func_vt = sym->type;
559 loc = -16; // for ra and s0
560 func_sub_sp_offset = ind;
561 ind += 5 * 4;
562
563 aireg = afreg = 0;
564 addr = 0; // XXX not correct
565 /* if the function returns by reference, then add an
566 implicit pointer parameter */
567 size = type_size(&func_vt, &align);
568 if (size > 2 * XLEN) {
569 loc -= 8;
570 func_vc = loc;
571 ES(0x23, 3, 8, 10 + aireg, loc); // sd a0, loc(s0)
572 aireg++;
573 }
574 /* define parameters */
575 while ((sym = sym->next) != NULL) {
576 int byref = 0;
577 type = &sym->type;
578 size = type_size(type, &align);
579 if (size > 2 * XLEN) {
580 type = &char_pointer_type;
581 size = align = byref = 8;
582 }
583 if (size > 2 * XLEN) {
584 from_stack:
585 if (align < XLEN)
586 align = XLEN;
587 addr = (addr + align - 1) & -align;
588 param_addr = addr;
589 addr += size;
590 } else {
591 int regcount = 1, *pareg = &aireg;
592 if (is_float(type->t) && (type->t & VT_BTYPE) != VT_LDOUBLE)
593 pareg = &afreg;
594 if (regcount + *pareg > 8)
595 goto from_stack;
596 if (size > XLEN)
597 regcount++;
598 loc -= regcount * 8; // XXX could reserve only 'size' bytes
599 param_addr = loc;
600 for (i = 0; i < regcount; i++) {
601 if (*pareg >= 8) {
602 assert(i == 1 && regcount == 2 && !(addr & 7));
603 EI(0x03, 3, 5, 8, addr); // ld t0, addr(s0)
604 addr += 8;
605 ES(0x23, 3, 8, 5, loc + i*8); // sd t0, loc(s0)
606 continue;
607 }
608 if (pareg == &afreg) {
609 assert(type->t == VT_FLOAT || type->t == VT_DOUBLE);
610 ES(0x27, size == 4 ? 2 : 3, 8, 10 + *pareg, loc + i*8); // fs[wd] FAi, loc(s0)
611 } else {
612 ES(0x23, 3, 8, 10 + *pareg, loc + i*8); // sd aX, loc(s0) // XXX
613 }
614 (*pareg)++;
615 }
616 }
617 sym_push(sym->v & ~SYM_FIELD, &sym->type,
618 (byref ? VT_LLOCAL : VT_LOCAL) | lvalue_type(sym->type.t),
619 param_addr);
620 }
621 num_va_regs = 0;
622 if (func_type->ref->f.func_type == FUNC_ELLIPSIS) {
623 for (; aireg < 8; aireg++) {
624 num_va_regs++;
625 ES(0x23, 3, 8, 10 + aireg, -8 + num_va_regs * 8); // sd aX, loc(s0)
626 }
627 }
628 }
629
630 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret,
631 int *ret_align, int *regsize)
632 {
633 /* generic code can only deal with structs of pow(2) sizes
634 (it always deals with whole registers), so go through our own
635 code. */
636 int align, size = type_size(vt, &align);
637 *ret_align = 1;
638 *regsize = 8;
639 if (size > 16)
640 return 0;
641 if (size > 8)
642 ret->t = VT_LLONG;
643 else if (size > 4)
644 ret->t = VT_LLONG;
645 else if (size > 2)
646 ret->t = VT_INT;
647 else if (size > 1)
648 ret->t = VT_SHORT;
649 else
650 ret->t = VT_BYTE;
651 return (size + 7) / 8;
652 }
653
654 ST_FUNC void gfunc_return(CType *func_type)
655 {
656 int align, size = type_size(func_type, &align), nregs;
657 CType type = *func_type;
658 if (size > 2 * XLEN) {
659 mk_pointer(&type);
660 vset(&type, VT_LOCAL | VT_LVAL, func_vc);
661 indir();
662 vswap();
663 vstore();
664 vpop();
665 return;
666 }
667 nregs = (size + 7) / 8;
668 if (nregs == 2)
669 vtop->type.t = VT_LDOUBLE;
670
671 if (is_float(func_type->t) && (vtop->type.t & VT_BTYPE) != VT_LDOUBLE)
672 gv(RC_FRET);
673 else
674 gv(RC_IRET);
675 vtop--;
676 }
677
678 ST_FUNC void gfunc_epilog(void)
679 {
680 int v, saved_ind, d, large_ofs_ind;
681
682 loc = (loc - num_va_regs * 8);
683 d = v = (-loc + 15) & -16;
684
685 if (v >= (1 << 11)) {
686 d = 16;
687 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
688 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
689 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20)); //add sp, sp, t0
690 }
691 EI(0x03, 3, 1, 2, d - 8 - num_va_regs * 8); // ld ra, v-8(sp)
692 EI(0x03, 3, 8, 2, d - 16 - num_va_regs * 8); // ld s0, v-16(sp)
693 EI(0x13, 0, 2, 2, d); // addi sp, sp, v
694 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
695 if (v >= (1 << 11)) {
696 large_ofs_ind = ind;
697 EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
698 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
699 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
700 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20) | (0x20 << 25)); //sub sp, sp, t0
701 gjmp_addr(func_sub_sp_offset + 5*4);
702 }
703 saved_ind = ind;
704
705 ind = func_sub_sp_offset;
706 EI(0x13, 0, 2, 2, -d); // addi sp, sp, -d
707 ES(0x23, 3, 2, 1, d - 8 - num_va_regs * 8); // sd ra, d-8(sp)
708 ES(0x23, 3, 2, 8, d - 16 - num_va_regs * 8); // sd s0, d-16(sp)
709 if (v < (1 << 11))
710 EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
711 else
712 gjmp_addr(large_ofs_ind);
713 if ((ind - func_sub_sp_offset) != 5*4)
714 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
715 ind = saved_ind;
716 }
717
718 ST_FUNC void gen_va_start(void)
719 {
720 tcc_error("implement me: %s", __FUNCTION__);
721 }
722
723 ST_FUNC void gen_va_arg(CType *t)
724 {
725 tcc_error("implement me: %s", __FUNCTION__);
726 }
727
728 ST_FUNC void gen_fill_nops(int bytes)
729 {
730 tcc_error("implement me: %s", __FUNCTION__);
731 if ((bytes & 3))
732 tcc_error("alignment of code section not multiple of 4");
733 }
734
735 // Generate forward branch to label:
736 ST_FUNC int gjmp(int t)
737 {
738 if (nocode_wanted)
739 return t;
740 o(t);
741 return ind - 4;
742 }
743
744 // Generate branch to known address:
745 ST_FUNC void gjmp_addr(int a)
746 {
747 uint32_t r = a - ind, imm;
748 if ((r + (1 << 21)) & ~((1U << 22) - 2)) {
749 o(0x17 | (5 << 7) | (((r + 0x800) & 0xfffff000))); // lui RR, up(r)
750 r = (int)r << 20 >> 20;
751 EI(0x67, 0, 0, 5, r); // jalr x0, r(t0)
752 } else {
753 imm = (((r >> 12) & 0xff) << 12)
754 | (((r >> 11) & 1) << 20)
755 | (((r >> 1) & 0x3ff) << 21)
756 | (((r >> 20) & 1) << 31);
757 o(0x6f | imm); // jal x0, imm == j imm
758 }
759 }
760
761 ST_FUNC int gjmp_cond(int op, int t)
762 {
763 int inv = op & 1;
764 assert(op == TOK_EQ || op == TOK_NE);
765 assert(vtop->cmp_r >= 10 && vtop->cmp_r < 18);
766 o(0x63 | (!inv << 12) | (vtop->cmp_r << 15) | (8 << 7)); // bne/beq x0,r,+4
767 return gjmp(t);
768 }
769
770 ST_FUNC int gjmp_append(int n, int t)
771 {
772 void *p;
773 /* insert jump list n into t */
774 if (n) {
775 uint32_t n1 = n, n2;
776 while ((n2 = read32le(p = cur_text_section->data + n1)))
777 n1 = n2;
778 write32le(p, t);
779 t = n;
780 }
781 return t;
782 }
783
784 static void gen_opil(int op, int ll)
785 {
786 int a, b, d;
787 int inv = 0;
788 int func3 = 0, func7 = 0;
789 /* XXX We could special-case some constant args. */
790 gv2(RC_INT, RC_INT);
791 a = ireg(vtop[-1].r);
792 b = ireg(vtop[0].r);
793 vtop -= 2;
794 d = get_reg(RC_INT);
795 vtop++;
796 vtop[0].r = d;
797 d = ireg(d);
798 ll = ll ? 0 : 8;
799 switch (op) {
800 case TOK_PDIV:
801 default:
802 tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
803
804 case '+':
805 o(0x33 | (d << 7) | (a << 15) | (b << 20)); // add d, a, b
806 break;
807 case '-':
808 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b
809 break;
810 case TOK_SAR:
811 o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b
812 break;
813 case TOK_SHR:
814 o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b
815 break;
816 case TOK_SHL:
817 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b
818 break;
819 case '*':
820 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25)); //mul d, a, b
821 break;
822 case '/':
823 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
824 break;
825 case '&':
826 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (7 << 12)); // and d, a, b
827 break;
828 case '^':
829 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (4 << 12)); // xor d, a, b
830 break;
831 case '|':
832 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (6 << 12)); // or d, a, b
833 break;
834 case '%':
835 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (6 << 12)); //rem d, a, b
836 break;
837 case TOK_UMOD:
838 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (7 << 12)); //remu d, a, b
839 break;
840 case TOK_UDIV:
841 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (5 << 12)); //divu d, a, b
842 break;
843
844 case TOK_ULT:
845 case TOK_UGE:
846 case TOK_ULE:
847 case TOK_UGT:
848 case TOK_LT:
849 case TOK_GE:
850 case TOK_LE:
851 case TOK_GT:
852 if (op & 1) { // remove [U]GE,GT
853 inv = 1;
854 op--;
855 }
856 if ((op & 7) == 6) { // [U]LE
857 int t = a; a = b; b = t;
858 inv ^= 1;
859 }
860 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (((op > TOK_UGT) ? 2 : 3) << 12)); // slt[u] d, a, b
861 if (inv)
862 EI(0x13, 4, d, d, 1); // xori d, d, 1
863 vset_VT_CMP(TOK_NE);
864 vtop->cmp_r = d;
865 break;
866 case TOK_NE:
867 case TOK_EQ:
868 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); // sub d, a, b
869 if (op == TOK_NE)
870 o(0x33 | (3 << 12) | (d << 7) | (0 << 15) | (d << 20)); // sltu d, x0, d == snez d,d
871 else
872 EI(0x13, 3, d, d, 1); // sltiu d, d, 1 == seqz d,d
873 vset_VT_CMP(TOK_NE);
874 vtop->cmp_r = d;
875 break;
876 }
877 }
878
879 ST_FUNC void gen_opi(int op)
880 {
881 gen_opil(op, 0);
882 }
883
884 ST_FUNC void gen_opl(int op)
885 {
886 gen_opil(op, 1);
887 }
888
889 ST_FUNC void gen_opf(int op)
890 {
891 int rs1, rs2, rd, dbl, invert;
892 gv2(RC_FLOAT, RC_FLOAT);
893 assert(vtop->type.t == VT_DOUBLE || vtop->type.t == VT_FLOAT);
894 dbl = vtop->type.t == VT_DOUBLE;
895 rs1 = freg(vtop[-1].r);
896 rs2 = freg(vtop->r);
897 vtop--;
898 invert = 0;
899 switch(op) {
900 default:
901 assert(0);
902 case '+':
903 op = 0; // fadd
904 arithop:
905 rd = get_reg(RC_FLOAT);
906 vtop->r = rd;
907 rd = freg(rd);
908 o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (7 << 12) | (dbl << 25) | (op << 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)
909 break;
910 case '-':
911 op = 1; // fsub
912 goto arithop;
913 case '*':
914 op = 2; // fmul
915 goto arithop;
916 case '/':
917 op = 3; // fdiv
918 goto arithop;
919 case TOK_EQ:
920 op = 2; // EQ
921 cmpop:
922 rd = get_reg(RC_INT);
923 vtop->r = rd;
924 rd = ireg(rd);
925 o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (op << 12) | (dbl << 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
926 if (invert)
927 EI(0x13, 4, rd, rd, 1); // xori RD, 1
928 break;
929 case TOK_NE:
930 invert = 1;
931 op = 2; // EQ
932 goto cmpop;
933 case TOK_LT:
934 op = 1; // LT
935 goto cmpop;
936 case TOK_LE:
937 op = 0; // LE
938 goto cmpop;
939 case TOK_GT:
940 op = 1; // LT
941 rd = rs1, rs1 = rs2, rs2 = rd;
942 goto cmpop;
943 case TOK_GE:
944 op = 0; // LE
945 rd = rs1, rs1 = rs2, rs2 = rd;
946 goto cmpop;
947 }
948 }
949
950 ST_FUNC void gen_cvt_sxtw(void)
951 {
952 /* XXX on risc-v the registers are usually sign-extended already.
953 Let's try to not do anything here. */
954 }
955
956 ST_FUNC void gen_cvt_itof(int t)
957 {
958 tcc_error("implement me: %s", __FUNCTION__);
959 }
960
961 ST_FUNC void gen_cvt_ftoi(int t)
962 {
963 tcc_error("implement me: %s", __FUNCTION__);
964 }
965
966 ST_FUNC void gen_cvt_ftof(int dt)
967 {
968 int st = vtop->type.t & VT_BTYPE, rs, rd;
969 dt &= VT_BTYPE;
970 if (st == dt)
971 return;
972 if (dt == VT_LDOUBLE || st == VT_LDOUBLE) {
973 int func = (dt == VT_LDOUBLE) ?
974 (st == VT_FLOAT ? TOK___extendsftf2 : TOK___extenddftf2) :
975 (st == VT_FLOAT ? TOK___trunctfsf2 : TOK___trunctfdf2);
976 vpush_global_sym(&func_old_type, func);
977 vrott(2);
978 gfunc_call(1);
979 vpushi(0);
980 vtop->type.t = dt;
981 if (dt == VT_LDOUBLE)
982 vtop->r = REG_IRET, vtop->r2 = REG_IRET+1;
983 else
984 vtop->r = REG_FRET;
985 } else {
986 assert (dt == VT_FLOAT || dt == VT_DOUBLE);
987 assert (st == VT_FLOAT || st == VT_DOUBLE);
988 rs = gv(RC_FLOAT);
989 rd = get_reg(RC_FLOAT);
990 if (dt == VT_DOUBLE)
991 EI(0x53, 7, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
992 else
993 EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS
994 vtop->r = rd;
995 }
996 }
997
998 ST_FUNC void ggoto(void)
999 {
1000 tcc_error("implement me: %s", __FUNCTION__);
1001 }
1002
1003 ST_FUNC void gen_vla_sp_save(int addr)
1004 {
1005 ES(0x23, 3, 8, 2, addr); // sd sp, fc(s0)
1006 }
1007
1008 ST_FUNC void gen_vla_sp_restore(int addr)
1009 {
1010 EI(0x03, 3, 2, 8, addr); // ld sp, fc(s0)
1011 }
1012
1013 ST_FUNC void gen_vla_alloc(CType *type, int align)
1014 {
1015 int rr = ireg(gv(RC_INT));
1016 EI(0x13, 0, rr, rr, 15); // addi RR, RR, 15
1017 EI(0x13, 7, rr, rr, -16); // andi, RR, RR, -16
1018 o(0x33 | (2 << 7) | (2 << 15) | (rr << 20) | (0x20 << 25)); //sub sp, sp, rr
1019 vpop();
1020 }
1021 #endif
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