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x86_64: Use addend on relocs
[tinycc.git] / i386-asm.c
blob435dd15a849a93febdc98bccb178ca5985ab7080
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include "tcc.h"
23
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
27
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_pxor
31
32 #define OPC_JMP 0x01 /* jmp operand */
33 #define OPC_B 0x02 /* only used with OPC_WL */
34 #define OPC_WL 0x04 /* accepts w, l or no suffix */
35 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
36 #define OPC_REG 0x08 /* register is added to opcode */
37 #define OPC_MODRM 0x10 /* modrm encoding */
38 #define OPC_FWAIT 0x20 /* add fwait opcode */
39 #define OPC_TEST 0x40 /* test opcodes */
40 #define OPC_SHIFT 0x80 /* shift opcodes */
41 #define OPC_D16 0x0100 /* generate data16 prefix */
42 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
43 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
44 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
45 #ifdef TCC_TARGET_X86_64
46 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
47 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
48 # define OPC_WLX OPC_WLQ
49 #else
50 # define OPC_WLX OPC_WL
51 #endif
52
53 #define OPC_GROUP_SHIFT 13
54
55 /* in order to compress the operand type, we use specific operands and
56 we or only with EA */
57 enum {
58 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
59 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
60 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
61 #ifdef TCC_TARGET_X86_64
62 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
63 #endif
64 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
65 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
66 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
67 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SEG,
70 OPT_ST,
71 OPT_IM8,
72 OPT_IM8S,
73 OPT_IM16,
74 OPT_IM32,
75 #ifdef TCC_TARGET_X86_64
76 OPT_IM64,
77 #endif
78 OPT_EAX, /* %al, %ax, %eax or %rax register */
79 OPT_ST0, /* %st(0) register */
80 OPT_CL, /* %cl register */
81 OPT_DX, /* %dx register */
82 OPT_ADDR, /* OP_EA with only offset */
83 OPT_INDIR, /* *(expr) */
84 /* composite types */
85 OPT_COMPOSITE_FIRST,
86 OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
87 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
88 OPT_REGW, /* REG16 | REG32 | REG64 */
89 OPT_IMW, /* IM16 | IM32 | IM64 */
90 #ifdef TCC_TARGET_X86_64
91 OPT_IMNO64, /* IM16 | IM32 */
92 #endif
93 /* can be ored with any OPT_xxx */
94 OPT_EA = 0x80
95 };
96
97 #define OP_REG8 (1 << OPT_REG8)
98 #define OP_REG16 (1 << OPT_REG16)
99 #define OP_REG32 (1 << OPT_REG32)
100 #define OP_MMX (1 << OPT_MMX)
101 #define OP_SSE (1 << OPT_SSE)
102 #define OP_CR (1 << OPT_CR)
103 #define OP_TR (1 << OPT_TR)
104 #define OP_DB (1 << OPT_DB)
105 #define OP_SEG (1 << OPT_SEG)
106 #define OP_ST (1 << OPT_ST)
107 #define OP_IM8 (1 << OPT_IM8)
108 #define OP_IM8S (1 << OPT_IM8S)
109 #define OP_IM16 (1 << OPT_IM16)
110 #define OP_IM32 (1 << OPT_IM32)
111 #define OP_EAX (1 << OPT_EAX)
112 #define OP_ST0 (1 << OPT_ST0)
113 #define OP_CL (1 << OPT_CL)
114 #define OP_DX (1 << OPT_DX)
115 #define OP_ADDR (1 << OPT_ADDR)
116 #define OP_INDIR (1 << OPT_INDIR)
117 #ifdef TCC_TARGET_X86_64
118 # define OP_REG64 (1 << OPT_REG64)
119 # define OP_IM64 (1 << OPT_IM64)
120 # define OP_EA32 (OP_EA << 1)
121 #else
122 # define OP_REG64 0
123 # define OP_IM64 0
124 # define OP_EA32 0
125 #endif
126
127 #define OP_EA 0x40000000
128 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
129
130 #ifdef TCC_TARGET_X86_64
131 # define OP_IM OP_IM64
132 # define TREG_XAX TREG_RAX
133 # define TREG_XCX TREG_RCX
134 # define TREG_XDX TREG_RDX
135 #else
136 # define OP_IM OP_IM32
137 # define TREG_XAX TREG_EAX
138 # define TREG_XCX TREG_ECX
139 # define TREG_XDX TREG_EDX
140 #endif
141
142 typedef struct ASMInstr {
143 uint16_t sym;
144 uint16_t opcode;
145 uint16_t instr_type;
146 uint8_t nb_ops;
147 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
148 } ASMInstr;
149
150 typedef struct Operand {
151 uint32_t type;
152 int8_t reg; /* register, -1 if none */
153 int8_t reg2; /* second register, -1 if none */
154 uint8_t shift;
155 ExprValue e;
156 } Operand;
157
158 static const uint8_t reg_to_size[9] = {
159 /*
160 [OP_REG8] = 0,
161 [OP_REG16] = 1,
162 [OP_REG32] = 2,
163 #ifdef TCC_TARGET_X86_64
164 [OP_REG64] = 3,
165 #endif
166 */
167 0, 0, 1, 0, 2, 0, 0, 0, 3
168 };
169
170 #define NB_TEST_OPCODES 30
171
172 static const uint8_t test_bits[NB_TEST_OPCODES] = {
173 0x00, /* o */
174 0x01, /* no */
175 0x02, /* b */
176 0x02, /* c */
177 0x02, /* nae */
178 0x03, /* nb */
179 0x03, /* nc */
180 0x03, /* ae */
181 0x04, /* e */
182 0x04, /* z */
183 0x05, /* ne */
184 0x05, /* nz */
185 0x06, /* be */
186 0x06, /* na */
187 0x07, /* nbe */
188 0x07, /* a */
189 0x08, /* s */
190 0x09, /* ns */
191 0x0a, /* p */
192 0x0a, /* pe */
193 0x0b, /* np */
194 0x0b, /* po */
195 0x0c, /* l */
196 0x0c, /* nge */
197 0x0d, /* nl */
198 0x0d, /* ge */
199 0x0e, /* le */
200 0x0e, /* ng */
201 0x0f, /* nle */
202 0x0f, /* g */
203 };
204
205 static const uint8_t segment_prefixes[] = {
206 0x26, /* es */
207 0x2e, /* cs */
208 0x36, /* ss */
209 0x3e, /* ds */
210 0x64, /* fs */
211 0x65 /* gs */
212 };
213
214 static const ASMInstr asm_instrs[] = {
215 #define ALT(x) x
216 #define DEF_ASM_OP0(name, opcode)
217 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
218 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
219 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
220 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
221 #ifdef TCC_TARGET_X86_64
222 # include "x86_64-asm.h"
223 #else
224 # include "i386-asm.h"
225 #endif
226 /* last operation */
227 { 0, },
228 };
229
230 static const uint16_t op0_codes[] = {
231 #define ALT(x)
232 #define DEF_ASM_OP0(x, opcode) opcode,
233 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
234 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
235 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
236 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
237 #ifdef TCC_TARGET_X86_64
238 # include "x86_64-asm.h"
239 #else
240 # include "i386-asm.h"
241 #endif
242 };
243
244 static inline int get_reg_shift(TCCState *s1)
245 {
246 int shift, v;
247 #ifdef I386_ASM_16
248 if (s1->seg_size == 16)
249 tcc_error("invalid effective address");
250 #endif
251 v = asm_int_expr(s1);
252 switch(v) {
253 case 1:
254 shift = 0;
255 break;
256 case 2:
257 shift = 1;
258 break;
259 case 4:
260 shift = 2;
261 break;
262 case 8:
263 shift = 3;
264 break;
265 default:
266 expect("1, 2, 4 or 8 constant");
267 shift = 0;
268 break;
269 }
270 return shift;
271 }
272
273 static int asm_parse_reg(int *type)
274 {
275 int reg = 0;
276 *type = 0;
277 if (tok != '%')
278 goto error_32;
279 next();
280 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
281 reg = tok - TOK_ASM_eax;
282 #ifdef TCC_TARGET_X86_64
283 *type = OP_EA32;
284 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
285 reg = tok - TOK_ASM_rax;
286 #endif
287 #ifdef I386_ASM_16
288 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
289 reg = tok - TOK_ASM_ax;
290 #endif
291 } else {
292 error_32:
293 expect("register");
294 }
295 next();
296 return reg;
297 }
298
299 static void parse_operand(TCCState *s1, Operand *op)
300 {
301 ExprValue e;
302 int reg, indir;
303 const char *p;
304
305 indir = 0;
306 if (tok == '*') {
307 next();
308 indir = OP_INDIR;
309 }
310
311 if (tok == '%') {
312 next();
313 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
314 reg = tok - TOK_ASM_al;
315 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
316 op->reg = reg & 7;
317 if ((op->type & OP_REG) && op->reg == TREG_XAX)
318 op->type |= OP_EAX;
319 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
320 op->type |= OP_CL;
321 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
322 op->type |= OP_DX;
323 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
324 op->type = OP_DB;
325 op->reg = tok - TOK_ASM_dr0;
326 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
327 op->type = OP_SEG;
328 op->reg = tok - TOK_ASM_es;
329 } else if (tok == TOK_ASM_st) {
330 op->type = OP_ST;
331 op->reg = 0;
332 next();
333 if (tok == '(') {
334 next();
335 if (tok != TOK_PPNUM)
336 goto reg_error;
337 p = tokc.str.data;
338 reg = p[0] - '0';
339 if ((unsigned)reg >= 8 || p[1] != '\0')
340 goto reg_error;
341 op->reg = reg;
342 next();
343 skip(')');
344 }
345 if (op->reg == 0)
346 op->type |= OP_ST0;
347 goto no_skip;
348 } else {
349 reg_error:
350 tcc_error("unknown register");
351 }
352 next();
353 no_skip: ;
354 } else if (tok == '$') {
355 /* constant value */
356 next();
357 asm_expr(s1, &e);
358 op->type = OP_IM;
359 op->e.v = e.v;
360 op->e.sym = e.sym;
361 if (!op->e.sym) {
362 if (op->e.v == (uint8_t)op->e.v)
363 op->type |= OP_IM8;
364 if (op->e.v == (int8_t)op->e.v)
365 op->type |= OP_IM8S;
366 if (op->e.v == (uint16_t)op->e.v)
367 op->type |= OP_IM16;
368 #ifdef TCC_TARGET_X86_64
369 if (op->e.v == (uint32_t)op->e.v)
370 op->type |= OP_IM32;
371 #endif
372 }
373 } else {
374 /* address(reg,reg2,shift) with all variants */
375 op->type = OP_EA;
376 op->reg = -1;
377 op->reg2 = -1;
378 op->shift = 0;
379 if (tok != '(') {
380 asm_expr(s1, &e);
381 op->e.v = e.v;
382 op->e.sym = e.sym;
383 } else {
384 next();
385 if (tok == '%') {
386 unget_tok('(');
387 op->e.v = 0;
388 op->e.sym = NULL;
389 } else {
390 /* bracketed offset expression */
391 asm_expr(s1, &e);
392 if (tok != ')')
393 expect(")");
394 next();
395 op->e.v = e.v;
396 op->e.sym = e.sym;
397 }
398 }
399 if (tok == '(') {
400 int type = 0;
401 next();
402 if (tok != ',') {
403 op->reg = asm_parse_reg(&type);
404 }
405 if (tok == ',') {
406 next();
407 if (tok != ',') {
408 op->reg2 = asm_parse_reg(&type);
409 }
410 if (tok == ',') {
411 next();
412 op->shift = get_reg_shift(s1);
413 }
414 }
415 if (type & OP_EA32)
416 op->type |= OP_EA32;
417 skip(')');
418 }
419 if (op->reg == -1 && op->reg2 == -1)
420 op->type |= OP_ADDR;
421 }
422 op->type |= indir;
423 }
424
425 /* XXX: unify with C code output ? */
426 ST_FUNC void gen_expr32(ExprValue *pe)
427 {
428 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
429 }
430
431 #ifdef TCC_TARGET_X86_64
432 static void gen_expr64(ExprValue *pe)
433 {
434 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
435 }
436 #endif
437
438 /* XXX: unify with C code output ? */
439 static void gen_disp32(ExprValue *pe)
440 {
441 Sym *sym = pe->sym;
442 if (sym && sym->r == cur_text_section->sh_num) {
443 /* same section: we can output an absolute value. Note
444 that the TCC compiler behaves differently here because
445 it always outputs a relocation to ease (future) code
446 elimination in the linker */
447 gen_le32(pe->v + sym->jnext - ind - 4);
448 } else {
449 if (sym && sym->type.t == VT_VOID) {
450 sym->type.t = VT_FUNC;
451 sym->type.ref = NULL;
452 }
453 gen_addrpc32(VT_SYM, sym, pe->v);
454 }
455 }
456
457 #ifdef I386_ASM_16
458 static void gen_expr16(ExprValue *pe)
459 {
460 if (pe->sym)
461 greloc(cur_text_section, pe->sym, ind, R_386_16);
462 gen_le16(pe->v);
463 }
464 static void gen_disp16(ExprValue *pe)
465 {
466 Sym *sym;
467 sym = pe->sym;
468 if (sym) {
469 if (sym->r == cur_text_section->sh_num) {
470 /* same section: we can output an absolute value. Note
471 that the TCC compiler behaves differently here because
472 it always outputs a relocation to ease (future) code
473 elimination in the linker */
474 gen_le16(pe->v + sym->jnext - ind - 2);
475 } else {
476 greloc(cur_text_section, sym, ind, R_386_PC16);
477 gen_le16(pe->v - 2);
478 }
479 } else {
480 /* put an empty PC32 relocation */
481 put_elf_reloc(symtab_section, cur_text_section,
482 ind, R_386_PC16, 0);
483 gen_le16(pe->v - 2);
484 }
485 }
486 #endif
487
488 /* generate the modrm operand */
489 static inline void asm_modrm(int reg, Operand *op)
490 {
491 int mod, reg1, reg2, sib_reg1;
492
493 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
494 g(0xc0 + (reg << 3) + op->reg);
495 } else if (op->reg == -1 && op->reg2 == -1) {
496 /* displacement only */
497 #ifdef I386_ASM_16
498 if (tcc_state->seg_size == 16) {
499 g(0x06 + (reg << 3));
500 gen_expr16(&op->e);
501 } else if (tcc_state->seg_size == 32)
502 #endif
503 {
504 #ifdef TCC_TARGET_X86_64
505 g(0x04 + (reg << 3));
506 g(0x25);
507 #else
508 g(0x05 + (reg << 3));
509 #endif
510 gen_expr32(&op->e);
511 }
512 } else {
513 sib_reg1 = op->reg;
514 /* fist compute displacement encoding */
515 if (sib_reg1 == -1) {
516 sib_reg1 = 5;
517 mod = 0x00;
518 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
519 mod = 0x00;
520 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
521 mod = 0x40;
522 } else {
523 mod = 0x80;
524 }
525 /* compute if sib byte needed */
526 reg1 = op->reg;
527 if (op->reg2 != -1)
528 reg1 = 4;
529 #ifdef I386_ASM_16
530 if (tcc_state->seg_size == 32) {
531 #endif
532 g(mod + (reg << 3) + reg1);
533 if (reg1 == 4) {
534 /* add sib byte */
535 reg2 = op->reg2;
536 if (reg2 == -1)
537 reg2 = 4; /* indicate no index */
538 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
539 }
540 #ifdef I386_ASM_16
541 } else if (tcc_state->seg_size == 16) {
542 /* edi = 7, esi = 6 --> di = 5, si = 4 */
543 if ((reg1 == 6) || (reg1 == 7)) {
544 reg1 -= 2;
545 /* ebx = 3 --> bx = 7 */
546 } else if (reg1 == 3) {
547 reg1 = 7;
548 /* o32 = 5 --> o16 = 6 */
549 } else if (reg1 == 5) {
550 reg1 = 6;
551 /* sib not valid in 16-bit mode */
552 } else if (reg1 == 4) {
553 reg2 = op->reg2;
554 /* bp + si + offset */
555 if ((sib_reg1 == 5) && (reg2 == 6)) {
556 reg1 = 2;
557 /* bp + di + offset */
558 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
559 reg1 = 3;
560 /* bx + si + offset */
561 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
562 reg1 = 0;
563 /* bx + di + offset */
564 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
565 reg1 = 1;
566 } else {
567 tcc_error("invalid effective address");
568 }
569 if (op->e.v == 0)
570 mod = 0;
571 } else {
572 tcc_error("invalid register");
573 }
574 g(mod + (reg << 3) + reg1);
575 }
576 #endif
577 /* add offset */
578 if (mod == 0x40) {
579 g(op->e.v);
580 } else if (mod == 0x80 || op->reg == -1) {
581 #ifdef I386_ASM_16
582 if (tcc_state->seg_size == 16)
583 gen_expr16(&op->e);
584 else if (tcc_state->seg_size == 32)
585 #endif
586 gen_expr32(&op->e);
587 }
588 }
589 }
590
591 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
592 {
593 const ASMInstr *pa;
594 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
595 int nb_ops, s;
596 Operand ops[MAX_OPERANDS], *pop;
597 int op_type[3]; /* decoded op type */
598 int alltypes; /* OR of all operand types */
599 int autosize;
600 #ifdef I386_ASM_16
601 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
602 #endif
603
604 /* force synthetic ';' after prefix instruction, so we can handle */
605 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
606 if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
607 unget_tok(';');
608
609 /* get operands */
610 pop = ops;
611 nb_ops = 0;
612 seg_prefix = 0;
613 alltypes = 0;
614 for(;;) {
615 if (tok == ';' || tok == TOK_LINEFEED)
616 break;
617 if (nb_ops >= MAX_OPERANDS) {
618 tcc_error("incorrect number of operands");
619 }
620 parse_operand(s1, pop);
621 if (tok == ':') {
622 if (pop->type != OP_SEG || seg_prefix)
623 tcc_error("incorrect prefix");
624 seg_prefix = segment_prefixes[pop->reg];
625 next();
626 parse_operand(s1, pop);
627 #ifndef I386_ASM_16
628 if (!(pop->type & OP_EA)) {
629 tcc_error("segment prefix must be followed by memory reference");
630 }
631 #endif
632 }
633 pop++;
634 nb_ops++;
635 if (tok != ',')
636 break;
637 next();
638 }
639
640 is_short_jmp = 0;
641 s = 0; /* avoid warning */
642
643 /* optimize matching by using a lookup table (no hashing is needed
644 !) */
645 for(pa = asm_instrs; pa->sym != 0; pa++) {
646 s = 0;
647 if (pa->instr_type & OPC_FARITH) {
648 v = opcode - pa->sym;
649 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
650 continue;
651 } else if (pa->instr_type & OPC_ARITH) {
652 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
653 continue;
654 s = (opcode - pa->sym) % NBWLX;
655 } else if (pa->instr_type & OPC_SHIFT) {
656 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
657 continue;
658 s = (opcode - pa->sym) % NBWLX;
659 } else if (pa->instr_type & OPC_TEST) {
660 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
661 continue;
662 } else if (pa->instr_type & OPC_B) {
663 #ifdef TCC_TARGET_X86_64
664 /* Some instructions don't have the full size but only
665 bwl form. insb e.g. */
666 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
667 && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
668 continue;
669 #endif
670 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
671 continue;
672 s = opcode - pa->sym;
673 } else if (pa->instr_type & OPC_WLX) {
674 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
675 continue;
676 s = opcode - pa->sym + 1;
677 } else {
678 if (pa->sym != opcode)
679 continue;
680 }
681 if (pa->nb_ops != nb_ops)
682 continue;
683 /* now decode and check each operand */
684 alltypes = 0;
685 for(i = 0; i < nb_ops; i++) {
686 int op1, op2;
687 op1 = pa->op_type[i];
688 op2 = op1 & 0x1f;
689 switch(op2) {
690 case OPT_IM:
691 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
692 break;
693 case OPT_REG:
694 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
695 break;
696 case OPT_REGW:
697 v = OP_REG16 | OP_REG32 | OP_REG64;
698 break;
699 case OPT_IMW:
700 v = OP_IM16 | OP_IM32 | OP_IM64;
701 break;
702 #ifdef TCC_TARGET_X86_64
703 case OPT_IMNO64:
704 v = OP_IM16 | OP_IM32;
705 break;
706 #endif
707 default:
708 v = 1 << op2;
709 break;
710 }
711 if (op1 & OPT_EA)
712 v |= OP_EA;
713 op_type[i] = v;
714 if ((ops[i].type & v) == 0)
715 goto next;
716 alltypes |= ops[i].type;
717 }
718 /* all is matching ! */
719 break;
720 next: ;
721 }
722 if (pa->sym == 0) {
723 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
724 int b;
725 b = op0_codes[opcode - TOK_ASM_first];
726 #ifdef I386_ASM_16
727 if (opcode == TOK_ASM_o32) {
728 if (s1->seg_size == 32)
729 tcc_error("incorrect prefix");
730 else
731 o32 = data32 = 1;
732 } else if (opcode == TOK_ASM_a32) {
733 if (s1->seg_size == 32)
734 tcc_error("incorrect prefix");
735 else
736 a32 = addr32 = 1;
737 }
738 #endif
739 if (b & 0xff00)
740 g(b >> 8);
741 g(b);
742 return;
743 } else if (opcode <= TOK_ASM_alllast) {
744 tcc_error("bad operand with opcode '%s'",
745 get_tok_str(opcode, NULL));
746 } else {
747 tcc_error("unknown opcode '%s'",
748 get_tok_str(opcode, NULL));
749 }
750 }
751 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
752 autosize = NBWLX-1;
753 #ifdef TCC_TARGET_X86_64
754 /* XXX the autosize should rather be zero, to not have to adjust this
755 all the time. */
756 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ)
757 autosize = NBWLX-2;
758 #endif
759 if (s == autosize) {
760 for(i = 0; s == autosize && i < nb_ops; i++) {
761 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
762 s = reg_to_size[ops[i].type & OP_REG];
763 }
764 if (s == autosize) {
765 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
766 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
767 s = 2;
768 else
769 tcc_error("cannot infer opcode suffix");
770 }
771 }
772
773 #ifdef I386_ASM_16
774 for(i = 0; i < nb_ops; i++) {
775 if (ops[i].type & OP_REG32) {
776 if (s1->seg_size == 16)
777 o32 = 1;
778 } else if (!(ops[i].type & OP_REG32)) {
779 if (s1->seg_size == 32)
780 o32 = 1;
781 }
782 }
783
784
785 if (s == 1 || (pa->instr_type & OPC_D16)) {
786 if (s1->seg_size == 32)
787 o32 = 1;
788 } else if (s == 2) {
789 if (s1->seg_size == 16) {
790 if (!(pa->instr_type & OPC_D16))
791 o32 = 1;
792 }
793 }
794
795 /* generate a16/a32 prefix if needed */
796 if ((a32 == 1) && (addr32 == 0))
797 g(0x67);
798 /* generate o16/o32 prefix if needed */
799 if ((o32 == 1) && (data32 == 0))
800 g(0x66);
801
802 addr32 = data32 = 0;
803 #else
804 #ifdef TCC_TARGET_X86_64
805 /* Generate addr32 prefix if needed */
806 for(i = 0; i < nb_ops; i++) {
807 if (ops[i].type & OP_EA32) {
808 g(0x67);
809 break;
810 }
811 }
812 #endif
813 /* generate data16 prefix if needed */
814 if (s == 1 || (pa->instr_type & OPC_D16))
815 g(0x66);
816 #ifdef TCC_TARGET_X86_64
817 if (s == 3 || (alltypes & OP_REG64)) {
818 /* generate REX prefix */
819 int default64 = 0;
820 for(i = 0; i < nb_ops; i++) {
821 if (op_type[i] == OP_REG64) {
822 /* If only 64bit regs are accepted in one operand
823 this is a default64 instruction without need for
824 REX prefixes. */
825 default64 = 1;
826 break;
827 }
828 }
829 /* XXX find better encoding for the default64 instructions. */
830 if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
831 && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
832 && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
833 && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
834 && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
835 && !default64)
836 g(0x48);
837 }
838 #endif
839 #endif
840
841 /* now generates the operation */
842 if (pa->instr_type & OPC_FWAIT)
843 g(0x9b);
844 if (seg_prefix)
845 g(seg_prefix);
846
847 v = pa->opcode;
848 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
849 /* kludge for imul $im, %reg */
850 nb_ops = 3;
851 ops[2] = ops[1];
852 op_type[2] = op_type[1];
853 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
854 v--; /* int $3 case */
855 nb_ops = 0;
856 } else if ((v == 0x06 || v == 0x07)) {
857 if (ops[0].reg >= 4) {
858 /* push/pop %fs or %gs */
859 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
860 } else {
861 v += ops[0].reg << 3;
862 }
863 nb_ops = 0;
864 } else if (v <= 0x05) {
865 /* arith case */
866 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
867 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
868 /* fpu arith case */
869 v += ((opcode - pa->sym) / 6) << 3;
870 }
871 if (pa->instr_type & OPC_REG) {
872 for(i = 0; i < nb_ops; i++) {
873 if (op_type[i] & (OP_REG | OP_ST)) {
874 v += ops[i].reg;
875 break;
876 }
877 }
878 /* mov $im, %reg case */
879 if (pa->opcode == 0xb0 && s >= 1)
880 v += 7;
881 }
882 if (pa->instr_type & OPC_B)
883 v += s >= 1;
884 if (pa->instr_type & OPC_TEST)
885 v += test_bits[opcode - pa->sym];
886 if (pa->instr_type & OPC_SHORTJMP) {
887 Sym *sym;
888 int jmp_disp;
889
890 /* see if we can really generate the jump with a byte offset */
891 sym = ops[0].e.sym;
892 if (!sym)
893 goto no_short_jump;
894 if (sym->r != cur_text_section->sh_num)
895 goto no_short_jump;
896 jmp_disp = ops[0].e.v + sym->jnext - ind - 2 - (v >= 0xff);
897 if (jmp_disp == (int8_t)jmp_disp) {
898 /* OK to generate jump */
899 is_short_jmp = 1;
900 ops[0].e.v = jmp_disp;
901 } else {
902 no_short_jump:
903 if (pa->instr_type & OPC_JMP) {
904 /* long jump will be allowed. need to modify the
905 opcode slightly */
906 if (v == 0xeb)
907 v = 0xe9;
908 else
909 v += 0x0f10;
910 } else {
911 tcc_error("invalid displacement");
912 }
913 }
914 }
915 op1 = v >> 8;
916 if (op1)
917 g(op1);
918 g(v);
919
920 /* search which operand will used for modrm */
921 modrm_index = 0;
922 if (pa->instr_type & OPC_SHIFT) {
923 reg = (opcode - pa->sym) / NBWLX;
924 if (reg == 6)
925 reg = 7;
926 } else if (pa->instr_type & OPC_ARITH) {
927 reg = (opcode - pa->sym) / NBWLX;
928 } else if (pa->instr_type & OPC_FARITH) {
929 reg = (opcode - pa->sym) / 6;
930 } else {
931 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
932 }
933 if (pa->instr_type & OPC_MODRM) {
934 /* first look for an ea operand */
935 for(i = 0;i < nb_ops; i++) {
936 if (op_type[i] & OP_EA)
937 goto modrm_found;
938 }
939 /* then if not found, a register or indirection (shift instructions) */
940 for(i = 0;i < nb_ops; i++) {
941 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
942 goto modrm_found;
943 }
944 #ifdef ASM_DEBUG
945 tcc_error("bad op table");
946 #endif
947 modrm_found:
948 modrm_index = i;
949 /* if a register is used in another operand then it is
950 used instead of group */
951 for(i = 0;i < nb_ops; i++) {
952 v = op_type[i];
953 if (i != modrm_index &&
954 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
955 reg = ops[i].reg;
956 break;
957 }
958 }
959
960 asm_modrm(reg, &ops[modrm_index]);
961 }
962
963 /* emit constants */
964 #ifndef TCC_TARGET_X86_64
965 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
966 /* ljmp or lcall kludge */
967 #ifdef I386_ASM_16
968 if (s1->seg_size == 16 && o32 == 0)
969 gen_expr16(&ops[1].e);
970 else
971 #endif
972 gen_expr32(&ops[1].e);
973 if (ops[0].e.sym)
974 tcc_error("cannot relocate");
975 gen_le16(ops[0].e.v);
976 return;
977 }
978 #endif
979 for(i = 0;i < nb_ops; i++) {
980 v = op_type[i];
981 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
982 /* if multiple sizes are given it means we must look
983 at the op size */
984 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
985 if (s == 0)
986 v = OP_IM8;
987 else if (s == 1)
988 v = OP_IM16;
989 else if (s == 2 || (v & OP_IM64) == 0)
990 v = OP_IM32;
991 else
992 v = OP_IM64;
993 }
994 if (v & (OP_IM8 | OP_IM8S)) {
995 if (ops[i].e.sym)
996 goto error_relocate;
997 g(ops[i].e.v);
998 } else if (v & OP_IM16) {
999 #ifdef I386_ASM_16
1000 if (s1->seg_size == 16)
1001 gen_expr16(&ops[i].e);
1002 else
1003 #endif
1004 if (ops[i].e.sym)
1005 error_relocate:
1006 tcc_error("cannot relocate");
1007 else
1008 gen_le16(ops[i].e.v);
1009 } else {
1010 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
1011 if (is_short_jmp)
1012 g(ops[i].e.v);
1013 #ifdef I386_ASM_16
1014 else if (s1->seg_size == 16)
1015 gen_disp16(&ops[i].e);
1016 #endif
1017 else
1018 gen_disp32(&ops[i].e);
1019 } else {
1020 #ifdef I386_ASM_16
1021 if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
1022 gen_expr16(&ops[i].e);
1023 else
1024 #endif
1025 #ifdef TCC_TARGET_X86_64
1026 if (v & OP_IM64)
1027 gen_expr64(&ops[i].e);
1028 else
1029 #endif
1030 gen_expr32(&ops[i].e);
1031 }
1032 }
1033 #ifdef I386_ASM_16
1034 } else if (v & (OP_REG16 | OP_REG32)) {
1035 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
1036 /* jmp $r */
1037 g(0xE0 + ops[i].reg);
1038 }
1039 #endif
1040 #ifdef TCC_TARGET_X86_64
1041 } else if (v & (OP_REG32 | OP_REG64)) {
1042 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
1043 /* jmp $r */
1044 g(0xE0 + ops[i].reg);
1045 }
1046 #endif
1047 }
1048 }
1049 #ifdef I386_ASM_16
1050 a32 = o32 = 0;
1051 #endif
1052 }
1053
1054 /* return the constraint priority (we allocate first the lowest
1055 numbered constraints) */
1056 static inline int constraint_priority(const char *str)
1057 {
1058 int priority, c, pr;
1059
1060 /* we take the lowest priority */
1061 priority = 0;
1062 for(;;) {
1063 c = *str;
1064 if (c == '\0')
1065 break;
1066 str++;
1067 switch(c) {
1068 case 'A':
1069 pr = 0;
1070 break;
1071 case 'a':
1072 case 'b':
1073 case 'c':
1074 case 'd':
1075 case 'S':
1076 case 'D':
1077 pr = 1;
1078 break;
1079 case 'q':
1080 pr = 2;
1081 break;
1082 case 'r':
1083 pr = 3;
1084 break;
1085 case 'N':
1086 case 'M':
1087 case 'I':
1088 case 'i':
1089 case 'm':
1090 case 'g':
1091 pr = 4;
1092 break;
1093 default:
1094 tcc_error("unknown constraint '%c'", c);
1095 pr = 0;
1096 }
1097 if (pr > priority)
1098 priority = pr;
1099 }
1100 return priority;
1101 }
1102
1103 static const char *skip_constraint_modifiers(const char *p)
1104 {
1105 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1106 p++;
1107 return p;
1108 }
1109
1110 #define REG_OUT_MASK 0x01
1111 #define REG_IN_MASK 0x02
1112
1113 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1114
1115 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1116 int nb_operands, int nb_outputs,
1117 const uint8_t *clobber_regs,
1118 int *pout_reg)
1119 {
1120 ASMOperand *op;
1121 int sorted_op[MAX_ASM_OPERANDS];
1122 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1123 const char *str;
1124 uint8_t regs_allocated[NB_ASM_REGS];
1125
1126 /* init fields */
1127 for(i=0;i<nb_operands;i++) {
1128 op = &operands[i];
1129 op->input_index = -1;
1130 op->ref_index = -1;
1131 op->reg = -1;
1132 op->is_memory = 0;
1133 op->is_rw = 0;
1134 }
1135 /* compute constraint priority and evaluate references to output
1136 constraints if input constraints */
1137 for(i=0;i<nb_operands;i++) {
1138 op = &operands[i];
1139 str = op->constraint;
1140 str = skip_constraint_modifiers(str);
1141 if (isnum(*str) || *str == '[') {
1142 /* this is a reference to another constraint */
1143 k = find_constraint(operands, nb_operands, str, NULL);
1144 if ((unsigned)k >= i || i < nb_outputs)
1145 tcc_error("invalid reference in constraint %d ('%s')",
1146 i, str);
1147 op->ref_index = k;
1148 if (operands[k].input_index >= 0)
1149 tcc_error("cannot reference twice the same operand");
1150 operands[k].input_index = i;
1151 op->priority = 5;
1152 } else {
1153 op->priority = constraint_priority(str);
1154 }
1155 }
1156
1157 /* sort operands according to their priority */
1158 for(i=0;i<nb_operands;i++)
1159 sorted_op[i] = i;
1160 for(i=0;i<nb_operands - 1;i++) {
1161 for(j=i+1;j<nb_operands;j++) {
1162 p1 = operands[sorted_op[i]].priority;
1163 p2 = operands[sorted_op[j]].priority;
1164 if (p2 < p1) {
1165 tmp = sorted_op[i];
1166 sorted_op[i] = sorted_op[j];
1167 sorted_op[j] = tmp;
1168 }
1169 }
1170 }
1171
1172 for(i = 0;i < NB_ASM_REGS; i++) {
1173 if (clobber_regs[i])
1174 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1175 else
1176 regs_allocated[i] = 0;
1177 }
1178 /* esp cannot be used */
1179 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1180 /* ebp cannot be used yet */
1181 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1182
1183 /* allocate registers and generate corresponding asm moves */
1184 for(i=0;i<nb_operands;i++) {
1185 j = sorted_op[i];
1186 op = &operands[j];
1187 str = op->constraint;
1188 /* no need to allocate references */
1189 if (op->ref_index >= 0)
1190 continue;
1191 /* select if register is used for output, input or both */
1192 if (op->input_index >= 0) {
1193 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1194 } else if (j < nb_outputs) {
1195 reg_mask = REG_OUT_MASK;
1196 } else {
1197 reg_mask = REG_IN_MASK;
1198 }
1199 try_next:
1200 c = *str++;
1201 switch(c) {
1202 case '=':
1203 goto try_next;
1204 case '+':
1205 op->is_rw = 1;
1206 /* FALL THRU */
1207 case '&':
1208 if (j >= nb_outputs)
1209 tcc_error("'%c' modifier can only be applied to outputs", c);
1210 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1211 goto try_next;
1212 case 'A':
1213 /* allocate both eax and edx */
1214 if (is_reg_allocated(TREG_XAX) ||
1215 is_reg_allocated(TREG_XDX))
1216 goto try_next;
1217 op->is_llong = 1;
1218 op->reg = TREG_XAX;
1219 regs_allocated[TREG_XAX] |= reg_mask;
1220 regs_allocated[TREG_XDX] |= reg_mask;
1221 break;
1222 case 'a':
1223 reg = TREG_XAX;
1224 goto alloc_reg;
1225 case 'b':
1226 reg = 3;
1227 goto alloc_reg;
1228 case 'c':
1229 reg = TREG_XCX;
1230 goto alloc_reg;
1231 case 'd':
1232 reg = TREG_XDX;
1233 goto alloc_reg;
1234 case 'S':
1235 reg = 6;
1236 goto alloc_reg;
1237 case 'D':
1238 reg = 7;
1239 alloc_reg:
1240 if (is_reg_allocated(reg))
1241 goto try_next;
1242 goto reg_found;
1243 case 'q':
1244 /* eax, ebx, ecx or edx */
1245 for(reg = 0; reg < 4; reg++) {
1246 if (!is_reg_allocated(reg))
1247 goto reg_found;
1248 }
1249 goto try_next;
1250 case 'r':
1251 /* any general register */
1252 for(reg = 0; reg < 8; reg++) {
1253 if (!is_reg_allocated(reg))
1254 goto reg_found;
1255 }
1256 goto try_next;
1257 reg_found:
1258 /* now we can reload in the register */
1259 op->is_llong = 0;
1260 op->reg = reg;
1261 regs_allocated[reg] |= reg_mask;
1262 break;
1263 case 'i':
1264 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1265 goto try_next;
1266 break;
1267 case 'I':
1268 case 'N':
1269 case 'M':
1270 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1271 goto try_next;
1272 break;
1273 case 'm':
1274 case 'g':
1275 /* nothing special to do because the operand is already in
1276 memory, except if the pointer itself is stored in a
1277 memory variable (VT_LLOCAL case) */
1278 /* XXX: fix constant case */
1279 /* if it is a reference to a memory zone, it must lie
1280 in a register, so we reserve the register in the
1281 input registers and a load will be generated
1282 later */
1283 if (j < nb_outputs || c == 'm') {
1284 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1285 /* any general register */
1286 for(reg = 0; reg < 8; reg++) {
1287 if (!(regs_allocated[reg] & REG_IN_MASK))
1288 goto reg_found1;
1289 }
1290 goto try_next;
1291 reg_found1:
1292 /* now we can reload in the register */
1293 regs_allocated[reg] |= REG_IN_MASK;
1294 op->reg = reg;
1295 op->is_memory = 1;
1296 }
1297 }
1298 break;
1299 default:
1300 tcc_error("asm constraint %d ('%s') could not be satisfied",
1301 j, op->constraint);
1302 break;
1303 }
1304 /* if a reference is present for that operand, we assign it too */
1305 if (op->input_index >= 0) {
1306 operands[op->input_index].reg = op->reg;
1307 operands[op->input_index].is_llong = op->is_llong;
1308 }
1309 }
1310
1311 /* compute out_reg. It is used to store outputs registers to memory
1312 locations references by pointers (VT_LLOCAL case) */
1313 *pout_reg = -1;
1314 for(i=0;i<nb_operands;i++) {
1315 op = &operands[i];
1316 if (op->reg >= 0 &&
1317 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1318 !op->is_memory) {
1319 for(reg = 0; reg < 8; reg++) {
1320 if (!(regs_allocated[reg] & REG_OUT_MASK))
1321 goto reg_found2;
1322 }
1323 tcc_error("could not find free output register for reloading");
1324 reg_found2:
1325 *pout_reg = reg;
1326 break;
1327 }
1328 }
1329
1330 /* print sorted constraints */
1331 #ifdef ASM_DEBUG
1332 for(i=0;i<nb_operands;i++) {
1333 j = sorted_op[i];
1334 op = &operands[j];
1335 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1336 j,
1337 op->id ? get_tok_str(op->id, NULL) : "",
1338 op->constraint,
1339 op->vt->r,
1340 op->reg);
1341 }
1342 if (*pout_reg >= 0)
1343 printf("out_reg=%d\n", *pout_reg);
1344 #endif
1345 }
1346
1347 ST_FUNC void subst_asm_operand(CString *add_str,
1348 SValue *sv, int modifier)
1349 {
1350 int r, reg, size, val;
1351 char buf[64];
1352
1353 r = sv->r;
1354 if ((r & VT_VALMASK) == VT_CONST) {
1355 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1356 cstr_ccat(add_str, '$');
1357 if (r & VT_SYM) {
1358 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL), -1);
1359 if ((uint32_t)sv->c.i != 0) {
1360 cstr_ccat(add_str, '+');
1361 } else {
1362 return;
1363 }
1364 }
1365 val = sv->c.i;
1366 if (modifier == 'n')
1367 val = -val;
1368 snprintf(buf, sizeof(buf), "%d", (int)sv->c.i);
1369 cstr_cat(add_str, buf, -1);
1370 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1371 snprintf(buf, sizeof(buf), "%d(%%ebp)", (int)sv->c.i);
1372 cstr_cat(add_str, buf, -1);
1373 } else if (r & VT_LVAL) {
1374 reg = r & VT_VALMASK;
1375 if (reg >= VT_CONST)
1376 tcc_error("internal compiler error");
1377 snprintf(buf, sizeof(buf), "(%%%s)",
1378 get_tok_str(TOK_ASM_eax + reg, NULL));
1379 cstr_cat(add_str, buf, -1);
1380 } else {
1381 /* register case */
1382 reg = r & VT_VALMASK;
1383 if (reg >= VT_CONST)
1384 tcc_error("internal compiler error");
1385
1386 /* choose register operand size */
1387 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1388 size = 1;
1389 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1390 size = 2;
1391 #ifdef TCC_TARGET_X86_64
1392 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1393 size = 8;
1394 #endif
1395 else
1396 size = 4;
1397 if (size == 1 && reg >= 4)
1398 size = 4;
1399
1400 if (modifier == 'b') {
1401 if (reg >= 4)
1402 tcc_error("cannot use byte register");
1403 size = 1;
1404 } else if (modifier == 'h') {
1405 if (reg >= 4)
1406 tcc_error("cannot use byte register");
1407 size = -1;
1408 } else if (modifier == 'w') {
1409 size = 2;
1410 #ifdef TCC_TARGET_X86_64
1411 } else if (modifier == 'q') {
1412 size = 8;
1413 #endif
1414 }
1415
1416 switch(size) {
1417 case -1:
1418 reg = TOK_ASM_ah + reg;
1419 break;
1420 case 1:
1421 reg = TOK_ASM_al + reg;
1422 break;
1423 case 2:
1424 reg = TOK_ASM_ax + reg;
1425 break;
1426 default:
1427 reg = TOK_ASM_eax + reg;
1428 break;
1429 #ifdef TCC_TARGET_X86_64
1430 case 8:
1431 reg = TOK_ASM_rax + reg;
1432 break;
1433 #endif
1434 }
1435 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1436 cstr_cat(add_str, buf, -1);
1437 }
1438 }
1439
1440 /* generate prolog and epilog code for asm statement */
1441 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1442 int nb_outputs, int is_output,
1443 uint8_t *clobber_regs,
1444 int out_reg)
1445 {
1446 uint8_t regs_allocated[NB_ASM_REGS];
1447 ASMOperand *op;
1448 int i, reg;
1449 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1450
1451 /* mark all used registers */
1452 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1453 for(i = 0; i < nb_operands;i++) {
1454 op = &operands[i];
1455 if (op->reg >= 0)
1456 regs_allocated[op->reg] = 1;
1457 }
1458 if (!is_output) {
1459 /* generate reg save code */
1460 for(i = 0; i < NB_SAVED_REGS; i++) {
1461 reg = reg_saved[i];
1462 if (regs_allocated[reg]) {
1463 #ifdef I386_ASM_16
1464 if (tcc_state->seg_size == 16)
1465 g(0x66);
1466 #endif
1467 g(0x50 + reg);
1468 }
1469 }
1470
1471 /* generate load code */
1472 for(i = 0; i < nb_operands; i++) {
1473 op = &operands[i];
1474 if (op->reg >= 0) {
1475 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1476 op->is_memory) {
1477 /* memory reference case (for both input and
1478 output cases) */
1479 SValue sv;
1480 sv = *op->vt;
1481 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1482 load(op->reg, &sv);
1483 } else if (i >= nb_outputs || op->is_rw) {
1484 /* load value in register */
1485 load(op->reg, op->vt);
1486 if (op->is_llong) {
1487 SValue sv;
1488 sv = *op->vt;
1489 sv.c.i += 4;
1490 load(TREG_XDX, &sv);
1491 }
1492 }
1493 }
1494 }
1495 } else {
1496 /* generate save code */
1497 for(i = 0 ; i < nb_outputs; i++) {
1498 op = &operands[i];
1499 if (op->reg >= 0) {
1500 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1501 if (!op->is_memory) {
1502 SValue sv;
1503 sv = *op->vt;
1504 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1505 load(out_reg, &sv);
1506
1507 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1508 store(op->reg, &sv);
1509 }
1510 } else {
1511 store(op->reg, op->vt);
1512 if (op->is_llong) {
1513 SValue sv;
1514 sv = *op->vt;
1515 sv.c.i += 4;
1516 store(TREG_XDX, &sv);
1517 }
1518 }
1519 }
1520 }
1521 /* generate reg restore code */
1522 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1523 reg = reg_saved[i];
1524 if (regs_allocated[reg]) {
1525 #ifdef I386_ASM_16
1526 if (tcc_state->seg_size == 16)
1527 g(0x66);
1528 #endif
1529 g(0x58 + reg);
1530 }
1531 }
1532 }
1533 }
1534
1535 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1536 {
1537 int reg;
1538 TokenSym *ts;
1539
1540 if (!strcmp(str, "memory") ||
1541 !strcmp(str, "cc"))
1542 return;
1543 ts = tok_alloc(str, strlen(str));
1544 reg = ts->tok;
1545 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1546 reg -= TOK_ASM_eax;
1547 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1548 reg -= TOK_ASM_ax;
1549 #ifdef TCC_TARGET_X86_64
1550 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1551 reg -= TOK_ASM_rax;
1552 #endif
1553 } else {
1554 tcc_error("invalid clobber register '%s'", str);
1555 }
1556 clobber_regs[reg] = 1;
1557 }
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