1 /*************************************************************/
3 * RISCV64 assembler for TCC
7 #ifdef TARGET_DEFS_ONLY
10 /* 32 general purpose + 32 floating point registers */
11 #define NB_ASM_REGS 64
13 ST_FUNC
void g(int c
);
14 ST_FUNC
void gen_le16(int c
);
15 ST_FUNC
void gen_le32(int c
);
17 /*************************************************************/
19 /*************************************************************/
28 // Registers go from 0 to 31. We use next bit to choose general/float
29 #define REG_FLOAT_MASK 0x20
30 #define REG_IS_FLOAT(register_index) ((register_index) & REG_FLOAT_MASK)
31 #define REG_VALUE(register_index) ((register_index) & (REG_FLOAT_MASK-1))
32 #define C_ENCODE_RS1(register_index) (REG_VALUE(register_index) << 7)
33 #define C_ENCODE_RS2(register_index) (REG_VALUE(register_index) << 2)
34 #define ENCODE_RD(register_index) (REG_VALUE(register_index) << 7)
35 #define ENCODE_RS1(register_index) (REG_VALUE(register_index) << 15)
36 #define ENCODE_RS2(register_index) (REG_VALUE(register_index) << 20)
37 #define NTH_BIT(b, n) ((b >> n) & 1)
38 #define OP_IM12S (1 << OPT_IM12S)
39 #define OP_IM32 (1 << OPT_IM32)
40 #define OP_REG (1 << OPT_REG)
42 typedef struct Operand
{
51 static void asm_binary_opcode(TCCState
* s1
, int token
);
52 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
);
53 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
, int nb_operands
, int nb_outputs
, const uint8_t *clobber_regs
, int *pout_reg
);
54 static void asm_emit_a(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*rd1
, int aq
, int rl
);
55 static void asm_emit_b(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
);
56 static void asm_emit_i(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*rs2
);
57 static void asm_emit_j(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs2
);
58 static void asm_emit_opcode(uint32_t opcode
);
59 static void asm_emit_r(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*rs2
);
60 static void asm_emit_s(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
);
61 static void asm_emit_u(int token
, uint32_t opcode
, const Operand
*rd
, const Operand
*rs2
);
62 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
, int nb_outputs
, int is_output
, uint8_t *clobber_regs
, int out_reg
);
63 static void asm_nullary_opcode(TCCState
*s1
, int token
);
64 ST_FUNC
void asm_opcode(TCCState
*s1
, int token
);
65 static int asm_parse_csrvar(int t
);
66 ST_FUNC
int asm_parse_regvar(int t
);
67 static void asm_ternary_opcode(TCCState
*s1
, int token
);
68 static void asm_unary_opcode(TCCState
*s1
, int token
);
69 static void asm_branch_opcode(TCCState
*s1
, int token
, int argc
);
70 ST_FUNC
void gen_expr32(ExprValue
*pe
);
71 static void parse_operand(TCCState
*s1
, Operand
*op
);
72 static void parse_branch_offset_operand(TCCState
*s1
, Operand
*op
);
73 static void parse_operands(TCCState
*s1
, Operand
*ops
, int count
);
74 static void parse_mem_access_operands(TCCState
*s1
, Operand
* ops
);
75 ST_FUNC
void subst_asm_operand(CString
*add_str
, SValue
*sv
, int modifier
);
77 static void asm_emit_ca(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
);
78 static void asm_emit_cb(int token
, uint16_t opcode
, const Operand
*rs1
, const Operand
*imm
);
79 static void asm_emit_ci(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
);
80 static void asm_emit_ciw(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
);
81 static void asm_emit_cj(int token
, uint16_t opcode
, const Operand
*imm
);
82 static void asm_emit_cl(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*imm
);
83 static void asm_emit_cr(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
);
84 static void asm_emit_cs(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*rs1
, const Operand
*imm
);
85 static void asm_emit_css(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*imm
);
87 /* XXX: make it faster ? */
94 if (ind1
> cur_text_section
->data_allocated
)
95 section_realloc(cur_text_section
, ind1
);
96 cur_text_section
->data
[ind
] = c
;
100 ST_FUNC
void gen_le16 (int i
)
106 ST_FUNC
void gen_le32 (int i
)
112 if (ind1
> cur_text_section
->data_allocated
)
113 section_realloc(cur_text_section
, ind1
);
114 cur_text_section
->data
[ind
++] = i
& 0xFF;
115 cur_text_section
->data
[ind
++] = (i
>> 8) & 0xFF;
116 cur_text_section
->data
[ind
++] = (i
>> 16) & 0xFF;
117 cur_text_section
->data
[ind
++] = (i
>> 24) & 0xFF;
120 ST_FUNC
void gen_expr32(ExprValue
*pe
)
125 static void asm_emit_opcode(uint32_t opcode
) {
129 static void asm_nullary_opcode(TCCState
*s1
, int token
)
131 static const Operand nil
= {.type
= OP_REG
};
132 static const Operand zimm
= {.type
= OP_IM12S
};
137 case TOK_ASM_fence_i
: // I
138 asm_emit_opcode((0x3 << 2) | 3| (1 << 12));
143 case TOK_ASM_ecall
: // I (pseudo)
144 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12));
146 case TOK_ASM_ebreak
: // I (pseudo)
147 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20));
153 asm_emit_i(token
, (4 << 2) | 3, &nil
, &nil
, &zimm
);
157 asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20));
160 /* Pseudoinstructions */
162 /* jalr zero, x1, 0 */
163 asm_emit_opcode( 0x67 | (0 << 12) | ENCODE_RS1(1) );
167 case TOK_ASM_c_ebreak
:
168 asm_emit_cr(token
, 2 | (9 << 12), &nil
, &nil
);
171 asm_emit_ci(token
, 1, &nil
, &zimm
);
175 expect("nullary instruction");
179 /* Parse a text containing operand and store the result in OP */
180 static void parse_operand(TCCState
*s1
, Operand
*op
)
188 if ((reg
= asm_parse_regvar(tok
)) != -1) {
189 next(); // skip register name
191 op
->reg
= (uint8_t) reg
;
193 } else if (tok
== '$') {
195 next(); // skip '#' or '$'
196 } else if ((e
.v
= asm_parse_csrvar(tok
)) != -1) {
203 /* compare against unsigned 12-bit maximum */
205 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
207 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
208 label
.type
.t
= VT_VOID
| VT_STATIC
;
210 /* use the medium PIC model: GOT, auipc, lw */
211 if (op
->e
.sym
->type
.t
& VT_STATIC
)
212 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_PCREL_HI20
, 0);
214 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_GOT_HI20
, 0);
215 put_extern_sym(&label
, cur_text_section
, ind
, 0);
216 greloca(cur_text_section
, &label
, ind
+4, R_RISCV_PCREL_LO12_I
, 0);
225 static void parse_branch_offset_operand(TCCState
*s1
, Operand
*op
){
231 /* compare against unsigned 12-bit maximum */
233 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
235 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
236 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_BRANCH
, 0);
238 /* XXX: Implement far branches */
247 static void parse_jump_offset_operand(TCCState
*s1
, Operand
*op
){
253 /* compare against unsigned 12-bit maximum */
255 if ((int) op
->e
.v
>= -0x1000 && (int) op
->e
.v
< 0x1000)
257 } else if (op
->e
.sym
->type
.t
& (VT_EXTERN
| VT_STATIC
)) {
258 greloca(cur_text_section
, op
->e
.sym
, ind
, R_RISCV_JAL
, 0);
266 static void parse_operands(TCCState
*s1
, Operand
* ops
, int count
){
268 for (i
= 0; i
< count
; i
++) {
275 parse_operand(s1
, &ops
[i
]);
279 /* parse `X, imm(Y)` to {X, Y, imm} operands */
280 static void parse_mem_access_operands(TCCState
*s1
, Operand
* ops
){
281 static const Operand zimm
= {.type
= OP_IM12S
};
285 parse_operand(s1
, &ops
[0]);
294 parse_operand(s1
, &ops
[1]);
295 if ( tok
== ')') next(); else expect("')'");
298 parse_operand(s1
, &ops
[2]);
300 /* `X, imm(Y)` case*/
302 parse_operand(s1
, &ops
[1]);
303 if ( tok
== ')') next(); else expect("')'");
306 /* we parsed Y thinking it was imm, swap and default imm to zero */
315 /* This is special: First operand is optional */
316 static void asm_jal_opcode(TCCState
*s1
, int token
){
317 static const Operand ra
= {.type
= OP_REG
, .reg
= 1};
318 static const Operand zero
= {.type
= OP_REG
};
321 if (token
== TOK_ASM_j
){
322 ops
[0] = zero
; // j offset
323 } else if (asm_parse_regvar(tok
) == -1) {
324 ops
[0] = ra
; // jal offset
327 parse_operand(s1
, &ops
[0]);
328 if ( tok
== ',') next(); else expect("','");
330 parse_jump_offset_operand(s1
, &ops
[1]);
331 asm_emit_j(token
, 0x6f, &ops
[0], &ops
[1]);
334 /* This is special: It can be a pseudointruction or a instruction */
335 static void asm_jalr_opcode(TCCState
*s1
, int token
){
336 static const Operand zimm
= {.type
= OP_IM12S
};
337 static const Operand ra
= {.type
= OP_REG
, .reg
= 1};
341 parse_operand(s1
, &ops
[0]);
345 /* no more operands, it's the pseudoinstruction:
350 asm_emit_i(token
, 0x67 | (0 << 12), &ra
, &ops
[0], &zimm
);
357 parse_operand(s1
, &ops
[1]);
358 if ( tok
== ')') next(); else expect("')'");
361 parse_operand(s1
, &ops
[2]);
363 /* `X, imm(Y)` case*/
365 parse_operand(s1
, &ops
[1]);
366 if ( tok
== ')') next(); else expect("')'");
369 /* we parsed Y thinking it was imm, swap and default imm to zero */
376 /* jalr(RD, RS1, IMM); I-format */
377 asm_emit_i(token
, 0x67 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
381 static void asm_unary_opcode(TCCState
*s1
, int token
)
383 uint32_t opcode
= (0x1C << 2) | 3 | (2 << 12);
385 static const Operand zero
= {.type
= OP_REG
};
386 static const Operand zimm
= {.type
= OP_IM12S
};
388 parse_operands(s1
, &op
, 1);
389 /* Note: Those all map to CSR--so they are pseudo-instructions. */
390 opcode
|= ENCODE_RD(op
.reg
);
393 /* pseudoinstructions */
394 case TOK_ASM_rdcycle
:
395 asm_emit_opcode(opcode
| (0xC00 << 20));
397 case TOK_ASM_rdcycleh
:
398 asm_emit_opcode(opcode
| (0xC80 << 20));
401 asm_emit_opcode(opcode
| (0xC01 << 20) | ENCODE_RD(op
.reg
));
403 case TOK_ASM_rdtimeh
:
404 asm_emit_opcode(opcode
| (0xC81 << 20) | ENCODE_RD(op
.reg
));
406 case TOK_ASM_rdinstret
:
407 asm_emit_opcode(opcode
| (0xC02 << 20) | ENCODE_RD(op
.reg
));
409 case TOK_ASM_rdinstreth
:
410 asm_emit_opcode(opcode
| (0xC82 << 20) | ENCODE_RD(op
.reg
));
414 /* jalr zero, 0(rs)*/
415 asm_emit_i(token
, 0x67 | (0 << 12), &zero
, &op
, &zimm
);
419 greloca(cur_text_section
, op
.e
.sym
, ind
, R_RISCV_CALL
, 0);
420 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(1));
421 /* jalr zero, 0(ra) */
422 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(1));
426 greloca(cur_text_section
, op
.e
.sym
, ind
, R_RISCV_CALL
, 0);
427 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(6));
428 /* jalr zero, 0(x6) */
429 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(6));
434 asm_emit_cj(token
, 1 | (5 << 13), &op
);
436 case TOK_ASM_c_jal
: /* RV32C-only */
437 asm_emit_cj(token
, 1 | (1 << 13), &op
);
440 asm_emit_cr(token
, 2 | (9 << 12), &op
, &zero
);
443 asm_emit_cr(token
, 2 | (8 << 12), &op
, &zero
);
446 expect("unary instruction");
450 static void asm_emit_u(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs2
)
452 if (rd
->type
!= OP_REG
) {
453 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
456 if (rs2
->type
!= OP_IM12S
&& rs2
->type
!= OP_IM32
) {
457 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token
, NULL
));
459 } else if (rs2
->e
.v
>= 0x100000) {
460 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token
, NULL
));
463 /* U-type instruction:
467 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | (rs2
->e
.v
<< 12));
470 static int parse_fence_operand(){
472 if ( tok
== TOK_ASM_or
){
473 // we are in a fence instruction, parse as output read
474 t
= TOK_ASM_or_fence
;
477 return t
- (TOK_ASM_w_fence
- 1);
480 static void asm_fence_opcode(TCCState
*s1
, int token
){
481 // `fence` is both an instruction and a pseudoinstruction:
482 // `fence` expands to `fence iorw, iorw`
483 int succ
= 0xF, pred
= 0xF;
484 if (tok
!= TOK_LINEFEED
&& tok
!= ';' && tok
!= CH_EOF
){
485 pred
= parse_fence_operand();
486 if ( pred
> 0xF || pred
< 0) {
487 tcc_error("'%s': Expected first operand that is a valid predecessor operand", get_tok_str(token
, NULL
));
489 if ( tok
== ',') next(); else expect("','");
490 succ
= parse_fence_operand();
491 if ( succ
> 0xF || succ
< 0) {
492 tcc_error("'%s': Expected second operand that is a valid successor operand", get_tok_str(token
, NULL
));
495 asm_emit_opcode((0x3 << 2) | 3 | (0 << 12) | succ
<<20 | pred
<<24);
498 static void asm_binary_opcode(TCCState
* s1
, int token
)
500 static const Operand zero
= {.type
= OP_REG
, .reg
= 0};
501 Operand imm
= {.type
= OP_IM12S
, .e
= {.v
= 0}};
506 parse_operands(s1
, &ops
[0], 2);
509 asm_emit_u(token
, (0xD << 2) | 3, &ops
[0], &ops
[1]);
512 asm_emit_u(token
, (0x05 << 2) | 3, &ops
[0], &ops
[1]);
517 asm_emit_cr(token
, 2 | (9 << 12), ops
, ops
+ 1);
520 asm_emit_cr(token
, 2 | (8 << 12), ops
, ops
+ 1);
523 case TOK_ASM_c_addi16sp
:
524 asm_emit_ci(token
, 1 | (3 << 13), ops
, ops
+ 1);
527 asm_emit_ci(token
, 1, ops
, ops
+ 1);
529 case TOK_ASM_c_addiw
:
530 asm_emit_ci(token
, 1 | (1 << 13), ops
, ops
+ 1);
532 case TOK_ASM_c_fldsp
:
533 asm_emit_ci(token
, 2 | (1 << 13), ops
, ops
+ 1);
535 case TOK_ASM_c_flwsp
: /* RV32FC-only */
536 asm_emit_ci(token
, 2 | (3 << 13), ops
, ops
+ 1);
539 asm_emit_ci(token
, 2 | (3 << 13), ops
, ops
+ 1);
542 asm_emit_ci(token
, 1 | (2 << 13), ops
, ops
+ 1);
545 asm_emit_ci(token
, 1 | (3 << 13), ops
, ops
+ 1);
548 asm_emit_ci(token
, 2 | (2 << 13), ops
, ops
+ 1);
551 asm_emit_ci(token
, 2, ops
, ops
+ 1);
554 case TOK_ASM_c_addi4spn
:
555 asm_emit_ciw(token
, 0, ops
, ops
+ 1);
558 #define CA (1 | (3 << 10) | (4 << 13))
560 asm_emit_ca(token
, CA
| (1 << 5) | (1 << 12), ops
, ops
+ 1);
563 asm_emit_ca(token
, CA
| (3 << 5), ops
, ops
+ 1);
566 asm_emit_ca(token
, CA
| (2 << 5), ops
, ops
+ 1);
569 asm_emit_ca(token
, CA
, ops
, ops
+ 1);
572 asm_emit_ca(token
, CA
| (1 << 12), ops
, ops
+ 1);
575 asm_emit_ca(token
, CA
| (1 << 5), ops
, ops
+ 1);
580 asm_emit_cb(token
, 1 | (2 << 10) | (4 << 13), ops
, ops
+ 1);
583 asm_emit_cb(token
, 1 | (6 << 13), ops
, ops
+ 1);
586 asm_emit_cb(token
, 1 | (7 << 13), ops
, ops
+ 1);
589 asm_emit_cb(token
, 1 | (1 << 10) | (4 << 13), ops
, ops
+ 1);
592 asm_emit_cb(token
, 1 | (4 << 13), ops
, ops
+ 1);
596 asm_emit_css(token
, 2 | (7 << 13), ops
, ops
+ 1);
599 asm_emit_css(token
, 2 | (6 << 13), ops
, ops
+ 1);
601 case TOK_ASM_c_fswsp
: /* RV32FC-only */
602 asm_emit_css(token
, 2 | (7 << 13), ops
, ops
+ 1);
604 case TOK_ASM_c_fsdsp
:
605 asm_emit_css(token
, 2 | (5 << 13), ops
, ops
+ 1);
608 /* pseudoinstructions */
612 asm_emit_u(token
, 3 | (5 << 2), ops
, ops
+ 1);
614 asm_emit_i(token
, 3 | (2 << 12), ops
, ops
, ops
+ 1);
618 asm_emit_u(token
, 3 | (5 << 2), ops
, ops
+ 1);
620 asm_emit_i(token
, 3 | (4 << 2), ops
, ops
, ops
+ 1);
623 if(ops
[1].type
!= OP_IM32
&& ops
[1].type
!= OP_IM12S
){
624 tcc_error("'%s': Expected first source operand that is an immediate value between 0 and 0xFFFFFFFFFFFFFFFF", get_tok_str(token
, NULL
));
627 hi
= (int64_t)ops
[1].e
.v
>> 32;
631 imm
.e
.v
= ((hi
+ 0x800) & 0xfffff000) >> 12;
632 /* lui rd, HI_20(HI_32(imm)) */
633 asm_emit_u(token
, (0xD << 2) | 3, &ops
[0], &imm
);
634 /* addi rd, rd, LO_12(HI_32(imm)) */
635 imm
.e
.v
= (int32_t)hi
<<20>>20;
636 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
637 /* slli rd, rd, 12 */
639 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
640 /* addi rd, rd, HI_12(LO_32(imm)) */
641 imm
.e
.v
= (lo
+ (1<<19)) >> 20;
642 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
643 /* slli rd, rd, 12 */
645 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
646 /* addi rd, rd, HI_12(LO_20(LO_32imm)) */
649 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
652 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[0], &imm
);
653 /* addi rd, rd, LO_8(LO_20(LO_32imm)) */
655 imm
.e
.v
= lo
<< 20 >> 20;
656 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[0], &imm
);
660 asm_emit_i(token
, 3 | (4 << 2), &ops
[0], &ops
[1], &imm
);
663 /* xori rd, rs, -1 */
665 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &imm
);
670 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &zero
, &imm
);
675 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &zero
, &imm
);
679 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(5));
680 greloca(cur_text_section
, ops
->e
.sym
, ind
, R_RISCV_CALL
, 0);
681 /* jalr zero, 0(x5) */
682 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(5));
685 /* sltiu rd, rs, 1 */
687 asm_emit_i(token
, (0x4 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &imm
);
690 /* sltu rd, zero, rs */
692 asm_emit_r(token
, (0xC << 2) | 3 | (3 << 12), &ops
[0], &zero
, &ops
[1]);
695 /* slt rd, rs, zero */
696 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &zero
);
699 /* slt rd, zero, rs */
700 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &zero
, &ops
[1]);
704 expect("binary instruction");
708 /* caller: Add funct3, funct7 into opcode */
709 static void asm_emit_r(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs1
, const Operand
* rs2
)
711 if (rd
->type
!= OP_REG
) {
712 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
715 if (rs1
->type
!= OP_REG
) {
716 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
719 if (rs2
->type
!= OP_REG
) {
720 tcc_error("'%s': Expected second source operand that is a register or immediate", get_tok_str(token
, NULL
));
723 /* R-type instruction:
730 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
));
733 /* caller: Add funct3 into opcode */
734 static void asm_emit_i(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs1
, const Operand
* rs2
)
736 if (rd
->type
!= OP_REG
) {
737 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
740 if (rs1
->type
!= OP_REG
) {
741 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
744 if (rs2
->type
!= OP_IM12S
) {
745 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
748 /* I-type instruction:
755 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | ENCODE_RS1(rs1
->reg
) | (rs2
->e
.v
<< 20));
758 static void asm_emit_j(int token
, uint32_t opcode
, const Operand
* rd
, const Operand
* rs2
)
762 if (rd
->type
!= OP_REG
) {
763 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
766 if (rs2
->type
!= OP_IM12S
&& rs2
->type
!= OP_IM32
) {
767 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token
, NULL
));
773 /* even offsets in a +- 1 MiB range */
774 if ((int)imm
> (1 << 20) -1 || (int)imm
<= -1 * ((1 << 20) -1)) {
775 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0x1fffff", get_tok_str(token
, NULL
));
780 tcc_error("'%s': Expected second source operand that is an even immediate value", get_tok_str(token
, NULL
));
783 /* J-type instruction:
790 gen_le32(opcode
| ENCODE_RD(rd
->reg
) | (((imm
>> 20) & 1) << 31) | (((imm
>> 1) & 0x3ff) << 21) | (((imm
>> 11) & 1) << 20) | (((imm
>> 12) & 0xff) << 12));
793 static void asm_mem_access_opcode(TCCState
*s1
, int token
)
797 parse_mem_access_operands(s1
, &ops
[0]);
799 /* Pseudoinstruction: inst reg, label
803 * And with the proper relocation to label
805 if (ops
[1].type
== OP_IM32
&& ops
[1].e
.sym
&& ops
[1].e
.sym
->type
.t
& VT_STATIC
){
807 /* set the offset to zero */
808 ops
[2].type
= OP_IM12S
;
811 asm_emit_u(token
, (0x05 << 2) | 3, &ops
[0], &ops
[2]);
815 // l{b|h|w|d}[u] rd, imm(rs1); I-format
817 asm_emit_i(token
, (0x0 << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
820 asm_emit_i(token
, (0x0 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
823 asm_emit_i(token
, (0x0 << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
826 asm_emit_i(token
, (0x0 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
829 asm_emit_i(token
, (0x0 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
832 asm_emit_i(token
, (0x0 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
835 asm_emit_i(token
, (0x0 << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
838 // s{b|h|w|d} rs2, imm(rs1); S-format (with rsX swapped)
840 asm_emit_s(token
, (0x8 << 2) | 3 | (0 << 12), &ops
[1], &ops
[0], &ops
[2]);
843 asm_emit_s(token
, (0x8 << 2) | 3 | (1 << 12), &ops
[1], &ops
[0], &ops
[2]);
846 asm_emit_s(token
, (0x8 << 2) | 3 | (2 << 12), &ops
[1], &ops
[0], &ops
[2]);
849 asm_emit_s(token
, (0x8 << 2) | 3 | (3 << 12), &ops
[1], &ops
[0], &ops
[2]);
854 static void asm_branch_opcode(TCCState
*s1
, int token
, int argc
){
856 Operand zero
= {.type
= OP_REG
};
857 parse_operands(s1
, &ops
[0], argc
-1);
858 if ( tok
== ',') next(); else { expect(","); }
859 parse_branch_offset_operand(s1
, &ops
[argc
-1]);
862 /* branch (RS1, RS2, IMM); B-format */
864 asm_emit_b(token
, 0x63 | (0 << 12), ops
, ops
+ 1, ops
+ 2);
867 asm_emit_b(token
, 0x63 | (1 << 12), ops
, ops
+ 1, ops
+ 2);
870 asm_emit_b(token
, 0x63 | (4 << 12), ops
, ops
+ 1, ops
+ 2);
873 asm_emit_b(token
, 0x63 | (5 << 12), ops
, ops
+ 1, ops
+ 2);
876 asm_emit_b(token
, 0x63 | (6 << 12), ops
, ops
+ 1, ops
+ 2);
879 asm_emit_b(token
, 0x63 | (7 << 12), ops
, ops
+ 1, ops
+ 2);
881 /* related pseudoinstructions */
883 asm_emit_b(token
, 0x63 | (4 << 12), ops
+ 1, ops
, ops
+ 2);
886 asm_emit_b(token
, 0x63 | (5 << 12), ops
+ 1, ops
, ops
+ 2);
889 asm_emit_b(token
, 0x63 | (6 << 12), ops
+ 1, ops
, ops
+ 2);
892 asm_emit_b(token
, 0x63 | (7 << 12), ops
+ 1, ops
, ops
+ 2);
894 /* shorter pseudoinstructions */
896 /* bne rs, zero, offset */
897 asm_emit_b(token
, 0x63 | (1 << 12), &ops
[0], &zero
, &ops
[1]);
900 /* bne rs, zero, offset */
901 asm_emit_b(token
, 0x63 | (0 << 12), &ops
[0], &zero
, &ops
[1]);
904 /* bge rs, zero, offset */
905 asm_emit_b(token
, 0x63 | (5 << 12), &ops
[0], &zero
, &ops
[1]);
908 /* bge zero, rs, offset */
909 asm_emit_b(token
, 0x63 | (5 << 12), &zero
, &ops
[0], &ops
[1]);
912 /* blt rs, zero, offset */
913 asm_emit_b(token
, 0x63 | (4 << 12), &ops
[0], &zero
, &ops
[1]);
916 /* blt zero, rs, offset */
917 asm_emit_b(token
, 0x63 | (4 << 12), &zero
, &ops
[0], &ops
[1]);
922 static void asm_ternary_opcode(TCCState
*s1
, int token
)
925 parse_operands(s1
, &ops
[0], 3);
929 asm_emit_r(token
, (0xC << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
932 asm_emit_i(token
, (4 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
935 asm_emit_r(token
, (0xC << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
938 asm_emit_i(token
, (0x4 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
941 asm_emit_r(token
, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
944 asm_emit_i(token
, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops
[0], &ops
[1], &ops
[2]);
947 asm_emit_r(token
, (0xE << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
950 asm_emit_i(token
, (6 << 2) | 3 | (1 << 12), &ops
[0], &ops
[1], &ops
[2]);
953 asm_emit_r(token
, (0xE << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
956 asm_emit_i(token
, (0x6 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
959 asm_emit_r(token
, (0xE << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
962 asm_emit_i(token
, (0x6 << 2) | 3 | (5 << 12), &ops
[0], &ops
[1], &ops
[2]);
965 // Arithmetic (RD,RS1,(RS2|IMM)); R-format, I-format or U-format
968 asm_emit_r(token
, (0xC << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
971 asm_emit_i(token
, (4 << 2) | 3, &ops
[0], &ops
[1], &ops
[2]);
974 asm_emit_r(token
, (0xC << 2) | 3 | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
977 asm_emit_r(token
, (0xE << 2) | 3 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
979 case TOK_ASM_addiw
: // 64 bit
980 asm_emit_i(token
, (0x6 << 2) | 3 | (0 << 12), &ops
[0], &ops
[1], &ops
[2]);
983 asm_emit_r(token
, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops
[0], &ops
[1], &ops
[2]);
986 // Logical (RD,RS1,(RS2|IMM)); R-format or I-format
989 asm_emit_r(token
, (0xC << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
992 asm_emit_i(token
, (0x4 << 2) | 3 | (4 << 12), &ops
[0], &ops
[1], &ops
[2]);
995 asm_emit_r(token
, (0xC << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
998 asm_emit_i(token
, (0x4 << 2) | 3 | (6 << 12), &ops
[0], &ops
[1], &ops
[2]);
1001 asm_emit_r(token
, (0xC << 2) | 3 | (7 << 12), &ops
[0], &ops
[1], &ops
[2]);
1004 asm_emit_i(token
, (0x4 << 2) | 3 | (7 << 12), &ops
[0], &ops
[1], &ops
[2]);
1007 // Compare (RD,RS1,(RS2|IMM)); R-format or I-format
1010 asm_emit_r(token
, (0xC << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
1013 asm_emit_i(token
, (0x4 << 2) | 3 | (2 << 12), &ops
[0], &ops
[1], &ops
[2]);
1016 asm_emit_r(token
, (0xC << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
1019 asm_emit_i(token
, (0x4 << 2) | 3 | (3 << 12), &ops
[0], &ops
[1], &ops
[2]);
1024 asm_emit_r(token
, 0x33 | (4 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1027 asm_emit_r(token
, 0x33 | (5 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1030 asm_emit_r(token
, 0x3b | (5 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1033 asm_emit_r(token
, 0x3b | (4 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1036 asm_emit_r(token
, 0x33 | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1039 asm_emit_r(token
, 0x33 | (1 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1041 case TOK_ASM_mulhsu
:
1042 asm_emit_r(token
, 0x33 | (2 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1045 asm_emit_r(token
, 0x33 | (3 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1048 asm_emit_r(token
, 0x3b | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1051 asm_emit_r(token
, 0x33 | (6 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1054 asm_emit_r(token
, 0x33 | (7 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1057 asm_emit_r(token
, 0x3b | (7 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1060 asm_emit_r(token
, 0x3b | (6 << 12) | (1 << 25), ops
, ops
+ 1, ops
+ 2);
1063 /* Zicsr extension; (rd, csr, rs/uimm) */
1065 asm_emit_i(token
, 0x73 | (3 << 12), ops
, ops
+ 2, ops
+ 1);
1067 case TOK_ASM_csrrci
:
1068 /* using rs1 field for uimmm */
1069 ops
[2].type
= OP_REG
;
1070 asm_emit_i(token
, 0x73 | (7 << 12), ops
, ops
+ 2, ops
+ 1);
1073 asm_emit_i(token
, 0x73 | (2 << 12), ops
, ops
+ 2, ops
+ 1);
1075 case TOK_ASM_csrrsi
:
1076 ops
[2].type
= OP_REG
;
1077 asm_emit_i(token
, 0x73 | (6 << 12), ops
, ops
+ 2, ops
+ 1);
1080 asm_emit_i(token
, 0x73 | (1 << 12), ops
, ops
+ 2, ops
+ 1);
1082 case TOK_ASM_csrrwi
:
1083 ops
[2].type
= OP_REG
;
1084 asm_emit_i(token
, 0x73 | (5 << 12), ops
, ops
+ 2, ops
+ 1);
1088 /* register-based loads and stores (RD, RS1, IMM); CL-format */
1090 asm_emit_cl(token
, 1 << 13, ops
, ops
+ 1, ops
+ 2);
1092 case TOK_ASM_c_flw
: /* RV32FC-only */
1093 asm_emit_cl(token
, 3 << 13, ops
, ops
+ 1, ops
+ 2);
1096 asm_emit_cs(token
, 5 << 13, ops
, ops
+ 1, ops
+ 2);
1098 case TOK_ASM_c_fsw
: /* RV32FC-only */
1099 asm_emit_cs(token
, 7 << 13, ops
, ops
+ 1, ops
+ 2);
1102 asm_emit_cl(token
, 3 << 13, ops
, ops
+ 1, ops
+ 2);
1105 asm_emit_cl(token
, 2 << 13, ops
, ops
+ 1, ops
+ 2);
1108 asm_emit_cs(token
, 7 << 13, ops
, ops
+ 1, ops
+ 2);
1111 asm_emit_cs(token
, 6 << 13, ops
, ops
+ 1, ops
+ 2);
1115 expect("ternary instruction");
1119 static void asm_atomic_opcode(TCCState
*s1
, int token
)
1121 static const Operand zero
= {.type
= OP_REG
};
1124 parse_operand(s1
, &ops
[0]);
1125 if ( tok
== ',') next(); else expect("','");
1127 if ( token
<= TOK_ASM_lr_d_aqrl
&& token
>= TOK_ASM_lr_w
) {
1130 parse_operand(s1
, &ops
[1]);
1131 if ( tok
== ',') next(); else expect("','");
1134 if ( tok
== '(') next(); else expect("'('");
1135 parse_operand(s1
, &ops
[2]);
1136 if ( tok
== ')') next(); else expect("')'");
1140 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1142 case TOK_ASM_lr_w_aq
:
1143 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1145 case TOK_ASM_lr_w_rl
:
1146 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1148 case TOK_ASM_lr_w_aqrl
:
1149 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1153 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1155 case TOK_ASM_lr_d_aq
:
1156 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1158 case TOK_ASM_lr_d_rl
:
1159 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1161 case TOK_ASM_lr_d_aqrl
:
1162 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x2<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1166 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1168 case TOK_ASM_sc_w_aq
:
1169 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1171 case TOK_ASM_sc_w_rl
:
1172 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1174 case TOK_ASM_sc_w_aqrl
:
1175 asm_emit_a(token
, 0x2F | 0x2<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1179 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 0);
1181 case TOK_ASM_sc_d_aq
:
1182 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 0);
1184 case TOK_ASM_sc_d_rl
:
1185 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 0, 1);
1187 case TOK_ASM_sc_d_aqrl
:
1188 asm_emit_a(token
, 0x2F | 0x3<<12 | 0x3<<27, &ops
[0], &ops
[1], &ops
[2], 1, 1);
1193 /* caller: Add funct3 and func5 to opcode */
1194 static void asm_emit_a(int token
, uint32_t opcode
, const Operand
*rd1
, const Operand
*rs2
, const Operand
*rs1
, int aq
, int rl
)
1196 if (rd1
->type
!= OP_REG
)
1197 tcc_error("'%s': Expected first destination operand that is a register", get_tok_str(token
, NULL
));
1198 if (rs2
->type
!= OP_REG
)
1199 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token
, NULL
));
1200 if (rs1
->type
!= OP_REG
)
1201 tcc_error("'%s': Expected third source operand that is a register", get_tok_str(token
, NULL
));
1202 /* A-type instruction:
1211 opcode always fixed pos. */
1212 gen_le32(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | ENCODE_RD(rd1
->reg
) | aq
<< 26 | rl
<< 25);
1215 /* caller: Add funct3 to opcode */
1216 static void asm_emit_s(int token
, uint32_t opcode
, const Operand
* rs1
, const Operand
* rs2
, const Operand
* imm
)
1218 if (rs1
->type
!= OP_REG
) {
1219 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
1222 if (rs2
->type
!= OP_REG
) {
1223 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token
, NULL
));
1226 if (imm
->type
!= OP_IM12S
) {
1227 tcc_error("'%s': Expected third operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
1231 uint16_t v
= imm
->e
.v
;
1232 /* S-type instruction:
1239 opcode always fixed pos. */
1240 gen_le32(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | ((v
& 0x1F) << 7) | ((v
>> 5) << 25));
1244 static void asm_emit_b(int token
, uint32_t opcode
, const Operand
*rs1
, const Operand
*rs2
, const Operand
*imm
)
1248 if (rs1
->type
!= OP_REG
) {
1249 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token
, NULL
));
1252 if (rs2
->type
!= OP_REG
) {
1253 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
1256 if (imm
->type
!= OP_IM12S
) {
1257 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token
, NULL
));
1263 /* B-type instruction:
1272 asm_emit_opcode(opcode
| ENCODE_RS1(rs1
->reg
) | ENCODE_RS2(rs2
->reg
) | (((offset
>> 1) & 0xF) << 8) | (((offset
>> 5) & 0x1f) << 25) | (((offset
>> 11) & 1) << 7) | (((offset
>> 12) & 1) << 31));
1275 ST_FUNC
void asm_opcode(TCCState
*s1
, int token
)
1278 case TOK_ASM_ebreak
:
1280 case TOK_ASM_fence_i
:
1285 asm_nullary_opcode(s1
, token
);
1289 asm_fence_opcode(s1
, token
);
1292 case TOK_ASM_rdcycle
:
1293 case TOK_ASM_rdcycleh
:
1294 case TOK_ASM_rdtime
:
1295 case TOK_ASM_rdtimeh
:
1296 case TOK_ASM_rdinstret
:
1297 case TOK_ASM_rdinstreth
:
1298 asm_unary_opcode(s1
, token
);
1303 asm_binary_opcode(s1
, token
);
1317 asm_mem_access_opcode(s1
, token
);
1321 asm_jalr_opcode(s1
, token
); /* it can be a pseudo instruction too*/
1324 asm_jal_opcode(s1
, token
); /* jal zero, offset*/
1327 asm_jal_opcode(s1
, token
); /* it can be a pseudo instruction too*/
1365 case TOK_ASM_mulhsu
:
1372 /* Zicsr extension */
1374 case TOK_ASM_csrrci
:
1376 case TOK_ASM_csrrsi
:
1378 case TOK_ASM_csrrwi
:
1379 asm_ternary_opcode(s1
, token
);
1389 asm_branch_opcode(s1
, token
, 3);
1393 case TOK_ASM_c_ebreak
:
1395 asm_nullary_opcode(s1
, token
);
1400 case TOK_ASM_c_jalr
:
1402 asm_unary_opcode(s1
, token
);
1406 case TOK_ASM_c_addi16sp
:
1407 case TOK_ASM_c_addi4spn
:
1408 case TOK_ASM_c_addi
:
1409 case TOK_ASM_c_addiw
:
1410 case TOK_ASM_c_addw
:
1412 case TOK_ASM_c_andi
:
1413 case TOK_ASM_c_beqz
:
1414 case TOK_ASM_c_bnez
:
1415 case TOK_ASM_c_fldsp
:
1416 case TOK_ASM_c_flwsp
:
1417 case TOK_ASM_c_fsdsp
:
1418 case TOK_ASM_c_fswsp
:
1419 case TOK_ASM_c_ldsp
:
1422 case TOK_ASM_c_lwsp
:
1425 case TOK_ASM_c_sdsp
:
1426 case TOK_ASM_c_slli
:
1427 case TOK_ASM_c_srai
:
1428 case TOK_ASM_c_srli
:
1430 case TOK_ASM_c_subw
:
1431 case TOK_ASM_c_swsp
:
1433 asm_binary_opcode(s1
, token
);
1444 asm_ternary_opcode(s1
, token
);
1447 /* pseudoinstructions */
1450 asm_nullary_opcode(s1
, token
);
1456 asm_unary_opcode(s1
, token
);
1471 asm_binary_opcode(s1
, token
);
1480 asm_branch_opcode(s1
, token
, 2);
1487 asm_branch_opcode(s1
, token
, 3);
1490 /* Atomic operations */
1492 case TOK_ASM_lr_w_aq
:
1493 case TOK_ASM_lr_w_rl
:
1494 case TOK_ASM_lr_w_aqrl
:
1496 case TOK_ASM_lr_d_aq
:
1497 case TOK_ASM_lr_d_rl
:
1498 case TOK_ASM_lr_d_aqrl
:
1500 case TOK_ASM_sc_w_aq
:
1501 case TOK_ASM_sc_w_rl
:
1502 case TOK_ASM_sc_w_aqrl
:
1504 case TOK_ASM_sc_d_aq
:
1505 case TOK_ASM_sc_d_rl
:
1506 case TOK_ASM_sc_d_aqrl
:
1507 asm_atomic_opcode(s1
, token
);
1511 expect("known instruction");
1515 static int asm_parse_csrvar(int t
)
1522 case TOK_ASM_fflags
:
1526 case TOK_ASM_instret
:
1530 case TOK_ASM_cycleh
:
1532 case TOK_ASM_instreth
:
1541 ST_FUNC
void subst_asm_operand(CString
*add_str
, SValue
*sv
, int modifier
)
1547 if ((r
& VT_VALMASK
) == VT_CONST
) {
1548 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n' &&
1550 //cstr_ccat(add_str, '#');
1553 const char *name
= get_tok_str(sv
->sym
->v
, NULL
);
1554 if (sv
->sym
->v
>= SYM_FIRST_ANOM
) {
1555 /* In case of anonymous symbols ("L.42", used
1556 for static data labels) we can't find them
1557 in the C symbol table when later looking up
1558 this name. So enter them now into the asm label
1559 list when we still know the symbol. */
1560 get_asm_sym(tok_alloc(name
, strlen(name
))->tok
, sv
->sym
);
1562 if (tcc_state
->leading_underscore
)
1563 cstr_ccat(add_str
, '_');
1564 cstr_cat(add_str
, name
, -1);
1565 if ((uint32_t) sv
->c
.i
== 0)
1567 cstr_ccat(add_str
, '+');
1570 if (modifier
== 'n')
1572 if (modifier
== 'z' && sv
->c
.i
== 0) {
1573 cstr_cat(add_str
, "zero", -1);
1575 snprintf(buf
, sizeof(buf
), "%d", (int) sv
->c
.i
);
1576 cstr_cat(add_str
, buf
, -1);
1579 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1580 snprintf(buf
, sizeof(buf
), "%d", (int) sv
->c
.i
);
1581 cstr_cat(add_str
, buf
, -1);
1582 } else if (r
& VT_LVAL
) {
1583 reg
= r
& VT_VALMASK
;
1584 if (reg
>= VT_CONST
)
1585 tcc_internal_error("");
1586 if ((sv
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1587 (sv
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1588 /* floating point register */
1589 reg
= TOK_ASM_f0
+ reg
;
1591 /* general purpose register */
1592 reg
= TOK_ASM_x0
+ reg
;
1594 snprintf(buf
, sizeof(buf
), "%s", get_tok_str(reg
, NULL
));
1595 cstr_cat(add_str
, buf
, -1);
1598 reg
= r
& VT_VALMASK
;
1599 if (reg
>= VT_CONST
)
1600 tcc_internal_error("");
1601 if ((sv
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1602 (sv
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1603 /* floating point register */
1604 reg
= TOK_ASM_f0
+ reg
;
1606 /* general purpose register */
1607 reg
= TOK_ASM_x0
+ reg
;
1609 snprintf(buf
, sizeof(buf
), "%s", get_tok_str(reg
, NULL
));
1610 cstr_cat(add_str
, buf
, -1);
1614 /* TCC does not use RISC-V register numbers internally, it uses 0-8 for
1615 * integers and 8-16 for floats instead */
1616 static int tcc_ireg(int r
){
1617 return REG_VALUE(r
) - 10;
1619 static int tcc_freg(int r
){
1620 return REG_VALUE(r
) - 10 + 8;
1623 /* generate prolog and epilog code for asm statement */
1624 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1625 int nb_outputs
, int is_output
,
1626 uint8_t *clobber_regs
,
1629 uint8_t regs_allocated
[NB_ASM_REGS
];
1633 static const uint8_t reg_saved
[] = {
1634 // General purpose regs
1635 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
1637 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59
1640 /* mark all used registers */
1641 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1642 for(i
= 0; i
< nb_operands
; i
++) {
1645 regs_allocated
[op
->reg
] = 1;
1650 /* generate reg save code */
1651 for(i
= 0; i
< sizeof(reg_saved
)/sizeof(reg_saved
[0]); i
++) {
1653 if (regs_allocated
[reg
]) {
1655 /* addi sp, sp, -offset */
1656 gen_le32((4 << 2) | 3 |
1657 ENCODE_RD(2) | ENCODE_RS1(2) | -8 << 20);
1658 if (REG_IS_FLOAT(reg
)){
1659 /* fsd reg, offset(sp) */
1660 gen_le32( 0x27 | (3 << 12) |
1661 ENCODE_RS2(reg
) | ENCODE_RS1(2) );
1663 /* sd reg, offset(sp) */
1664 gen_le32((0x8 << 2) | 3 | (3 << 12) |
1665 ENCODE_RS2(reg
) | ENCODE_RS1(2) );
1670 /* generate load code */
1671 for(i
= 0; i
< nb_operands
; i
++) {
1674 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1676 /* memory reference case (for both input and
1680 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
| VT_LVAL
;
1682 load(tcc_ireg(op
->reg
), &sv
);
1683 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1684 /* load value in register */
1685 if ((op
->vt
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1686 (op
->vt
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1687 load(tcc_freg(op
->reg
), op
->vt
);
1689 load(tcc_ireg(op
->reg
), op
->vt
);
1692 tcc_error("long long not implemented");
1698 /* generate save code */
1699 for(i
= 0 ; i
< nb_outputs
; i
++) {
1702 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1703 if (!op
->is_memory
) {
1706 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1708 load(tcc_ireg(out_reg
), &sv
);
1711 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1712 store(tcc_ireg(op
->reg
), &sv
);
1715 if ((op
->vt
->type
.t
& VT_BTYPE
) == VT_FLOAT
||
1716 (op
->vt
->type
.t
& VT_BTYPE
) == VT_DOUBLE
) {
1717 store(tcc_freg(op
->reg
), op
->vt
);
1719 store(tcc_ireg(op
->reg
), op
->vt
);
1722 tcc_error("long long not implemented");
1727 /* generate reg restore code for floating point registers */
1728 for(i
= sizeof(reg_saved
)/sizeof(reg_saved
[0]) - 1; i
>= 0; i
--) {
1730 if (regs_allocated
[reg
]) {
1732 if (REG_IS_FLOAT(reg
)){
1733 /* fld reg, offset(sp) */
1734 gen_le32(7 | (3 << 12) |
1735 ENCODE_RD(reg
) | ENCODE_RS1(2) | 0);
1737 /* ld reg, offset(sp) */
1738 gen_le32(3 | (3 << 12) |
1739 ENCODE_RD(reg
) | ENCODE_RS1(2) | 0);
1741 /* addi sp, sp, offset */
1742 gen_le32((4 << 2) | 3 |
1743 ENCODE_RD(2) | ENCODE_RS1(2) | 8 << 20);
1749 /* return the constraint priority (we allocate first the lowest
1750 numbered constraints) */
1751 static inline int constraint_priority(const char *str
)
1753 // TODO: How is this chosen??
1754 int priority
, c
, pr
;
1756 /* we take the lowest priority */
1764 case 'A': // address that is held in a general-purpose register.
1765 case 'S': // constraint that matches an absolute symbolic address.
1766 case 'f': // register [float]
1767 case 'r': // register [general]
1768 case 'p': // valid memory address for load,store [general]
1771 case 'I': // 12 bit signed immedate
1772 case 'i': // immediate integer operand, including symbolic constants [general]
1773 case 'm': // memory operand [general]
1774 case 'g': // general-purpose-register, memory, immediate integer [general]
1778 tcc_error("unimp: vector constraints '%d'", c
);
1782 tcc_error("unknown constraint '%d'", c
);
1791 static const char *skip_constraint_modifiers(const char *p
)
1793 /* Constraint modifier:
1794 = Operand is written to by this instruction
1795 + Operand is both read and written to by this instruction
1796 % Instruction is commutative for this operand and the following operand.
1798 Per-alternative constraint modifier:
1799 & Operand is clobbered before the instruction is done using the input operands
1801 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1806 #define REG_OUT_MASK 0x01
1807 #define REG_IN_MASK 0x02
1809 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1811 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1812 int nb_operands
, int nb_outputs
,
1813 const uint8_t *clobber_regs
,
1816 /* TODO: Simple constraints
1818 o memory operand that is offsetable
1819 V memory but not offsetable
1820 < memory operand with autodecrement addressing is allowed. Restrictions apply.
1821 > memory operand with autoincrement addressing is allowed. Restrictions apply.
1822 n immediate integer operand with a known numeric value
1823 E immediate floating operand (const_double) is allowed, but only if target=host
1824 F immediate floating operand (const_double or const_vector) is allowed
1825 s immediate integer operand whose value is not an explicit integer
1826 X any operand whatsoever
1827 0...9 (postfix); (can also be more than 1 digit number); an operand that matches the specified operand number is allowed
1830 /* TODO: RISCV constraints
1832 K A 5-bit unsigned immediate for CSR access instructions.
1833 A An address that is held in a general-purpose register.
1834 S A constraint that matches an absolute symbolic address.
1835 vr A vector register (if available)..
1836 vd A vector register, excluding v0 (if available).
1837 vm A vector register, only v0 (if available).
1840 int sorted_op
[MAX_ASM_OPERANDS
];
1841 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1843 uint8_t regs_allocated
[NB_ASM_REGS
];
1846 for (i
= 0; i
< nb_operands
; i
++) {
1848 op
->input_index
= -1;
1854 /* compute constraint priority and evaluate references to output
1855 constraints if input constraints */
1856 for (i
= 0; i
< nb_operands
; i
++) {
1858 str
= op
->constraint
;
1859 str
= skip_constraint_modifiers(str
);
1860 if (isnum(*str
) || *str
== '[') {
1861 /* this is a reference to another constraint */
1862 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1863 if ((unsigned) k
>= i
|| i
< nb_outputs
)
1864 tcc_error("invalid reference in constraint %d ('%s')",
1867 if (operands
[k
].input_index
>= 0)
1868 tcc_error("cannot reference twice the same operand");
1869 operands
[k
].input_index
= i
;
1871 } else if ((op
->vt
->r
& VT_VALMASK
) == VT_LOCAL
1873 && (reg
= op
->vt
->sym
->r
& VT_VALMASK
) < VT_CONST
) {
1877 op
->priority
= constraint_priority(str
);
1881 /* sort operands according to their priority */
1882 for (i
= 0; i
< nb_operands
; i
++)
1884 for (i
= 0; i
< nb_operands
- 1; i
++) {
1885 for (j
= i
+ 1; j
< nb_operands
; j
++) {
1886 p1
= operands
[sorted_op
[i
]].priority
;
1887 p2
= operands
[sorted_op
[j
]].priority
;
1890 sorted_op
[i
] = sorted_op
[j
];
1896 for (i
= 0; i
< NB_ASM_REGS
; i
++) {
1897 if (clobber_regs
[i
])
1898 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1900 regs_allocated
[i
] = 0;
1903 /* allocate registers and generate corresponding asm moves */
1904 for (i
= 0; i
< nb_operands
; i
++) {
1907 str
= op
->constraint
;
1908 /* no need to allocate references */
1909 if (op
->ref_index
>= 0)
1911 /* select if register is used for output, input or both */
1912 if (op
->input_index
>= 0) {
1913 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1914 } else if (j
< nb_outputs
) {
1915 reg_mask
= REG_OUT_MASK
;
1917 reg_mask
= REG_IN_MASK
;
1920 if (is_reg_allocated(op
->reg
))
1922 ("asm regvar requests register that's taken already");
1928 case '=': // Operand is written-to
1930 case '+': // Operand is both READ and written-to
1933 case '&': // Operand is clobbered before the instruction is done using the input operands
1934 if (j
>= nb_outputs
)
1935 tcc_error("'%c' modifier can only be applied to outputs", c
);
1936 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1938 case 'r': // general-purpose register
1939 case 'p': // loadable/storable address
1940 /* any general register */
1942 if ((reg
= op
->reg
) >= 0)
1944 else for (reg
= 10; reg
<= 18; reg
++) {
1945 if (!is_reg_allocated(reg
))
1950 /* now we can reload in the register */
1953 regs_allocated
[reg
] |= reg_mask
;
1955 case 'f': // floating pont register
1956 /* floating point register */
1957 /* From fa0 to fa7 */
1958 if ((reg
= op
->reg
) >= 0)
1960 else for (reg
= 42; reg
<= 50; reg
++) {
1961 if (!is_reg_allocated(reg
))
1965 case 'I': // I-Type 12 bit signed immediate
1966 case 'i': // immediate integer operand, including symbolic constants
1967 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1970 case 'm': // memory operand
1971 case 'g': // any register
1972 /* nothing special to do because the operand is already in
1973 memory, except if the pointer itself is stored in a
1974 memory variable (VT_LLOCAL case) */
1975 /* XXX: fix constant case */
1976 /* if it is a reference to a memory zone, it must lie
1977 in a register, so we reserve the register in the
1978 input registers and a load will be generated
1980 if (j
< nb_outputs
|| c
== 'm') {
1981 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1982 /* any general register: from a0 to a7 */
1983 for (reg
= 10; reg
<= 18; reg
++) {
1984 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1989 /* now we can reload in the register */
1990 regs_allocated
[reg
] |= REG_IN_MASK
;
1997 tcc_error("asm constraint %d ('%s') could not be satisfied",
2001 /* if a reference is present for that operand, we assign it too */
2002 if (op
->input_index
>= 0) {
2003 operands
[op
->input_index
].reg
= op
->reg
;
2004 operands
[op
->input_index
].is_llong
= op
->is_llong
;
2008 /* compute out_reg. It is used to store outputs registers to memory
2009 locations references by pointers (VT_LLOCAL case) */
2011 for (i
= 0; i
< nb_operands
; i
++) {
2014 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&& !op
->is_memory
) {
2015 if (REG_IS_FLOAT(op
->reg
)){
2016 /* From fa0 to fa7 */
2017 for (reg
= 42; reg
<= 50; reg
++) {
2018 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
2023 for (reg
= 10; reg
<= 18; reg
++) {
2024 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
2028 tcc_error("could not find free output register for reloading");
2035 /* print sorted constraints */
2037 for (i
= 0; i
< nb_operands
; i
++) {
2040 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
2042 op
->id
? get_tok_str(op
->id
, NULL
) : "",
2043 op
->constraint
, op
->vt
->r
, op
->reg
);
2046 printf("out_reg=%d\n", *pout_reg
);
2050 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
2055 if (!strcmp(str
, "memory") ||
2056 !strcmp(str
, "cc") ||
2057 !strcmp(str
, "flags"))
2059 ts
= tok_alloc(str
, strlen(str
));
2060 reg
= asm_parse_regvar(ts
->tok
);
2062 tcc_error("invalid clobber register '%s'", str
);
2064 clobber_regs
[reg
] = 1;
2067 ST_FUNC
int asm_parse_regvar (int t
)
2069 /* PC register not implemented */
2070 if (t
>= TOK_ASM_pc
|| t
< TOK_ASM_x0
)
2074 return t
- TOK_ASM_x0
;
2076 if (t
< TOK_ASM_zero
)
2077 return t
- TOK_ASM_f0
+ 32; // Use higher 32 for floating point
2080 if (t
< TOK_ASM_ft0
)
2081 return t
- TOK_ASM_zero
;
2083 return t
- TOK_ASM_ft0
+ 32; // Use higher 32 for floating point
2086 /*************************************************************/
2089 /* caller: Add funct6, funct2 into opcode */
2090 static void asm_emit_ca(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
)
2094 if (rd
->type
!= OP_REG
) {
2095 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2099 if (rs2
->type
!= OP_REG
) {
2100 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2104 /* subtract index of x8 */
2108 /* only registers {x,f}8 to {x,f}15 are valid (3-bit) */
2110 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2115 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2119 /* CA-type instruction:
2126 gen_le16(opcode
| C_ENCODE_RS2(src
) | C_ENCODE_RS1(dst
));
2129 static void asm_emit_cb(int token
, uint16_t opcode
, const Operand
*rs1
, const Operand
*imm
)
2134 if (rs1
->type
!= OP_REG
) {
2135 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2139 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2140 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2147 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token
, NULL
));
2154 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2158 /* CB-type instruction:
2165 /* non-branch also using CB:
2174 case TOK_ASM_c_beqz
:
2175 case TOK_ASM_c_bnez
:
2176 gen_le16(opcode
| C_ENCODE_RS1(src
) | ((NTH_BIT(offset
, 5) | (((offset
>> 1) & 3) << 1) | (((offset
>> 6) & 3) << 3)) << 2) | ((((offset
>> 3) & 3) | NTH_BIT(offset
, 8)) << 10));
2179 gen_le16(opcode
| C_ENCODE_RS1(src
) | ((offset
& 0x1f) << 2) | (NTH_BIT(offset
, 5) << 12));
2184 static void asm_emit_ci(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
)
2188 if (rd
->type
!= OP_REG
) {
2189 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2193 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2194 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2198 immediate
= imm
->e
.v
;
2200 /* CI-type instruction:
2208 case TOK_ASM_c_addi
:
2209 case TOK_ASM_c_addiw
:
2211 case TOK_ASM_c_slli
:
2212 gen_le16(opcode
| ((immediate
& 0x1f) << 2) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2214 case TOK_ASM_c_addi16sp
:
2215 gen_le16(opcode
| NTH_BIT(immediate
, 5) << 2 | (((immediate
>> 7) & 3) << 3) | NTH_BIT(immediate
, 6) << 5 | NTH_BIT(immediate
, 4) << 6 | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 9) << 12));
2218 gen_le16(opcode
| (((immediate
>> 12) & 0x1f) << 2) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 17) << 12));
2220 case TOK_ASM_c_fldsp
:
2221 case TOK_ASM_c_ldsp
:
2222 gen_le16(opcode
| (((immediate
>> 6) & 7) << 2) | (((immediate
>> 3) & 2) << 5) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2224 case TOK_ASM_c_flwsp
:
2225 case TOK_ASM_c_lwsp
:
2226 gen_le16(opcode
| (((immediate
>> 6) & 3) << 2) | (((immediate
>> 2) & 7) << 4) | ENCODE_RD(rd
->reg
) | (NTH_BIT(immediate
, 5) << 12));
2232 expect("known instruction");
2236 /* caller: Add funct3 into opcode */
2237 static void asm_emit_ciw(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*imm
)
2242 if (rd
->type
!= OP_REG
) {
2243 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2247 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2248 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2255 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2261 if (nzuimm
> 0x3fc) {
2262 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0x3ff", get_tok_str(token
, NULL
));
2267 tcc_error("'%s': Expected source operand that is a non-zero immediate value divisible by 4", get_tok_str(token
, NULL
));
2271 /* CIW-type instruction:
2277 gen_le16(opcode
| ENCODE_RS2(rd
->reg
) | ((NTH_BIT(nzuimm
, 3) | (NTH_BIT(nzuimm
, 2) << 1) | (((nzuimm
>> 6) & 0xf) << 2) | (((nzuimm
>> 4) & 3) << 6)) << 5));
2280 /* caller: Add funct3 into opcode */
2281 static void asm_emit_cj(int token
, uint16_t opcode
, const Operand
*imm
)
2286 if (imm
->type
!= OP_IM12S
) {
2287 tcc_error("'%s': Expected source operand that is a 12-bit immediate value", get_tok_str(token
, NULL
));
2294 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token
, NULL
));
2298 /* CJ-type instruction:
2300 12...2 offset[11|4|9:8|10|6|7|3:1|5]
2303 gen_le16(opcode
| (NTH_BIT(offset
, 5) << 2) | (((offset
>> 1) & 7) << 3) | (NTH_BIT(offset
, 7) << 6) | (NTH_BIT(offset
, 6) << 7) | (NTH_BIT(offset
, 10) << 8) | (((offset
>> 8) & 3) << 9) | (NTH_BIT(offset
, 4) << 11) | (NTH_BIT(offset
, 11) << 12));
2306 /* caller: Add funct3 into opcode */
2307 static void asm_emit_cl(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs1
, const Operand
*imm
)
2312 if (rd
->type
!= OP_REG
) {
2313 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2317 if (rs1
->type
!= OP_REG
) {
2318 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2322 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2323 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2331 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2336 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2342 if (offset
> 0xff) {
2343 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2348 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2352 /* CL-type instruction:
2364 gen_le16(opcode
| C_ENCODE_RS2(dst
) | C_ENCODE_RS1(src
) | (NTH_BIT(offset
, 6) << 5) | (NTH_BIT(offset
, 2) << 6) | (((offset
>> 3) & 7) << 10));
2369 gen_le16(opcode
| C_ENCODE_RS2(dst
) | C_ENCODE_RS1(src
) | (((offset
>> 6) & 3) << 5) | (((offset
>> 3) & 7) << 10));
2372 expect("known instruction");
2376 /* caller: Add funct4 into opcode */
2377 static void asm_emit_cr(int token
, uint16_t opcode
, const Operand
*rd
, const Operand
*rs2
)
2379 if (rd
->type
!= OP_REG
) {
2380 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2384 if (rs2
->type
!= OP_REG
) {
2385 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2389 /* CR-type instruction:
2395 gen_le16(opcode
| C_ENCODE_RS1(rd
->reg
) | C_ENCODE_RS2(rs2
->reg
));
2398 /* caller: Add funct3 into opcode */
2399 static void asm_emit_cs(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*rs1
, const Operand
*imm
)
2404 if (rs2
->type
!= OP_REG
) {
2405 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2409 if (rs1
->type
!= OP_REG
) {
2410 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token
, NULL
));
2414 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2415 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2419 base
= rs1
->reg
- 8;
2423 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2428 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token
, NULL
));
2434 if (offset
> 0xff) {
2435 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2440 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2444 /* CS-type instruction:
2455 gen_le16(opcode
| C_ENCODE_RS2(base
) | C_ENCODE_RS1(src
) | (NTH_BIT(offset
, 6) << 5) | (NTH_BIT(offset
, 2) << 6) | (((offset
>> 3) & 7) << 10));
2460 gen_le16(opcode
| C_ENCODE_RS2(base
) | C_ENCODE_RS1(src
) | (((offset
>> 6) & 3) << 5) | (((offset
>> 3) & 7) << 10));
2463 expect("known instruction");
2467 /* caller: Add funct3 into opcode */
2468 static void asm_emit_css(int token
, uint16_t opcode
, const Operand
*rs2
, const Operand
*imm
)
2472 if (rs2
->type
!= OP_REG
) {
2473 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token
, NULL
));
2477 if (imm
->type
!= OP_IM12S
&& imm
->type
!= OP_IM32
) {
2478 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token
, NULL
));
2484 if (offset
> 0xff) {
2485 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token
, NULL
));
2490 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token
, NULL
));
2494 /* CSS-type instruction:
2502 case TOK_ASM_c_fswsp
:
2503 case TOK_ASM_c_swsp
:
2504 gen_le16(opcode
| ENCODE_RS2(rs2
->reg
) | (((offset
>> 6) & 3) << 7) | (((offset
>> 2) & 0xf) << 9));
2507 case TOK_ASM_c_fsdsp
:
2508 case TOK_ASM_c_sdsp
:
2509 gen_le16(opcode
| ENCODE_RS2(rs2
->reg
) | (((offset
>> 6) & 7) << 7) | (((offset
>> 3) & 7) << 10));
2512 expect("known instruction");
2516 /*************************************************************/
2517 #endif /* ndef TARGET_DEFS_ONLY */