2 * i386 specific functions for TCC assembler
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* #define NB_ASM_REGS 8 */
25 #define MAX_OPERANDS 3
26 #define NB_SAVED_REGS 3
28 #define TOK_ASM_first TOK_ASM_clc
29 #define TOK_ASM_last TOK_ASM_emms
30 #define TOK_ASM_alllast TOK_ASM_subps
32 #define OPC_B 0x01 /* only used with OPC_WL */
33 #define OPC_WL 0x02 /* accepts w, l or no suffix */
34 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
35 #define OPC_REG 0x04 /* register is added to opcode */
36 #define OPC_MODRM 0x08 /* modrm encoding */
38 #define OPCT_MASK 0x70
39 #define OPC_FWAIT 0x10 /* add fwait opcode */
40 #define OPC_SHIFT 0x20 /* shift opcodes */
41 #define OPC_ARITH 0x30 /* arithmetic opcodes */
42 #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
43 #define OPC_TEST 0x50 /* test opcodes */
44 #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
46 #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
47 #ifdef TCC_TARGET_X86_64
48 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
49 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
50 # define OPC_WLX OPC_WLQ
51 # define OPC_BWLX OPC_BWLQ
53 # define OPC_WLX OPC_WL
54 # define OPC_BWLX OPC_BWL
57 #define OPC_GROUP_SHIFT 13
59 /* in order to compress the operand type, we use specific operands and
62 OPT_REG8
=0, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_REG16
, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_REG32
, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #ifdef TCC_TARGET_X86_64
66 OPT_REG64
, /* warning: value is hardcoded from TOK_ASM_xxx */
68 OPT_MMX
, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SSE
, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_CR
, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_TR
, /* warning: value is hardcoded from TOK_ASM_xxx */
72 OPT_DB
, /* warning: value is hardcoded from TOK_ASM_xxx */
79 #ifdef TCC_TARGET_X86_64
82 OPT_EAX
, /* %al, %ax, %eax or %rax register */
83 OPT_ST0
, /* %st(0) register */
84 OPT_CL
, /* %cl register */
85 OPT_DX
, /* %dx register */
86 OPT_ADDR
, /* OP_EA with only offset */
87 OPT_INDIR
, /* *(expr) */
90 OPT_IM
, /* IM8 | IM16 | IM32 */
91 OPT_REG
, /* REG8 | REG16 | REG32 | REG64 */
92 OPT_REGW
, /* REG16 | REG32 | REG64 */
93 OPT_IMW
, /* IM16 | IM32 */
94 OPT_MMXSSE
, /* MMX | SSE */
95 OPT_DISP
, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
96 OPT_DISP8
, /* Like OPT_ADDR, but only 8bit (short jumps) */
97 /* can be ored with any OPT_xxx */
101 #define OP_REG8 (1 << OPT_REG8)
102 #define OP_REG16 (1 << OPT_REG16)
103 #define OP_REG32 (1 << OPT_REG32)
104 #define OP_MMX (1 << OPT_MMX)
105 #define OP_SSE (1 << OPT_SSE)
106 #define OP_CR (1 << OPT_CR)
107 #define OP_TR (1 << OPT_TR)
108 #define OP_DB (1 << OPT_DB)
109 #define OP_SEG (1 << OPT_SEG)
110 #define OP_ST (1 << OPT_ST)
111 #define OP_IM8 (1 << OPT_IM8)
112 #define OP_IM8S (1 << OPT_IM8S)
113 #define OP_IM16 (1 << OPT_IM16)
114 #define OP_IM32 (1 << OPT_IM32)
115 #define OP_EAX (1 << OPT_EAX)
116 #define OP_ST0 (1 << OPT_ST0)
117 #define OP_CL (1 << OPT_CL)
118 #define OP_DX (1 << OPT_DX)
119 #define OP_ADDR (1 << OPT_ADDR)
120 #define OP_INDIR (1 << OPT_INDIR)
121 #ifdef TCC_TARGET_X86_64
122 # define OP_REG64 (1 << OPT_REG64)
123 # define OP_IM64 (1 << OPT_IM64)
124 # define OP_EA32 (OP_EA << 1)
131 #define OP_EA 0x40000000
132 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
134 #ifdef TCC_TARGET_X86_64
135 # define TREG_XAX TREG_RAX
136 # define TREG_XCX TREG_RCX
137 # define TREG_XDX TREG_RDX
139 # define TREG_XAX TREG_EAX
140 # define TREG_XCX TREG_ECX
141 # define TREG_XDX TREG_EDX
144 typedef struct ASMInstr
{
149 uint8_t op_type
[MAX_OPERANDS
]; /* see OP_xxx */
152 typedef struct Operand
{
154 int8_t reg
; /* register, -1 if none */
155 int8_t reg2
; /* second register, -1 if none */
160 static const uint8_t reg_to_size
[9] = {
165 #ifdef TCC_TARGET_X86_64
169 0, 0, 1, 0, 2, 0, 0, 0, 3
172 #define NB_TEST_OPCODES 30
174 static const uint8_t test_bits
[NB_TEST_OPCODES
] = {
207 static const uint8_t segment_prefixes
[] = {
216 static const ASMInstr asm_instrs
[] = {
218 /* This removes a 0x0f in the second byte */
219 #define O(o) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o))
220 /* This constructs instr_type from opcode, type and group. */
221 #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
222 #define DEF_ASM_OP0(name, opcode)
223 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0 },
224 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
225 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
226 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
227 #ifdef TCC_TARGET_X86_64
228 # include "x86_64-asm.h"
230 # include "i386-asm.h"
236 static const uint16_t op0_codes
[] = {
238 #define DEF_ASM_OP0(x, opcode) opcode,
239 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
240 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
241 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
242 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
243 #ifdef TCC_TARGET_X86_64
244 # include "x86_64-asm.h"
246 # include "i386-asm.h"
250 static inline int get_reg_shift(TCCState
*s1
)
253 v
= asm_int_expr(s1
);
268 expect("1, 2, 4 or 8 constant");
275 static int asm_parse_reg(int *type
)
282 if (tok
>= TOK_ASM_eax
&& tok
<= TOK_ASM_edi
) {
283 reg
= tok
- TOK_ASM_eax
;
284 #ifdef TCC_TARGET_X86_64
286 } else if (tok
>= TOK_ASM_rax
&& tok
<= TOK_ASM_rdi
) {
287 reg
= tok
- TOK_ASM_rax
;
288 } else if (tok
== TOK_ASM_rip
) {
299 static void parse_operand(TCCState
*s1
, Operand
*op
)
313 if (tok
>= TOK_ASM_al
&& tok
<= TOK_ASM_db7
) {
314 reg
= tok
- TOK_ASM_al
;
315 op
->type
= 1 << (reg
>> 3); /* WARNING: do not change constant order */
317 if ((op
->type
& OP_REG
) && op
->reg
== TREG_XAX
)
319 else if (op
->type
== OP_REG8
&& op
->reg
== TREG_XCX
)
321 else if (op
->type
== OP_REG16
&& op
->reg
== TREG_XDX
)
323 } else if (tok
>= TOK_ASM_dr0
&& tok
<= TOK_ASM_dr7
) {
325 op
->reg
= tok
- TOK_ASM_dr0
;
326 } else if (tok
>= TOK_ASM_es
&& tok
<= TOK_ASM_gs
) {
328 op
->reg
= tok
- TOK_ASM_es
;
329 } else if (tok
== TOK_ASM_st
) {
335 if (tok
!= TOK_PPNUM
)
339 if ((unsigned)reg
>= 8 || p
[1] != '\0')
350 tcc_error("unknown register");
354 } else if (tok
== '$') {
361 if (op
->e
.v
== (uint8_t)op
->e
.v
)
363 if (op
->e
.v
== (int8_t)op
->e
.v
)
365 if (op
->e
.v
== (uint16_t)op
->e
.v
)
367 #ifdef TCC_TARGET_X86_64
368 if (op
->e
.v
!= (int32_t)op
->e
.v
)
373 /* address(reg,reg2,shift) with all variants */
388 /* bracketed offset expression */
402 op
->reg
= asm_parse_reg(&type
);
407 op
->reg2
= asm_parse_reg(&type
);
411 op
->shift
= get_reg_shift(s1
);
418 if (op
->reg
== -1 && op
->reg2
== -1)
424 /* XXX: unify with C code output ? */
425 ST_FUNC
void gen_expr32(ExprValue
*pe
)
428 /* If PC-relative, always set VT_SYM, even without symbol,
429 so as to force a relocation to be emitted. */
430 gen_addrpc32(VT_SYM
, pe
->sym
, pe
->v
);
432 gen_addr32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
435 #ifdef TCC_TARGET_X86_64
436 ST_FUNC
void gen_expr64(ExprValue
*pe
)
438 gen_addr64(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
442 /* XXX: unify with C code output ? */
443 static void gen_disp32(ExprValue
*pe
)
446 if (sym
&& sym
->r
== cur_text_section
->sh_num
) {
447 /* same section: we can output an absolute value. Note
448 that the TCC compiler behaves differently here because
449 it always outputs a relocation to ease (future) code
450 elimination in the linker */
451 gen_le32(pe
->v
+ sym
->jnext
- ind
- 4);
453 if (sym
&& sym
->type
.t
== VT_VOID
) {
454 sym
->type
.t
= VT_FUNC
;
455 sym
->type
.ref
= NULL
;
457 gen_addrpc32(VT_SYM
, sym
, pe
->v
);
461 /* generate the modrm operand */
462 static inline int asm_modrm(int reg
, Operand
*op
)
464 int mod
, reg1
, reg2
, sib_reg1
;
466 if (op
->type
& (OP_REG
| OP_MMX
| OP_SSE
)) {
467 g(0xc0 + (reg
<< 3) + op
->reg
);
468 } else if (op
->reg
== -1 && op
->reg2
== -1) {
469 /* displacement only */
470 #ifdef TCC_TARGET_X86_64
471 g(0x04 + (reg
<< 3));
474 g(0x05 + (reg
<< 3));
477 #ifdef TCC_TARGET_X86_64
478 } else if (op
->reg
== 8) {
479 ExprValue
*pe
= &op
->e
;
480 g(0x05 + (reg
<< 3));
481 gen_addrpc32(pe
->sym
? VT_SYM
: 0, pe
->sym
, pe
->v
);
486 /* fist compute displacement encoding */
487 if (sib_reg1
== -1) {
490 } else if (op
->e
.v
== 0 && !op
->e
.sym
&& op
->reg
!= 5) {
492 } else if (op
->e
.v
== (int8_t)op
->e
.v
&& !op
->e
.sym
) {
497 /* compute if sib byte needed */
501 g(mod
+ (reg
<< 3) + reg1
);
506 reg2
= 4; /* indicate no index */
507 g((op
->shift
<< 6) + (reg2
<< 3) + sib_reg1
);
512 } else if (mod
== 0x80 || op
->reg
== -1) {
519 static void maybe_print_stats (void)
521 static int already
= 1;
523 /* print stats about opcodes */
525 const struct ASMInstr
*pa
;
528 int nb_op_vals
, i
, j
;
532 memset(freq
, 0, sizeof(freq
));
533 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
535 //for(i=0;i<pa->nb_ops;i++) {
536 for(j
=0;j
<nb_op_vals
;j
++) {
537 //if (pa->op_type[i] == op_vals[j])
538 if (pa
->instr_type
== op_vals
[j
])
541 //op_vals[nb_op_vals++] = pa->op_type[i];
542 op_vals
[nb_op_vals
++] = pa
->instr_type
;
546 for(i
=0;i
<nb_op_vals
;i
++) {
548 //if ((v & (v - 1)) != 0)
549 printf("%3d: %08x\n", i
, v
);
551 printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
552 (int)sizeof(asm_instrs
),
553 (int)sizeof(asm_instrs
) / (int)sizeof(ASMInstr
),
554 freq
[0], freq
[1], freq
[2], freq
[3]);
558 ST_FUNC
void asm_opcode(TCCState
*s1
, int opcode
)
561 int i
, modrm_index
, reg
, v
, op1
, seg_prefix
, pc
;
563 Operand ops
[MAX_OPERANDS
], *pop
;
564 int op_type
[3]; /* decoded op type */
565 int alltypes
; /* OR of all operand types */
570 /* force synthetic ';' after prefix instruction, so we can handle */
571 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
572 if (opcode
>= TOK_ASM_wait
&& opcode
<= TOK_ASM_repnz
)
581 if (tok
== ';' || tok
== TOK_LINEFEED
)
583 if (nb_ops
>= MAX_OPERANDS
) {
584 tcc_error("incorrect number of operands");
586 parse_operand(s1
, pop
);
588 if (pop
->type
!= OP_SEG
|| seg_prefix
)
589 tcc_error("incorrect prefix");
590 seg_prefix
= segment_prefixes
[pop
->reg
];
592 parse_operand(s1
, pop
);
593 if (!(pop
->type
& OP_EA
)) {
594 tcc_error("segment prefix must be followed by memory reference");
604 s
= 0; /* avoid warning */
606 /* optimize matching by using a lookup table (no hashing is needed
608 for(pa
= asm_instrs
; pa
->sym
!= 0; pa
++) {
609 int it
= pa
->instr_type
& OPCT_MASK
;
611 if (it
== OPC_FARITH
) {
612 v
= opcode
- pa
->sym
;
613 if (!((unsigned)v
< 8 * 6 && (v
% 6) == 0))
615 } else if (it
== OPC_ARITH
) {
616 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 8*NBWLX
))
618 s
= (opcode
- pa
->sym
) % NBWLX
;
619 if ((pa
->instr_type
& OPC_BWLX
) == OPC_WLX
)
621 /* We need to reject the xxxb opcodes that we accepted above.
622 Note that pa->sym for WLX opcodes is the 'w' token,
623 to get the 'b' token subtract one. */
624 if (((opcode
- pa
->sym
+ 1) % NBWLX
) == 0)
628 } else if (it
== OPC_SHIFT
) {
629 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ 7*NBWLX
))
631 s
= (opcode
- pa
->sym
) % NBWLX
;
632 } else if (it
== OPC_TEST
) {
633 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NB_TEST_OPCODES
))
635 /* cmovxx is a test opcode but accepts multiple sizes.
636 TCC doesn't accept the suffixed mnemonic, instead we
637 simply force size autodetection always. */
638 if (pa
->instr_type
& OPC_WLX
)
640 } else if (pa
->instr_type
& OPC_B
) {
641 #ifdef TCC_TARGET_X86_64
642 /* Some instructions don't have the full size but only
643 bwl form. insb e.g. */
644 if ((pa
->instr_type
& OPC_WLQ
) != OPC_WLQ
645 && !(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
648 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
))
650 s
= opcode
- pa
->sym
;
651 } else if (pa
->instr_type
& OPC_WLX
) {
652 if (!(opcode
>= pa
->sym
&& opcode
< pa
->sym
+ NBWLX
-1))
654 s
= opcode
- pa
->sym
+ 1;
656 if (pa
->sym
!= opcode
)
659 if (pa
->nb_ops
!= nb_ops
)
661 #ifdef TCC_TARGET_X86_64
662 /* Special case for moves. Selecting the IM64->REG64 form
663 should only be done if we really have an >32bit imm64, and that
664 is hardcoded. Ignore it here. */
665 if (pa
->opcode
== 0xb0 && ops
[0].type
!= OP_IM64
666 && ops
[1].type
== OP_REG64
667 && !(pa
->instr_type
& OPC_0F
))
670 /* now decode and check each operand */
672 for(i
= 0; i
< nb_ops
; i
++) {
674 op1
= pa
->op_type
[i
];
678 v
= OP_IM8
| OP_IM16
| OP_IM32
;
681 v
= OP_REG8
| OP_REG16
| OP_REG32
| OP_REG64
;
684 v
= OP_REG16
| OP_REG32
| OP_REG64
;
687 v
= OP_IM16
| OP_IM32
;
703 if ((ops
[i
].type
& v
) == 0)
705 alltypes
|= ops
[i
].type
;
707 /* all is matching ! */
712 if (opcode
>= TOK_ASM_first
&& opcode
<= TOK_ASM_last
) {
714 b
= op0_codes
[opcode
- TOK_ASM_first
];
719 } else if (opcode
<= TOK_ASM_alllast
) {
720 tcc_error("bad operand with opcode '%s'",
721 get_tok_str(opcode
, NULL
));
723 tcc_error("unknown opcode '%s'",
724 get_tok_str(opcode
, NULL
));
727 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
729 #ifdef TCC_TARGET_X86_64
730 /* XXX the autosize should rather be zero, to not have to adjust this
732 if ((pa
->instr_type
& OPC_BWLQ
) == OPC_B
)
736 for(i
= 0; s
== autosize
&& i
< nb_ops
; i
++) {
737 if ((ops
[i
].type
& OP_REG
) && !(op_type
[i
] & (OP_CL
| OP_DX
)))
738 s
= reg_to_size
[ops
[i
].type
& OP_REG
];
741 if ((opcode
== TOK_ASM_push
|| opcode
== TOK_ASM_pop
) &&
742 (ops
[0].type
& (OP_SEG
| OP_IM8S
| OP_IM32
)))
745 tcc_error("cannot infer opcode suffix");
749 #ifdef TCC_TARGET_X86_64
750 /* Generate addr32 prefix if needed */
751 for(i
= 0; i
< nb_ops
; i
++) {
752 if (ops
[i
].type
& OP_EA32
) {
758 /* generate data16 prefix if needed */
763 /* accepting mmx+sse in all operands --> needs 0x66 to
764 switch to sse mode. Accepting only sse in an operand --> is
765 already SSE insn and needs 0x66/f2/f3 handling. */
766 for (i
= 0; i
< nb_ops
; i
++)
767 if ((op_type
[i
] & (OP_MMX
| OP_SSE
)) == (OP_MMX
| OP_SSE
)
768 && ops
[i
].type
& OP_SSE
)
773 #ifdef TCC_TARGET_X86_64
774 if (s
== 3 || (alltypes
& OP_REG64
)) {
775 /* generate REX prefix */
777 for(i
= 0; i
< nb_ops
; i
++) {
778 if (op_type
[i
] == OP_REG64
) {
779 /* If only 64bit regs are accepted in one operand
780 this is a default64 instruction without need for
786 /* XXX find better encoding for the default64 instructions. */
787 if (((opcode
!= TOK_ASM_push
&& opcode
!= TOK_ASM_pop
788 && opcode
!= TOK_ASM_pushw
&& opcode
!= TOK_ASM_pushl
789 && opcode
!= TOK_ASM_pushq
&& opcode
!= TOK_ASM_popw
790 && opcode
!= TOK_ASM_popl
&& opcode
!= TOK_ASM_popq
791 && opcode
!= TOK_ASM_call
&& opcode
!= TOK_ASM_jmp
))
797 /* now generates the operation */
798 if (OPCT_IS(pa
->instr_type
, OPC_FWAIT
))
804 if (pa
->instr_type
& OPC_0F
)
805 v
= ((v
& ~0xff) << 8) | 0x0f00 | (v
& 0xff);
806 if ((v
== 0x69 || v
== 0x6b) && nb_ops
== 2) {
807 /* kludge for imul $im, %reg */
810 op_type
[2] = op_type
[1];
811 } else if (v
== 0xcd && ops
[0].e
.v
== 3 && !ops
[0].e
.sym
) {
812 v
--; /* int $3 case */
814 } else if ((v
== 0x06 || v
== 0x07)) {
815 if (ops
[0].reg
>= 4) {
816 /* push/pop %fs or %gs */
817 v
= 0x0fa0 + (v
- 0x06) + ((ops
[0].reg
- 4) << 3);
819 v
+= ops
[0].reg
<< 3;
822 } else if (v
<= 0x05) {
824 v
+= ((opcode
- TOK_ASM_addb
) / NBWLX
) << 3;
825 } else if ((pa
->instr_type
& (OPCT_MASK
| OPC_MODRM
)) == OPC_FARITH
) {
827 v
+= ((opcode
- pa
->sym
) / 6) << 3;
829 if (pa
->instr_type
& OPC_REG
) {
830 /* mov $im, %reg case */
831 if (v
== 0xb0 && s
>= 1)
833 for(i
= 0; i
< nb_ops
; i
++) {
834 if (op_type
[i
] & (OP_REG
| OP_ST
)) {
840 if (pa
->instr_type
& OPC_B
)
842 if (nb_ops
== 1 && pa
->op_type
[0] == OPT_DISP8
) {
846 /* see if we can really generate the jump with a byte offset */
850 if (sym
->r
!= cur_text_section
->sh_num
)
852 jmp_disp
= ops
[0].e
.v
+ sym
->jnext
- ind
- 2 - (v
>= 0xff);
853 if (jmp_disp
== (int8_t)jmp_disp
) {
854 /* OK to generate jump */
856 ops
[0].e
.v
= jmp_disp
;
857 op_type
[0] = OP_IM8S
;
860 /* long jump will be allowed. need to modify the
862 if (v
== 0xeb) /* jmp */
864 else if (v
== 0x70) /* jcc */
867 tcc_error("invalid displacement");
870 if (OPCT_IS(pa
->instr_type
, OPC_TEST
))
871 v
+= test_bits
[opcode
- pa
->sym
];
875 op1
= (v
>> 8) & 0xff;
880 /* search which operand will used for modrm */
882 if (OPCT_IS(pa
->instr_type
, OPC_SHIFT
)) {
883 reg
= (opcode
- pa
->sym
) / NBWLX
;
886 } else if (OPCT_IS(pa
->instr_type
, OPC_ARITH
)) {
887 reg
= (opcode
- pa
->sym
) / NBWLX
;
888 } else if (OPCT_IS(pa
->instr_type
, OPC_FARITH
)) {
889 reg
= (opcode
- pa
->sym
) / 6;
891 reg
= (pa
->instr_type
>> OPC_GROUP_SHIFT
) & 7;
895 if (pa
->instr_type
& OPC_MODRM
) {
897 /* A modrm opcode without operands is a special case (e.g. mfence).
898 It has a group and acts as if there's an register operand 0
901 ops
[i
].type
= OP_REG
;
905 /* first look for an ea operand */
906 for(i
= 0;i
< nb_ops
; i
++) {
907 if (op_type
[i
] & OP_EA
)
910 /* then if not found, a register or indirection (shift instructions) */
911 for(i
= 0;i
< nb_ops
; i
++) {
912 if (op_type
[i
] & (OP_REG
| OP_MMX
| OP_SSE
| OP_INDIR
))
916 tcc_error("bad op table");
920 /* if a register is used in another operand then it is
921 used instead of group */
922 for(i
= 0;i
< nb_ops
; i
++) {
924 if (i
!= modrm_index
&&
925 (v
& (OP_REG
| OP_MMX
| OP_SSE
| OP_CR
| OP_TR
| OP_DB
| OP_SEG
))) {
930 pc
= asm_modrm(reg
, &ops
[modrm_index
]);
934 #ifndef TCC_TARGET_X86_64
935 if (!(pa
->instr_type
& OPC_0F
)
936 && (pa
->opcode
== 0x9a || pa
->opcode
== 0xea)) {
937 /* ljmp or lcall kludge */
938 gen_expr32(&ops
[1].e
);
940 tcc_error("cannot relocate");
941 gen_le16(ops
[0].e
.v
);
945 for(i
= 0;i
< nb_ops
; i
++) {
947 if (v
& (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
| OP_IM8S
| OP_ADDR
)) {
948 /* if multiple sizes are given it means we must look
950 if ((v
| OP_IM8
| OP_IM64
) == (OP_IM8
| OP_IM16
| OP_IM32
| OP_IM64
)) {
955 else if (s
== 2 || (v
& OP_IM64
) == 0)
961 if ((v
& (OP_IM8
| OP_IM8S
| OP_IM16
)) && ops
[i
].e
.sym
)
962 tcc_error("cannot relocate");
964 if (v
& (OP_IM8
| OP_IM8S
)) {
966 } else if (v
& OP_IM16
) {
967 gen_le16(ops
[i
].e
.v
);
968 #ifdef TCC_TARGET_X86_64
969 } else if (v
& OP_IM64
) {
970 gen_expr64(&ops
[i
].e
);
972 } else if (pa
->op_type
[i
] == OPT_DISP
|| pa
->op_type
[i
] == OPT_DISP8
) {
973 gen_disp32(&ops
[i
].e
);
975 gen_expr32(&ops
[i
].e
);
980 /* after immediate operands, adjust pc-relative address */
982 add32le(text_section
->data
+ pc
- 4, pc
- ind
);
985 /* return the constraint priority (we allocate first the lowest
986 numbered constraints) */
987 static inline int constraint_priority(const char *str
)
991 /* we take the lowest priority */
1027 tcc_error("unknown constraint '%c'", c
);
1036 static const char *skip_constraint_modifiers(const char *p
)
1038 while (*p
== '=' || *p
== '&' || *p
== '+' || *p
== '%')
1043 #define REG_OUT_MASK 0x01
1044 #define REG_IN_MASK 0x02
1046 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1048 ST_FUNC
void asm_compute_constraints(ASMOperand
*operands
,
1049 int nb_operands
, int nb_outputs
,
1050 const uint8_t *clobber_regs
,
1054 int sorted_op
[MAX_ASM_OPERANDS
];
1055 int i
, j
, k
, p1
, p2
, tmp
, reg
, c
, reg_mask
;
1057 uint8_t regs_allocated
[NB_ASM_REGS
];
1060 for(i
=0;i
<nb_operands
;i
++) {
1062 op
->input_index
= -1;
1068 /* compute constraint priority and evaluate references to output
1069 constraints if input constraints */
1070 for(i
=0;i
<nb_operands
;i
++) {
1072 str
= op
->constraint
;
1073 str
= skip_constraint_modifiers(str
);
1074 if (isnum(*str
) || *str
== '[') {
1075 /* this is a reference to another constraint */
1076 k
= find_constraint(operands
, nb_operands
, str
, NULL
);
1077 if ((unsigned)k
>= i
|| i
< nb_outputs
)
1078 tcc_error("invalid reference in constraint %d ('%s')",
1081 if (operands
[k
].input_index
>= 0)
1082 tcc_error("cannot reference twice the same operand");
1083 operands
[k
].input_index
= i
;
1086 op
->priority
= constraint_priority(str
);
1090 /* sort operands according to their priority */
1091 for(i
=0;i
<nb_operands
;i
++)
1093 for(i
=0;i
<nb_operands
- 1;i
++) {
1094 for(j
=i
+1;j
<nb_operands
;j
++) {
1095 p1
= operands
[sorted_op
[i
]].priority
;
1096 p2
= operands
[sorted_op
[j
]].priority
;
1099 sorted_op
[i
] = sorted_op
[j
];
1105 for(i
= 0;i
< NB_ASM_REGS
; i
++) {
1106 if (clobber_regs
[i
])
1107 regs_allocated
[i
] = REG_IN_MASK
| REG_OUT_MASK
;
1109 regs_allocated
[i
] = 0;
1111 /* esp cannot be used */
1112 regs_allocated
[4] = REG_IN_MASK
| REG_OUT_MASK
;
1113 /* ebp cannot be used yet */
1114 regs_allocated
[5] = REG_IN_MASK
| REG_OUT_MASK
;
1116 /* allocate registers and generate corresponding asm moves */
1117 for(i
=0;i
<nb_operands
;i
++) {
1120 str
= op
->constraint
;
1121 /* no need to allocate references */
1122 if (op
->ref_index
>= 0)
1124 /* select if register is used for output, input or both */
1125 if (op
->input_index
>= 0) {
1126 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1127 } else if (j
< nb_outputs
) {
1128 reg_mask
= REG_OUT_MASK
;
1130 reg_mask
= REG_IN_MASK
;
1141 if (j
>= nb_outputs
)
1142 tcc_error("'%c' modifier can only be applied to outputs", c
);
1143 reg_mask
= REG_IN_MASK
| REG_OUT_MASK
;
1146 /* allocate both eax and edx */
1147 if (is_reg_allocated(TREG_XAX
) ||
1148 is_reg_allocated(TREG_XDX
))
1152 regs_allocated
[TREG_XAX
] |= reg_mask
;
1153 regs_allocated
[TREG_XDX
] |= reg_mask
;
1173 if (is_reg_allocated(reg
))
1177 /* eax, ebx, ecx or edx */
1178 for(reg
= 0; reg
< 4; reg
++) {
1179 if (!is_reg_allocated(reg
))
1184 case 'p': /* A general address, for x86(64) any register is acceptable*/
1185 /* any general register */
1186 for(reg
= 0; reg
< 8; reg
++) {
1187 if (!is_reg_allocated(reg
))
1192 /* now we can reload in the register */
1195 regs_allocated
[reg
] |= reg_mask
;
1199 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
))
1205 if (!((op
->vt
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
))
1210 /* nothing special to do because the operand is already in
1211 memory, except if the pointer itself is stored in a
1212 memory variable (VT_LLOCAL case) */
1213 /* XXX: fix constant case */
1214 /* if it is a reference to a memory zone, it must lie
1215 in a register, so we reserve the register in the
1216 input registers and a load will be generated
1218 if (j
< nb_outputs
|| c
== 'm') {
1219 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1220 /* any general register */
1221 for(reg
= 0; reg
< 8; reg
++) {
1222 if (!(regs_allocated
[reg
] & REG_IN_MASK
))
1227 /* now we can reload in the register */
1228 regs_allocated
[reg
] |= REG_IN_MASK
;
1235 tcc_error("asm constraint %d ('%s') could not be satisfied",
1239 /* if a reference is present for that operand, we assign it too */
1240 if (op
->input_index
>= 0) {
1241 operands
[op
->input_index
].reg
= op
->reg
;
1242 operands
[op
->input_index
].is_llong
= op
->is_llong
;
1246 /* compute out_reg. It is used to store outputs registers to memory
1247 locations references by pointers (VT_LLOCAL case) */
1249 for(i
=0;i
<nb_operands
;i
++) {
1252 (op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1254 for(reg
= 0; reg
< 8; reg
++) {
1255 if (!(regs_allocated
[reg
] & REG_OUT_MASK
))
1258 tcc_error("could not find free output register for reloading");
1265 /* print sorted constraints */
1267 for(i
=0;i
<nb_operands
;i
++) {
1270 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1272 op
->id
? get_tok_str(op
->id
, NULL
) : "",
1278 printf("out_reg=%d\n", *pout_reg
);
1282 ST_FUNC
void subst_asm_operand(CString
*add_str
,
1283 SValue
*sv
, int modifier
)
1285 int r
, reg
, size
, val
;
1289 if ((r
& VT_VALMASK
) == VT_CONST
) {
1290 if (!(r
& VT_LVAL
) && modifier
!= 'c' && modifier
!= 'n' &&
1292 cstr_ccat(add_str
, '$');
1294 cstr_cat(add_str
, get_tok_str(sv
->sym
->v
, NULL
), -1);
1295 if ((uint32_t)sv
->c
.i
== 0)
1297 cstr_ccat(add_str
, '+');
1300 if (modifier
== 'n')
1302 snprintf(buf
, sizeof(buf
), "%d", (int)sv
->c
.i
);
1303 cstr_cat(add_str
, buf
, -1);
1305 #ifdef TCC_TARGET_X86_64
1307 cstr_cat(add_str
, "(%rip)", -1);
1309 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
1310 #ifdef TCC_TARGET_X86_64
1311 snprintf(buf
, sizeof(buf
), "%d(%%rbp)", (int)sv
->c
.i
);
1313 snprintf(buf
, sizeof(buf
), "%d(%%ebp)", (int)sv
->c
.i
);
1315 cstr_cat(add_str
, buf
, -1);
1316 } else if (r
& VT_LVAL
) {
1317 reg
= r
& VT_VALMASK
;
1318 if (reg
>= VT_CONST
)
1319 tcc_error("internal compiler error");
1320 snprintf(buf
, sizeof(buf
), "(%%%s)",
1321 #ifdef TCC_TARGET_X86_64
1322 get_tok_str(TOK_ASM_rax
+ reg
, NULL
)
1324 get_tok_str(TOK_ASM_eax
+ reg
, NULL
)
1327 cstr_cat(add_str
, buf
, -1);
1330 reg
= r
& VT_VALMASK
;
1331 if (reg
>= VT_CONST
)
1332 tcc_error("internal compiler error");
1334 /* choose register operand size */
1335 if ((sv
->type
.t
& VT_BTYPE
) == VT_BYTE
)
1337 else if ((sv
->type
.t
& VT_BTYPE
) == VT_SHORT
)
1339 #ifdef TCC_TARGET_X86_64
1340 else if ((sv
->type
.t
& VT_BTYPE
) == VT_LLONG
)
1345 if (size
== 1 && reg
>= 4)
1348 if (modifier
== 'b') {
1350 tcc_error("cannot use byte register");
1352 } else if (modifier
== 'h') {
1354 tcc_error("cannot use byte register");
1356 } else if (modifier
== 'w') {
1358 } else if (modifier
== 'k') {
1360 #ifdef TCC_TARGET_X86_64
1361 } else if (modifier
== 'q') {
1368 reg
= TOK_ASM_ah
+ reg
;
1371 reg
= TOK_ASM_al
+ reg
;
1374 reg
= TOK_ASM_ax
+ reg
;
1377 reg
= TOK_ASM_eax
+ reg
;
1379 #ifdef TCC_TARGET_X86_64
1381 reg
= TOK_ASM_rax
+ reg
;
1385 snprintf(buf
, sizeof(buf
), "%%%s", get_tok_str(reg
, NULL
));
1386 cstr_cat(add_str
, buf
, -1);
1390 /* generate prolog and epilog code for asm statement */
1391 ST_FUNC
void asm_gen_code(ASMOperand
*operands
, int nb_operands
,
1392 int nb_outputs
, int is_output
,
1393 uint8_t *clobber_regs
,
1396 uint8_t regs_allocated
[NB_ASM_REGS
];
1399 static uint8_t reg_saved
[NB_SAVED_REGS
] = { 3, 6, 7 };
1401 /* mark all used registers */
1402 memcpy(regs_allocated
, clobber_regs
, sizeof(regs_allocated
));
1403 for(i
= 0; i
< nb_operands
;i
++) {
1406 regs_allocated
[op
->reg
] = 1;
1409 /* generate reg save code */
1410 for(i
= 0; i
< NB_SAVED_REGS
; i
++) {
1412 if (regs_allocated
[reg
]) {
1417 /* generate load code */
1418 for(i
= 0; i
< nb_operands
; i
++) {
1421 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
&&
1423 /* memory reference case (for both input and
1427 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
| VT_LVAL
;
1430 } else if (i
>= nb_outputs
|| op
->is_rw
) {
1431 /* load value in register */
1432 load(op
->reg
, op
->vt
);
1437 load(TREG_XDX
, &sv
);
1443 /* generate save code */
1444 for(i
= 0 ; i
< nb_outputs
; i
++) {
1447 if ((op
->vt
->r
& VT_VALMASK
) == VT_LLOCAL
) {
1448 if (!op
->is_memory
) {
1451 sv
.r
= (sv
.r
& ~VT_VALMASK
) | VT_LOCAL
;
1454 sv
.r
= (sv
.r
& ~VT_VALMASK
) | out_reg
;
1455 store(op
->reg
, &sv
);
1458 store(op
->reg
, op
->vt
);
1463 store(TREG_XDX
, &sv
);
1468 /* generate reg restore code */
1469 for(i
= NB_SAVED_REGS
- 1; i
>= 0; i
--) {
1471 if (regs_allocated
[reg
]) {
1478 ST_FUNC
void asm_clobber(uint8_t *clobber_regs
, const char *str
)
1483 if (!strcmp(str
, "memory") ||
1486 ts
= tok_alloc(str
, strlen(str
));
1488 if (reg
>= TOK_ASM_eax
&& reg
<= TOK_ASM_edi
) {
1490 } else if (reg
>= TOK_ASM_ax
&& reg
<= TOK_ASM_di
) {
1492 #ifdef TCC_TARGET_X86_64
1493 } else if (reg
>= TOK_ASM_rax
&& reg
<= TOK_ASM_rdi
) {
1495 } else if (1 && str
[0] == 'r' &&
1496 (((str
[1] == '8' || str
[1] == '9') && str
[2] == 0) ||
1497 (str
[1] == '1' && str
[2] >= '0' && str
[2] <= '5' &&
1499 /* Do nothing for now. We can't parse the high registers. */
1503 tcc_error("invalid clobber register '%s'", str
);
1505 clobber_regs
[reg
] = 1;