1 #ifdef TARGET_DEFS_ONLY
3 // Number of registers available to allocator:
4 #define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
6 #define TREG_R(x) (x) // x = 0..7
7 #define TREG_F(x) (x + 8) // x = 0..7
9 // Register classes sorted from more general to more precise:
10 #define RC_INT (1 << 0)
11 #define RC_FLOAT (1 << 1)
12 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
13 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
15 #define RC_IRET (RC_R(0)) // int return register class
16 #define RC_IRE2 (RC_R(1)) // int 2nd return register class
17 #define RC_FRET (RC_F(0)) // float return register class
19 #define REG_IRET (TREG_R(0)) // int return register number
20 #define REG_IRE2 (TREG_R(1)) // int 2nd return register number
21 #define REG_FRET (TREG_F(0)) // float return register number
25 #define LDOUBLE_SIZE 16
26 #define LDOUBLE_ALIGN 16
30 #define CHAR_IS_UNSIGNED
42 ST_DATA
const int reg_classes
[NB_REGS
] = {
64 static int ireg(int r
)
70 assert(r
>= 0 && r
< 8);
71 return r
+ 10; // tccrX --> aX == x(10+X)
74 static int is_ireg(int r
)
76 return (unsigned)r
< 8 || r
== TREG_RA
|| r
== TREG_SP
;
79 static int freg(int r
)
81 assert(r
>= 8 && r
< 16);
82 return r
- 8 + 10; // tccfX --> faX == f(10+X)
85 static int is_freg(int r
)
87 return r
>= 8 && r
< 16;
90 ST_FUNC
void o(unsigned int c
)
95 if (ind1
> cur_text_section
->data_allocated
)
96 section_realloc(cur_text_section
, ind1
);
97 write32le(cur_text_section
->data
+ ind
, c
);
101 static void EIu(uint32_t opcode
, uint32_t func3
,
102 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
104 o(opcode
| (func3
<< 12) | (rd
<< 7) | (rs1
<< 15) | (imm
<< 20));
107 static void ER(uint32_t opcode
, uint32_t func3
,
108 uint32_t rd
, uint32_t rs1
, uint32_t rs2
, uint32_t func7
)
110 o(opcode
| func3
<< 12 | rd
<< 7 | rs1
<< 15 | rs2
<< 20 | func7
<< 25);
113 static void EI(uint32_t opcode
, uint32_t func3
,
114 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
116 assert(! ((imm
+ (1 << 11)) >> 12));
117 EIu(opcode
, func3
, rd
, rs1
, imm
);
120 static void ES(uint32_t opcode
, uint32_t func3
,
121 uint32_t rs1
, uint32_t rs2
, uint32_t imm
)
123 assert(! ((imm
+ (1 << 11)) >> 12));
124 o(opcode
| (func3
<< 12) | ((imm
& 0x1f) << 7) | (rs1
<< 15)
125 | (rs2
<< 20) | ((imm
>> 5) << 25));
128 // Patch all branches in list pointed to by t to branch to a:
129 ST_FUNC
void gsym_addr(int t_
, int a_
)
134 unsigned char *ptr
= cur_text_section
->data
+ t
;
135 uint32_t next
= read32le(ptr
);
136 uint32_t r
= a
- t
, imm
;
137 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
138 tcc_error("out-of-range branch chain");
139 imm
= (((r
>> 12) & 0xff) << 12)
140 | (((r
>> 11) & 1) << 20)
141 | (((r
>> 1) & 0x3ff) << 21)
142 | (((r
>> 20) & 1) << 31);
143 write32le(ptr
, r
== 4 ? 0x33 : 0x6f | imm
); // nop || j imm
148 static int load_symofs(int r
, SValue
*sv
, int forstore
)
152 int fc
= sv
->c
.i
, v
= sv
->r
& VT_VALMASK
;
153 if (sv
->r
& VT_SYM
) {
154 assert(v
== VT_CONST
);
155 if (sv
->sym
->type
.t
& VT_STATIC
) { // XXX do this per linker relax
156 greloca(cur_text_section
, sv
->sym
, ind
,
157 R_RISCV_PCREL_HI20
, sv
->c
.i
);
160 if (((unsigned)fc
+ (1 << 11)) >> 12)
161 tcc_error("unimp: large addend for global address (0x%llx)", sv
->c
.i
);
162 greloca(cur_text_section
, sv
->sym
, ind
,
163 R_RISCV_GOT_HI20
, 0);
167 label
.v
= tok_alloc(".L0 ", 4)->tok
;
168 label
.type
.t
= VT_VOID
| VT_STATIC
;
170 label
.c
= 0; /* force new local ELF symbol */
171 put_extern_sym(&label
, cur_text_section
, ind
, 0);
172 rr
= is_ireg(r
) ? ireg(r
) : 5;
173 o(0x17 | (rr
<< 7)); // auipc RR, 0 %pcrel_hi(sym)+addend
174 greloca(cur_text_section
, &label
, ind
,
176 ? R_RISCV_PCREL_LO12_I
: R_RISCV_PCREL_LO12_S
, 0);
178 EI(0x03, 3, rr
, rr
, 0); // ld RR, 0(RR)
180 } else if (v
== VT_LOCAL
|| v
== VT_LLOCAL
) {
183 tcc_error("unimp: store(giant local off) (0x%llx)", (long long)sv
->c
.i
);
184 if (((unsigned)fc
+ (1 << 11)) >> 12) {
185 rr
= is_ireg(r
) ? ireg(r
) : 5; // t0
186 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
187 ER(0x33, 0, rr
, rr
, 8, 0); // add RR, RR, s0
188 sv
->c
.i
= fc
<< 20 >> 20;
195 ST_FUNC
void load(int r
, SValue
*sv
)
198 int v
= fr
& VT_VALMASK
;
199 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
201 int bt
= sv
->type
.t
& VT_BTYPE
;
202 int align
, size
= type_size(&sv
->type
, &align
);
204 int func3
, opcode
= is_freg(r
) ? 0x07 : 0x03, br
;
205 assert (!is_freg(r
) || bt
== VT_FLOAT
|| bt
== VT_DOUBLE
);
206 if (bt
== VT_FUNC
) /* XXX should be done in generic code */
208 func3
= size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3;
209 if (size
< 4 && !is_float(sv
->type
.t
) && (sv
->type
.t
& VT_UNSIGNED
))
211 if (v
== VT_LOCAL
|| (fr
& VT_SYM
)) {
212 br
= load_symofs(r
, sv
, 0);
214 } else if (v
< VT_CONST
) {
216 /*if (((unsigned)fc + (1 << 11)) >> 12)
217 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
218 fc
= 0; // XXX store ofs in LVAL(reg)
219 } else if (v
== VT_LLOCAL
) {
220 br
= load_symofs(r
, sv
, 0);
222 EI(0x03, 3, rr
, br
, fc
); // ld RR, fc(BR)
226 tcc_error("unimp: load(non-local lval)");
228 EI(opcode
, func3
, rr
, br
, fc
); // l[bhwd][u] / fl[wd] RR, fc(BR)
229 } else if (v
== VT_CONST
) {
230 int rb
= 0, do32bit
= 8, zext
= 0;
231 assert((!is_float(sv
->type
.t
) && is_ireg(r
)) || bt
== VT_LDOUBLE
);
233 rb
= load_symofs(r
, sv
, 0);
237 if (is_float(sv
->type
.t
) && bt
!= VT_LDOUBLE
)
238 tcc_error("unimp: load(float)");
240 int64_t si
= sv
->c
.i
;
247 o(0x37 | (rr
<< 7) | (((pi
+ 0x800) & 0xfffff000))); // lui RR, up(up(fc))
248 EI(0x13, 0, rr
, rr
, (int)pi
<< 20 >> 20); // addi RR, RR, lo(up(fc))
249 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
250 EI(0x13, 0, rr
, rr
, (fc
+ (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
251 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
253 EI(0x13, 0, rr
, rr
, fc
>> 8); // addi RR, RR, lo1(lo(fc))
254 EI(0x13, 1, rr
, rr
, 8); // slli RR, RR, 8
258 } else if (bt
== VT_LLONG
) {
259 /* A 32bit unsigned constant for a 64bit type.
260 lui always sign extends, so we need to do an explicit zext.*/
264 if (((unsigned)fc
+ (1 << 11)) >> 12)
265 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)), rb
= rr
; //lui RR, upper(fc)
266 if (fc
|| (rr
!= rb
) || do32bit
|| (fr
& VT_SYM
))
267 EI(0x13 | do32bit
, 0, rr
, rb
, fc
<< 20 >> 20); // addi[w] R, x0|R, FC
269 EI(0x13, 1, rr
, rr
, 32); // slli RR, RR, 32
270 EI(0x13, 5, rr
, rr
, 32); // srli RR, RR, 32
272 } else if (v
== VT_LOCAL
) {
273 int br
= load_symofs(r
, sv
, 0);
276 EI(0x13, 0, rr
, br
, fc
); // addi R, s0, FC
277 } else if (v
< VT_CONST
) { /* reg-reg */
278 //assert(!fc); XXX support offseted regs
279 if (is_freg(r
) && is_freg(v
))
280 ER(0x53, 0, rr
, freg(v
), freg(v
), bt
== VT_DOUBLE
? 0x11 : 0x10); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
281 else if (is_ireg(r
) && is_ireg(v
))
282 EI(0x13, 0, rr
, ireg(v
), 0); // addi RR, V, 0 == mv RR, V
284 int func7
= is_ireg(r
) ? 0x70 : 0x78;
287 assert(size
== 4 || size
== 8);
288 o(0x53 | (rr
<< 7) | ((is_freg(v
) ? freg(v
) : ireg(v
)) << 15)
289 | (func7
<< 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
291 } else if (v
== VT_CMP
) {
292 int op
= vtop
->cmp_op
;
293 int a
= vtop
->cmp_r
& 0xff;
294 int b
= (vtop
->cmp_r
>> 8) & 0xff;
305 if (op
& 1) { // remove [U]GE,GT
309 if ((op
& 7) == 6) { // [U]LE
310 int t
= a
; a
= b
; b
= t
;
313 ER(0x33, (op
> TOK_UGT
) ? 2 : 3, rr
, a
, b
, 0); // slt[u] d, a, b
315 EI(0x13, 4, rr
, rr
, 1); // xori d, d, 1
320 ER(0x33, 0, rr
, a
, b
, 0x20); // sub d, a, b
322 ER(0x33, 3, rr
, 0, rr
, 0); // sltu d, x0, d == snez d,d
324 EI(0x13, 3, rr
, rr
, 1); // sltiu d, d, 1 == seqz d,d
327 } else if ((v
& ~1) == VT_JMP
) {
330 EI(0x13, 0, rr
, 0, t
); // addi RR, x0, t
333 EI(0x13, 0, rr
, 0, t
^ 1); // addi RR, x0, !t
335 tcc_error("unimp: load(non-const)");
338 ST_FUNC
void store(int r
, SValue
*sv
)
340 int fr
= sv
->r
& VT_VALMASK
;
341 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
), ptrreg
;
343 int bt
= sv
->type
.t
& VT_BTYPE
;
344 int align
, size
= type_size(&sv
->type
, &align
);
345 assert(!is_float(bt
) || is_freg(r
) || bt
== VT_LDOUBLE
);
346 /* long doubles are in two integer registers, but the load/store
347 primitives only deal with one, so do as if it's one reg. */
348 if (bt
== VT_LDOUBLE
)
351 tcc_error("unimp: store(struct)");
353 tcc_error("unimp: large sized store");
354 assert(sv
->r
& VT_LVAL
);
355 if (fr
== VT_LOCAL
|| (sv
->r
& VT_SYM
)) {
356 ptrreg
= load_symofs(-1, sv
, 1);
358 } else if (fr
< VT_CONST
) {
360 /*if (((unsigned)fc + (1 << 11)) >> 12)
361 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
362 fc
= 0; // XXX support offsets regs
364 tcc_error("implement me: %s(!local)", __FUNCTION__
);
365 ES(is_freg(r
) ? 0x27 : 0x23, // fs... | s...
366 size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3, // ... [wd] | [bhwd]
367 ptrreg
, rr
, fc
); // RR, fc(base)
370 static void gcall_or_jmp(int docall
)
372 int tr
= docall
? 1 : 5; // ra or t0
373 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
374 ((vtop
->r
& VT_SYM
) && vtop
->c
.i
== (int)vtop
->c
.i
)) {
375 /* constant symbolic case -> simple relocation */
376 greloca(cur_text_section
, vtop
->sym
, ind
,
377 R_RISCV_CALL_PLT
, (int)vtop
->c
.i
);
378 o(0x17 | (tr
<< 7)); // auipc TR, 0 %call(func)
379 EI(0x67, 0, tr
, tr
, 0);// jalr TR, r(TR)
380 } else if (vtop
->r
< VT_CONST
) {
381 int r
= ireg(vtop
->r
);
382 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
387 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
391 static void reg_pass_rec(CType
*type
, int *rc
, int *fieldofs
, int ofs
)
393 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
395 if (type
->ref
->type
.t
== VT_UNION
)
397 else for (f
= type
->ref
->next
; f
; f
= f
->next
)
398 reg_pass_rec(&f
->type
, rc
, fieldofs
, ofs
+ f
->c
);
399 } else if (type
->t
& VT_ARRAY
) {
400 if (type
->ref
->c
< 0 || type
->ref
->c
> 2)
403 int a
, sz
= type_size(&type
->ref
->type
, &a
);
404 reg_pass_rec(&type
->ref
->type
, rc
, fieldofs
, ofs
);
405 if (rc
[0] > 2 || (rc
[0] == 2 && type
->ref
->c
> 1))
407 else if (type
->ref
->c
== 2 && rc
[0] && rc
[1] == RC_FLOAT
) {
408 rc
[++rc
[0]] = RC_FLOAT
;
409 fieldofs
[rc
[0]] = ((ofs
+ sz
) << 4)
410 | (type
->ref
->type
.t
& VT_BTYPE
);
411 } else if (type
->ref
->c
== 2)
414 } else if (rc
[0] == 2 || rc
[0] < 0 || (type
->t
& VT_BTYPE
) == VT_LDOUBLE
)
416 else if (!rc
[0] || rc
[1] == RC_FLOAT
|| is_float(type
->t
)) {
417 rc
[++rc
[0]] = is_float(type
->t
) ? RC_FLOAT
: RC_INT
;
418 fieldofs
[rc
[0]] = (ofs
<< 4) | (type
->t
& VT_BTYPE
);
423 static void reg_pass(CType
*type
, int *prc
, int *fieldofs
, int named
)
426 reg_pass_rec(type
, prc
, fieldofs
, 0);
427 if (prc
[0] <= 0 || !named
) {
428 int align
, size
= type_size(type
, &align
);
429 prc
[0] = (size
+ 7) >> 3;
430 prc
[1] = prc
[2] = RC_INT
;
431 fieldofs
[1] = (0 << 4) | (size
<= 1 ? VT_BYTE
: size
<= 2 ? VT_SHORT
: size
<= 4 ? VT_INT
: VT_LLONG
);
432 fieldofs
[2] = (8 << 4) | (size
<= 9 ? VT_BYTE
: size
<= 10 ? VT_SHORT
: size
<= 12 ? VT_INT
: VT_LLONG
);
436 ST_FUNC
void gfunc_call(int nb_args
)
438 int i
, align
, size
, areg
[2];
439 int info
[nb_args
? nb_args
: 1];
440 int stack_adj
= 0, tempspace
= 0, ofs
, splitofs
= 0;
443 areg
[0] = 0; /* int arg regs */
444 areg
[1] = 8; /* float arg regs */
445 sa
= vtop
[-nb_args
].type
.ref
->next
;
446 for (i
= 0; i
< nb_args
; i
++) {
447 int nregs
, byref
= 0, tempofs
;
448 int prc
[3], fieldofs
[3];
449 sv
= &vtop
[1 + i
- nb_args
];
450 sv
->type
.t
&= ~VT_ARRAY
; // XXX this should be done in tccgen.c
451 size
= type_size(&sv
->type
, &align
);
455 tempspace
= (tempspace
+ align
- 1) & -align
;
459 byref
= 64 | (tempofs
<< 7);
461 reg_pass(&sv
->type
, prc
, fieldofs
, sa
!= 0);
462 if (!sa
&& align
== 2*XLEN
&& size
<= 2*XLEN
)
463 areg
[0] = (areg
[0] + 1) & ~1;
465 if ((prc
[1] == RC_INT
&& areg
[0] >= 8)
466 || (prc
[1] == RC_FLOAT
&& areg
[1] >= 16)
467 || (nregs
== 2 && prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
469 || (nregs
== 2 && prc
[1] != prc
[2]
470 && (areg
[1] >= 16 || areg
[0] >= 8))) {
474 stack_adj
+= (size
+ align
- 1) & -align
;
475 if (!sa
) /* one vararg on stack forces the rest on stack */
476 areg
[0] = 8, areg
[1] = 16;
478 info
[i
] = areg
[prc
[1] - 1]++;
480 info
[i
] |= (fieldofs
[1] & VT_BTYPE
) << 12;
481 assert(!(fieldofs
[1] >> 4));
483 if (prc
[2] == RC_FLOAT
|| areg
[0] < 8)
484 info
[i
] |= (1 + areg
[prc
[2] - 1]++) << 7;
490 assert((fieldofs
[2] >> 4) < 2048);
491 info
[i
] |= fieldofs
[2] << (12 + 4); // includes offset
499 stack_adj
= (stack_adj
+ 15) & -16;
500 tempspace
= (tempspace
+ 15) & -16;
501 if (stack_adj
+ tempspace
) {
502 EI(0x13, 0, 2, 2, -(stack_adj
+ tempspace
)); // addi sp, sp, -adj
503 for (i
= ofs
= 0; i
< nb_args
; i
++) {
504 if (info
[i
] & (64 | 32)) {
506 size
= type_size(&vtop
->type
, &align
);
508 vset(&char_pointer_type
, TREG_SP
, 0);
509 vpushi(stack_adj
+ (info
[i
] >> 7));
511 vpushv(vtop
); // this replaces the old argument
514 vtop
->type
= vtop
[-1].type
;
523 /* Once we support offseted regs we can do this:
524 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
525 to construct the lvalue for the outgoing stack slot,
526 until then we have to jump through hoops. */
527 vset(&char_pointer_type
, TREG_SP
, 0);
528 ofs
= (ofs
+ align
- 1) & -align
;
532 vtop
->type
= vtop
[-1].type
;
535 vtop
->r
= vtop
->r2
= VT_CONST
; // this arg is done
539 } else if (info
[i
] & 16) {
546 for (i
= 0; i
< nb_args
; i
++) {
547 int ii
= info
[nb_args
- 1 - i
], r
= ii
, r2
= r
;
552 r2
= r2
& 64 ? 0 : (r2
>> 7) & 31;
555 origtype
= vtop
->type
;
556 size
= type_size(&vtop
->type
, &align
);
557 loadt
= vtop
->type
.t
& VT_BTYPE
;
558 if (loadt
== VT_STRUCT
) {
559 loadt
= (ii
>> 12) & VT_BTYPE
;
561 if (info
[nb_args
- 1 - i
] & 16) {
565 if (loadt
== VT_LDOUBLE
) {
572 vtop
->type
.t
= loadt
| (vtop
->type
.t
& VT_UNSIGNED
);
573 gv(r
< 8 ? RC_R(r
) : RC_F(r
- 8));
574 vtop
->type
= origtype
;
576 if (r2
&& loadt
!= VT_LDOUBLE
) {
578 assert(r2
< 16 || r2
== TREG_RA
);
581 vtop
->type
= char_pointer_type
;
585 vtop
->type
= origtype
;
586 loadt
= vtop
->type
.t
& VT_BTYPE
;
587 if (loadt
== VT_STRUCT
) {
588 loadt
= (ii
>> 16) & VT_BTYPE
;
590 save_reg_upstack(r2
, 1);
591 vtop
->type
.t
= loadt
| (vtop
->type
.t
& VT_UNSIGNED
);
593 assert(r2
< VT_CONST
);
597 if (info
[nb_args
- 1 - i
] & 16) {
598 ES(0x23, 3, 2, ireg(vtop
->r2
), splitofs
); // sd t0, ofs(sp)
600 } else if (loadt
== VT_LDOUBLE
&& vtop
->r2
!= r2
) {
601 assert(vtop
->r2
<= 7 && r2
<= 7);
602 /* XXX we'd like to have 'gv' move directly into
603 the right class instead of us fixing it up. */
604 EI(0x13, 0, ireg(r2
), ireg(vtop
->r2
), 0); // mv Ra+1, RR2
611 save_regs(nb_args
+ 1);
614 if (stack_adj
+ tempspace
)
615 EI(0x13, 0, 2, 2, stack_adj
+ tempspace
); // addi sp, sp, adj
618 static int func_sub_sp_offset
, num_va_regs
, func_va_list_ofs
;
620 ST_FUNC
void gfunc_prolog(Sym
*func_sym
)
622 CType
*func_type
= &func_sym
->type
;
623 int i
, addr
, align
, size
;
629 sym
= func_type
->ref
;
631 loc
= -16; // for ra and s0
632 func_sub_sp_offset
= ind
;
635 areg
[0] = 0, areg
[1] = 0;
637 /* if the function returns by reference, then add an
638 implicit pointer parameter */
639 size
= type_size(&func_vt
, &align
);
640 if (size
> 2 * XLEN
) {
643 ES(0x23, 3, 8, 10 + areg
[0]++, loc
); // sd a0, loc(s0)
645 /* define parameters */
646 while ((sym
= sym
->next
) != NULL
) {
649 int prc
[3], fieldofs
[3];
651 size
= type_size(type
, &align
);
652 if (size
> 2 * XLEN
) {
653 type
= &char_pointer_type
;
654 size
= align
= byref
= 8;
656 reg_pass(type
, prc
, fieldofs
, 1);
658 if (areg
[prc
[1] - 1] >= 8
660 && ((prc
[1] == RC_FLOAT
&& prc
[2] == RC_FLOAT
&& areg
[1] >= 7)
661 || (prc
[1] != prc
[2] && (areg
[1] >= 8 || areg
[0] >= 8))))) {
664 addr
= (addr
+ align
- 1) & -align
;
668 loc
-= regcount
* 8; // XXX could reserve only 'size' bytes
670 for (i
= 0; i
< regcount
; i
++) {
671 if (areg
[prc
[1+i
] - 1] >= 8) {
672 assert(i
== 1 && regcount
== 2 && !(addr
& 7));
673 EI(0x03, 3, 5, 8, addr
); // ld t0, addr(s0)
675 ES(0x23, 3, 8, 5, loc
+ i
*8); // sd t0, loc(s0)
676 } else if (prc
[1+i
] == RC_FLOAT
) {
677 ES(0x27, (size
/ regcount
) == 4 ? 2 : 3, 8, 10 + areg
[1]++, loc
+ (fieldofs
[i
+1] >> 4)); // fs[wd] FAi, loc(s0)
679 ES(0x23, 3, 8, 10 + areg
[0]++, loc
+ i
*8); // sd aX, loc(s0) // XXX
683 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
684 (byref
? VT_LLOCAL
: VT_LOCAL
) | VT_LVAL
,
687 func_va_list_ofs
= addr
;
689 if (func_type
->ref
->f
.func_type
== FUNC_ELLIPSIS
) {
690 for (; areg
[0] < 8; areg
[0]++) {
692 ES(0x23, 3, 8, 10 + areg
[0], -8 + num_va_regs
* 8); // sd aX, loc(s0)
697 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
698 int *ret_align
, int *regsize
)
700 int align
, size
= type_size(vt
, &align
), nregs
;
701 int prc
[3], fieldofs
[3];
706 reg_pass(vt
, prc
, fieldofs
, 1);
708 if (nregs
== 2 && prc
[1] != prc
[2])
709 return -1; /* generic code can't deal with this case */
710 if (prc
[1] == RC_FLOAT
) {
711 *regsize
= size
/ nregs
;
713 ret
->t
= fieldofs
[1] & VT_BTYPE
;
717 ST_FUNC
void arch_transfer_ret_regs(int aftercall
)
719 int prc
[3], fieldofs
[3];
720 reg_pass(&vtop
->type
, prc
, fieldofs
, 1);
721 assert(prc
[0] == 2 && prc
[1] != prc
[2] && !(fieldofs
[1] >> 4));
722 assert(vtop
->r
== (VT_LOCAL
| VT_LVAL
));
724 vtop
->type
.t
= fieldofs
[1] & VT_BTYPE
;
725 (aftercall
? store
: load
)(prc
[1] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
726 vtop
->c
.i
+= fieldofs
[2] >> 4;
727 vtop
->type
.t
= fieldofs
[2] & VT_BTYPE
;
728 (aftercall
? store
: load
)(prc
[2] == RC_INT
? REG_IRET
: REG_FRET
, vtop
);
732 ST_FUNC
void gfunc_epilog(void)
734 int v
, saved_ind
, d
, large_ofs_ind
;
736 loc
= (loc
- num_va_regs
* 8);
737 d
= v
= (-loc
+ 15) & -16;
739 if (v
>= (1 << 11)) {
741 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
742 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
743 ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
745 EI(0x03, 3, 1, 2, d
- 8 - num_va_regs
* 8); // ld ra, v-8(sp)
746 EI(0x03, 3, 8, 2, d
- 16 - num_va_regs
* 8); // ld s0, v-16(sp)
747 EI(0x13, 0, 2, 2, d
); // addi sp, sp, v
748 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
750 if (v
>= (1 << 11)) {
751 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
752 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
753 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
754 ER(0x33, 0, 2, 2, 5, 0x20); // sub sp, sp, t0
755 gjmp_addr(func_sub_sp_offset
+ 5*4);
759 ind
= func_sub_sp_offset
;
760 EI(0x13, 0, 2, 2, -d
); // addi sp, sp, -d
761 ES(0x23, 3, 2, 1, d
- 8 - num_va_regs
* 8); // sd ra, d-8(sp)
762 ES(0x23, 3, 2, 8, d
- 16 - num_va_regs
* 8); // sd s0, d-16(sp)
764 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
766 gjmp_addr(large_ofs_ind
);
767 if ((ind
- func_sub_sp_offset
) != 5*4)
768 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
772 ST_FUNC
void gen_va_start(void)
775 vset(&char_pointer_type
, VT_LOCAL
, func_va_list_ofs
);
778 ST_FUNC
void gen_fill_nops(int bytes
)
781 tcc_error("alignment of code section not multiple of 4");
783 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
788 // Generate forward branch to label:
789 ST_FUNC
int gjmp(int t
)
797 // Generate branch to known address:
798 ST_FUNC
void gjmp_addr(int a
)
800 uint32_t r
= a
- ind
, imm
;
801 if ((r
+ (1 << 21)) & ~((1U << 22) - 2)) {
802 o(0x17 | (5 << 7) | (((r
+ 0x800) & 0xfffff000))); // lui RR, up(r)
803 r
= (int)r
<< 20 >> 20;
804 EI(0x67, 0, 0, 5, r
); // jalr x0, r(t0)
806 imm
= (((r
>> 12) & 0xff) << 12)
807 | (((r
>> 11) & 1) << 20)
808 | (((r
>> 1) & 0x3ff) << 21)
809 | (((r
>> 20) & 1) << 31);
810 o(0x6f | imm
); // jal x0, imm == j imm
814 ST_FUNC
int gjmp_cond(int op
, int t
)
817 int a
= vtop
->cmp_r
& 0xff;
818 int b
= (vtop
->cmp_r
>> 8) & 0xff;
820 case TOK_ULT
: op
= 6; break;
821 case TOK_UGE
: op
= 7; break;
822 case TOK_ULE
: op
= 7; tmp
= a
; a
= b
; b
= tmp
; break;
823 case TOK_UGT
: op
= 6; tmp
= a
; a
= b
; b
= tmp
; break;
824 case TOK_LT
: op
= 4; break;
825 case TOK_GE
: op
= 5; break;
826 case TOK_LE
: op
= 5; tmp
= a
; a
= b
; b
= tmp
; break;
827 case TOK_GT
: op
= 4; tmp
= a
; a
= b
; b
= tmp
; break;
828 case TOK_NE
: op
= 1; break;
829 case TOK_EQ
: op
= 0; break;
831 o(0x63 | (op
^ 1) << 12 | a
<< 15 | b
<< 20 | 8 << 7); // bOP a,b,+4
835 ST_FUNC
int gjmp_append(int n
, int t
)
838 /* insert jump list n into t */
841 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
849 static void gen_opil(int op
, int ll
)
854 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
) {
856 if (fc
== vtop
->c
.i
&& !(((unsigned)fc
+ (1 << 11)) >> 12)) {
867 if (fc
<= -(1 << 11))
871 func3
= 0; // addi d, a, fc
873 EI(0x13 | cll
, func3
, ireg(d
), a
, fc
);
875 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
877 vtop
->cmp_r
= ireg(d
) | 0 << 8;
882 if (fc
>= (1 << 11) - 1)
885 case TOK_LT
: func3
= 2; goto do_cop
; // slti d, a, fc
887 if (fc
>= (1 << 11) - 1)
890 case TOK_ULT
: func3
= 3; goto do_cop
; // sltiu d, a, fc
891 case '^': func3
= 4; goto do_cop
; // xori d, a, fc
892 case '|': func3
= 6; goto do_cop
; // ori d, a, fc
893 case '&': func3
= 7; goto do_cop
; // andi d, a, fc
894 case TOK_SHL
: func3
= 1; fc
&= 63; goto do_cop
; // slli d, a, fc
895 case TOK_SHR
: func3
= 5; cll
= ll
; fc
&= 63; goto do_cop
; // srli d, a, fc
896 case TOK_SAR
: func3
= 5; cll
= ll
; fc
= 1024 | (fc
& 63); goto do_cop
;
902 gen_opil(op
- 1, ll
);
909 gen_opil('-', ll
), a
= ireg(vtop
++->r
);
912 vtop
->cmp_r
= a
| 0 << 8;
918 a
= ireg(vtop
[-1].r
);
927 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
929 vtop
->cmp_r
= a
| b
<< 8;
932 tcc_error("implement me: %s(%s)", __FUNCTION__
, get_tok_str(op
, NULL
));
936 ER(0x33, 0, d
, a
, b
, 0); // add d, a, b
939 ER(0x33, 0, d
, a
, b
, 0x20); // sub d, a, b
942 ER(0x33 | ll
, 5, d
, a
, b
, 0x20); // sra d, a, b
945 ER(0x33 | ll
, 5, d
, a
, b
, 0); // srl d, a, b
948 ER(0x33, 1, d
, a
, b
, 0); // sll d, a, b
951 ER(0x33, 0, d
, a
, b
, 1); // mul d, a, b
954 ER(0x33, 4, d
, a
, b
, 1); // div d, a, b
957 ER(0x33, 7, d
, a
, b
, 0); // and d, a, b
960 ER(0x33, 4, d
, a
, b
, 0); // xor d, a, b
963 ER(0x33, 6, d
, a
, b
, 0); // or d, a, b
966 ER(0x33, 6, d
, a
, b
, 1); // rem d, a, b
969 ER(0x33, 7, d
, a
, b
, 1); // remu d, a, b
973 ER(0x33, 5, d
, a
, b
, 1); // divu d, a, b
978 ST_FUNC
void gen_opi(int op
)
983 ST_FUNC
void gen_opl(int op
)
988 ST_FUNC
void gen_opf(int op
)
990 int rs1
, rs2
, rd
, dbl
, invert
;
991 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
992 CType type
= vtop
[0].type
;
996 case '*': func
= TOK___multf3
; break;
997 case '+': func
= TOK___addtf3
; break;
998 case '-': func
= TOK___subtf3
; break;
999 case '/': func
= TOK___divtf3
; break;
1000 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
1001 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
1002 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
1003 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
1004 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
1005 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
1006 default: assert(0); break;
1008 vpush_global_sym(&func_old_type
, func
);
1013 vtop
->r2
= cond
< 0 ? TREG_R(1) : VT_CONST
;
1023 gv2(RC_FLOAT
, RC_FLOAT
);
1024 assert(vtop
->type
.t
== VT_DOUBLE
|| vtop
->type
.t
== VT_FLOAT
);
1025 dbl
= vtop
->type
.t
== VT_DOUBLE
;
1026 rs1
= freg(vtop
[-1].r
);
1027 rs2
= freg(vtop
->r
);
1036 rd
= get_reg(RC_FLOAT
);
1039 ER(0x53, 7, rd
, rs1
, rs2
, dbl
| (op
<< 2)); // fop.[sd] RD, RS1, RS2 (dyn rm)
1053 rd
= get_reg(RC_INT
);
1056 ER(0x53, op
, rd
, rs1
, rs2
, dbl
| 0x50); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
1058 EI(0x13, 4, rd
, rd
, 1); // xori RD, 1
1072 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
1076 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
1081 ST_FUNC
void gen_cvt_sxtw(void)
1083 /* XXX on risc-v the registers are usually sign-extended already.
1084 Let's try to not do anything here. */
1087 ST_FUNC
void gen_cvt_itof(int t
)
1089 int rr
= ireg(gv(RC_INT
)), dr
;
1090 int u
= vtop
->type
.t
& VT_UNSIGNED
;
1091 int l
= (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
;
1092 if (t
== VT_LDOUBLE
) {
1094 (u
? TOK___floatunditf
: TOK___floatditf
) :
1095 (u
? TOK___floatunsitf
: TOK___floatsitf
);
1096 vpush_global_sym(&func_old_type
, func
);
1102 vtop
->r2
= TREG_R(1);
1105 dr
= get_reg(RC_FLOAT
);
1109 EIu(0x53, 7, dr
, rr
, ((0x68 | (t
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[sd].[wl][u]
1113 ST_FUNC
void gen_cvt_ftoi(int t
)
1115 int ft
= vtop
->type
.t
& VT_BTYPE
;
1116 int l
= (t
& VT_BTYPE
) == VT_LLONG
;
1117 int u
= t
& VT_UNSIGNED
;
1118 if (ft
== VT_LDOUBLE
) {
1120 (u
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1121 (u
? TOK___fixunstfsi
: TOK___fixtfsi
);
1122 vpush_global_sym(&func_old_type
, func
);
1129 int rr
= freg(gv(RC_FLOAT
)), dr
;
1131 dr
= get_reg(RC_INT
);
1135 EIu(0x53, 1, dr
, rr
, ((0x60 | (ft
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[wl][u].[sd] rtz
1139 ST_FUNC
void gen_cvt_ftof(int dt
)
1141 int st
= vtop
->type
.t
& VT_BTYPE
, rs
, rd
;
1145 if (dt
== VT_LDOUBLE
|| st
== VT_LDOUBLE
) {
1146 int func
= (dt
== VT_LDOUBLE
) ?
1147 (st
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1148 (dt
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1149 /* We can't use gfunc_call, as func_old_type works like vararg
1150 functions, and on riscv unnamed float args are passed like
1151 integers. But we really need them in the float argument registers
1152 for extendsftf2/extenddftf2. So, do it explicitely. */
1154 if (dt
== VT_LDOUBLE
)
1158 assert(vtop
->r2
< 7);
1159 if (vtop
->r2
!= 1 + vtop
->r
) {
1160 EI(0x13, 0, ireg(vtop
->r
) + 1, ireg(vtop
->r2
), 0); // mv Ra+1, RR2
1161 vtop
->r2
= 1 + vtop
->r
;
1164 vpush_global_sym(&func_old_type
, func
);
1169 if (dt
== VT_LDOUBLE
)
1170 vtop
->r
= REG_IRET
, vtop
->r2
= REG_IRET
+1;
1174 assert (dt
== VT_FLOAT
|| dt
== VT_DOUBLE
);
1175 assert (st
== VT_FLOAT
|| st
== VT_DOUBLE
);
1177 rd
= get_reg(RC_FLOAT
);
1178 if (dt
== VT_DOUBLE
)
1179 EI(0x53, 0, freg(rd
), freg(rs
), 0x21 << 5); // fcvt.d.s RD, RS (no rm)
1181 EI(0x53, 7, freg(rd
), freg(rs
), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm)
1186 ST_FUNC
void ggoto(void)
1192 ST_FUNC
void gen_vla_sp_save(int addr
)
1194 ES(0x23, 3, 8, 2, addr
); // sd sp, fc(s0)
1197 ST_FUNC
void gen_vla_sp_restore(int addr
)
1199 EI(0x03, 3, 2, 8, addr
); // ld sp, fc(s0)
1202 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
)
1204 int rr
= ireg(gv(RC_INT
));
1205 EI(0x13, 0, rr
, rr
, 15); // addi RR, RR, 15
1206 EI(0x13, 7, rr
, rr
, -16); // andi, RR, RR, -16
1207 ER(0x33, 0, 2, 2, rr
, 0x20); // sub sp, sp, rr