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[tinycc.git] / i386-asm.c
blobebdfe036d6c9cb58f1640842d491ec3ebdd8a238
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #define USING_GLOBALS
23 #include "tcc.h"
24
25 #define MAX_OPERANDS 3
26
27 #define TOK_ASM_first TOK_ASM_clc
28 #define TOK_ASM_last TOK_ASM_emms
29 #define TOK_ASM_alllast TOK_ASM_subps
30
31 #define OPC_B 0x01 /* only used with OPC_WL */
32 #define OPC_WL 0x02 /* accepts w, l or no suffix */
33 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
34 #define OPC_REG 0x04 /* register is added to opcode */
35 #define OPC_MODRM 0x08 /* modrm encoding */
36
37 #define OPCT_MASK 0x70
38 #define OPC_FWAIT 0x10 /* add fwait opcode */
39 #define OPC_SHIFT 0x20 /* shift opcodes */
40 #define OPC_ARITH 0x30 /* arithmetic opcodes */
41 #define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
42 #define OPC_TEST 0x50 /* test opcodes */
43 #define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
44
45 #define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
46 #define OPC_48 0x200 /* Always has REX prefix */
47 #ifdef TCC_TARGET_X86_64
48 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
49 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
50 # define OPC_WLX OPC_WLQ
51 # define OPC_BWLX OPC_BWLQ
52 #else
53 # define OPC_WLX OPC_WL
54 # define OPC_BWLX OPC_BWL
55 #endif
56
57 #define OPC_GROUP_SHIFT 13
58
59 /* in order to compress the operand type, we use specific operands and
60 we or only with EA */
61 enum {
62 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
65 #ifdef TCC_TARGET_X86_64
66 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
67 #endif
68 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
69 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
70 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
71 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
72 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
73 OPT_SEG,
74 OPT_ST,
75 #ifdef TCC_TARGET_X86_64
76 OPT_REG8_LOW, /* %spl,%bpl,%sil,%dil, encoded like ah,ch,dh,bh, but
77 with REX prefix, not used in insn templates */
78 #endif
79 OPT_IM8,
80 OPT_IM8S,
81 OPT_IM16,
82 OPT_IM32,
83 #ifdef TCC_TARGET_X86_64
84 OPT_IM64,
85 #endif
86 OPT_EAX, /* %al, %ax, %eax or %rax register */
87 OPT_ST0, /* %st(0) register */
88 OPT_CL, /* %cl register */
89 OPT_DX, /* %dx register */
90 OPT_ADDR, /* OP_EA with only offset */
91 OPT_INDIR, /* *(expr) */
92 /* composite types */
93 OPT_COMPOSITE_FIRST,
94 OPT_IM, /* IM8 | IM16 | IM32 */
95 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
96 OPT_REGW, /* REG16 | REG32 | REG64 */
97 OPT_IMW, /* IM16 | IM32 */
98 OPT_MMXSSE, /* MMX | SSE */
99 OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
100 OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */
101 /* can be ored with any OPT_xxx */
102 OPT_EA = 0x80
103 };
104
105 #define OP_REG8 (1 << OPT_REG8)
106 #define OP_REG16 (1 << OPT_REG16)
107 #define OP_REG32 (1 << OPT_REG32)
108 #define OP_MMX (1 << OPT_MMX)
109 #define OP_SSE (1 << OPT_SSE)
110 #define OP_CR (1 << OPT_CR)
111 #define OP_TR (1 << OPT_TR)
112 #define OP_DB (1 << OPT_DB)
113 #define OP_SEG (1 << OPT_SEG)
114 #define OP_ST (1 << OPT_ST)
115 #define OP_IM8 (1 << OPT_IM8)
116 #define OP_IM8S (1 << OPT_IM8S)
117 #define OP_IM16 (1 << OPT_IM16)
118 #define OP_IM32 (1 << OPT_IM32)
119 #define OP_EAX (1 << OPT_EAX)
120 #define OP_ST0 (1 << OPT_ST0)
121 #define OP_CL (1 << OPT_CL)
122 #define OP_DX (1 << OPT_DX)
123 #define OP_ADDR (1 << OPT_ADDR)
124 #define OP_INDIR (1 << OPT_INDIR)
125 #ifdef TCC_TARGET_X86_64
126 # define OP_REG64 (1 << OPT_REG64)
127 # define OP_REG8_LOW (1 << OPT_REG8_LOW)
128 # define OP_IM64 (1 << OPT_IM64)
129 # define OP_EA32 (OP_EA << 1)
130 #else
131 # define OP_REG64 0
132 # define OP_REG8_LOW 0
133 # define OP_IM64 0
134 # define OP_EA32 0
135 #endif
136
137 #define OP_EA 0x40000000
138 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
139
140 #ifdef TCC_TARGET_X86_64
141 # define TREG_XAX TREG_RAX
142 # define TREG_XCX TREG_RCX
143 # define TREG_XDX TREG_RDX
144 #else
145 # define TREG_XAX TREG_EAX
146 # define TREG_XCX TREG_ECX
147 # define TREG_XDX TREG_EDX
148 #endif
149
150 typedef struct ASMInstr {
151 uint16_t sym;
152 uint16_t opcode;
153 uint16_t instr_type;
154 uint8_t nb_ops;
155 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
156 } ASMInstr;
157
158 typedef struct Operand {
159 uint32_t type;
160 int8_t reg; /* register, -1 if none */
161 int8_t reg2; /* second register, -1 if none */
162 uint8_t shift;
163 ExprValue e;
164 } Operand;
165
166 static const uint8_t reg_to_size[9] = {
167 /*
168 [OP_REG8] = 0,
169 [OP_REG16] = 1,
170 [OP_REG32] = 2,
171 #ifdef TCC_TARGET_X86_64
172 [OP_REG64] = 3,
173 #endif
174 */
175 0, 0, 1, 0, 2, 0, 0, 0, 3
176 };
177
178 #define NB_TEST_OPCODES 30
179
180 static const uint8_t test_bits[NB_TEST_OPCODES] = {
181 0x00, /* o */
182 0x01, /* no */
183 0x02, /* b */
184 0x02, /* c */
185 0x02, /* nae */
186 0x03, /* nb */
187 0x03, /* nc */
188 0x03, /* ae */
189 0x04, /* e */
190 0x04, /* z */
191 0x05, /* ne */
192 0x05, /* nz */
193 0x06, /* be */
194 0x06, /* na */
195 0x07, /* nbe */
196 0x07, /* a */
197 0x08, /* s */
198 0x09, /* ns */
199 0x0a, /* p */
200 0x0a, /* pe */
201 0x0b, /* np */
202 0x0b, /* po */
203 0x0c, /* l */
204 0x0c, /* nge */
205 0x0d, /* nl */
206 0x0d, /* ge */
207 0x0e, /* le */
208 0x0e, /* ng */
209 0x0f, /* nle */
210 0x0f, /* g */
211 };
212
213 static const uint8_t segment_prefixes[] = {
214 0x26, /* es */
215 0x2e, /* cs */
216 0x36, /* ss */
217 0x3e, /* ds */
218 0x64, /* fs */
219 0x65 /* gs */
220 };
221
222 static const ASMInstr asm_instrs[] = {
223 #define ALT(x) x
224 /* This removes a 0x0f in the second byte */
225 #define O(o) ((uint64_t) ((((o) & 0xff00) == 0x0f00) ? ((((o) >> 8) & ~0xff) | ((o) & 0xff)) : (o)))
226 /* This constructs instr_type from opcode, type and group. */
227 #define T(o,i,g) ((i) | ((g) << OPC_GROUP_SHIFT) | ((((o) & 0xff00) == 0x0f00) ? OPC_0F : 0))
228 #define DEF_ASM_OP0(name, opcode)
229 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 0, { 0 } },
230 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 1, { op0 }},
231 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 2, { op0, op1 }},
232 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, O(opcode), T(opcode, instr_type, group), 3, { op0, op1, op2 }},
233 #ifdef TCC_TARGET_X86_64
234 # include "x86_64-asm.h"
235 #else
236 # include "i386-asm.h"
237 #endif
238 /* last operation */
239 { 0, },
240 };
241
242 static const uint16_t op0_codes[] = {
243 #define ALT(x)
244 #define DEF_ASM_OP0(x, opcode) opcode,
245 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
246 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
247 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
248 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
249 #ifdef TCC_TARGET_X86_64
250 # include "x86_64-asm.h"
251 #else
252 # include "i386-asm.h"
253 #endif
254 };
255
256 static inline int get_reg_shift(TCCState *s1)
257 {
258 int shift, v;
259 v = asm_int_expr(s1);
260 switch(v) {
261 case 1:
262 shift = 0;
263 break;
264 case 2:
265 shift = 1;
266 break;
267 case 4:
268 shift = 2;
269 break;
270 case 8:
271 shift = 3;
272 break;
273 default:
274 expect("1, 2, 4 or 8 constant");
275 shift = 0;
276 break;
277 }
278 return shift;
279 }
280
281 #ifdef TCC_TARGET_X86_64
282 static int asm_parse_numeric_reg(int t, unsigned int *type)
283 {
284 int reg = -1;
285 if (t >= TOK_IDENT && t < tok_ident) {
286 const char *s = table_ident[t - TOK_IDENT]->str;
287 char c;
288 *type = OP_REG64;
289 if (*s == 'c') {
290 s++;
291 *type = OP_CR;
292 }
293 if (*s++ != 'r')
294 return -1;
295 /* Don't allow leading '0'. */
296 if ((c = *s++) >= '1' && c <= '9')
297 reg = c - '0';
298 else
299 return -1;
300 if ((c = *s) >= '0' && c <= '5')
301 s++, reg = reg * 10 + c - '0';
302 if (reg > 15)
303 return -1;
304 if ((c = *s) == 0)
305 ;
306 else if (*type != OP_REG64)
307 return -1;
308 else if (c == 'b' && !s[1])
309 *type = OP_REG8;
310 else if (c == 'w' && !s[1])
311 *type = OP_REG16;
312 else if (c == 'd' && !s[1])
313 *type = OP_REG32;
314 else
315 return -1;
316 }
317 return reg;
318 }
319 #endif
320
321 static int asm_parse_reg(unsigned int *type)
322 {
323 int reg = 0;
324 *type = 0;
325 if (tok != '%')
326 goto error_32;
327 next();
328 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
329 reg = tok - TOK_ASM_eax;
330 *type = OP_REG32;
331 #ifdef TCC_TARGET_X86_64
332 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
333 reg = tok - TOK_ASM_rax;
334 *type = OP_REG64;
335 } else if (tok == TOK_ASM_rip) {
336 reg = -2; /* Probably should use different escape code. */
337 *type = OP_REG64;
338 } else if ((reg = asm_parse_numeric_reg(tok, type)) >= 0
339 && (*type == OP_REG32 || *type == OP_REG64)) {
340 ;
341 #endif
342 } else {
343 error_32:
344 expect("register");
345 }
346 next();
347 return reg;
348 }
349
350 static void parse_operand(TCCState *s1, Operand *op)
351 {
352 ExprValue e;
353 int reg, indir;
354 const char *p;
355
356 indir = 0;
357 if (tok == '*') {
358 next();
359 indir = OP_INDIR;
360 }
361
362 if (tok == '%') {
363 next();
364 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
365 reg = tok - TOK_ASM_al;
366 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
367 op->reg = reg & 7;
368 if ((op->type & OP_REG) && op->reg == TREG_XAX)
369 op->type |= OP_EAX;
370 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
371 op->type |= OP_CL;
372 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
373 op->type |= OP_DX;
374 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
375 op->type = OP_DB;
376 op->reg = tok - TOK_ASM_dr0;
377 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
378 op->type = OP_SEG;
379 op->reg = tok - TOK_ASM_es;
380 } else if (tok == TOK_ASM_st) {
381 op->type = OP_ST;
382 op->reg = 0;
383 next();
384 if (tok == '(') {
385 next();
386 if (tok != TOK_PPNUM)
387 goto reg_error;
388 p = tokc.str.data;
389 reg = p[0] - '0';
390 if ((unsigned)reg >= 8 || p[1] != '\0')
391 goto reg_error;
392 op->reg = reg;
393 next();
394 skip(')');
395 }
396 if (op->reg == 0)
397 op->type |= OP_ST0;
398 goto no_skip;
399 #ifdef TCC_TARGET_X86_64
400 } else if (tok >= TOK_ASM_spl && tok <= TOK_ASM_dil) {
401 op->type = OP_REG8 | OP_REG8_LOW;
402 op->reg = 4 + tok - TOK_ASM_spl;
403 } else if ((op->reg = asm_parse_numeric_reg(tok, &op->type)) >= 0) {
404 ;
405 #endif
406 } else {
407 reg_error:
408 tcc_error("unknown register %%%s", get_tok_str(tok, &tokc));
409 }
410 next();
411 no_skip: ;
412 } else if (tok == '$') {
413 /* constant value */
414 next();
415 asm_expr(s1, &e);
416 op->type = OP_IM32;
417 op->e = e;
418 if (!op->e.sym) {
419 if (op->e.v == (uint8_t)op->e.v)
420 op->type |= OP_IM8;
421 if (op->e.v == (int8_t)op->e.v)
422 op->type |= OP_IM8S;
423 if (op->e.v == (uint16_t)op->e.v)
424 op->type |= OP_IM16;
425 #ifdef TCC_TARGET_X86_64
426 if (op->e.v != (int32_t)op->e.v && op->e.v != (uint32_t)op->e.v)
427 op->type = OP_IM64;
428 #endif
429 }
430 } else {
431 /* address(reg,reg2,shift) with all variants */
432 op->type = OP_EA;
433 op->reg = -1;
434 op->reg2 = -1;
435 op->shift = 0;
436 if (tok != '(') {
437 asm_expr(s1, &e);
438 op->e = e;
439 } else {
440 next();
441 if (tok == '%') {
442 unget_tok('(');
443 op->e.v = 0;
444 op->e.sym = NULL;
445 } else {
446 /* bracketed offset expression */
447 asm_expr(s1, &e);
448 if (tok != ')')
449 expect(")");
450 next();
451 op->e.v = e.v;
452 op->e.sym = e.sym;
453 }
454 op->e.pcrel = 0;
455 }
456 if (tok == '(') {
457 unsigned int type = 0;
458 next();
459 if (tok != ',') {
460 op->reg = asm_parse_reg(&type);
461 }
462 if (tok == ',') {
463 next();
464 if (tok != ',') {
465 op->reg2 = asm_parse_reg(&type);
466 }
467 if (tok == ',') {
468 next();
469 op->shift = get_reg_shift(s1);
470 }
471 }
472 if (type & OP_REG32)
473 op->type |= OP_EA32;
474 skip(')');
475 }
476 if (op->reg == -1 && op->reg2 == -1)
477 op->type |= OP_ADDR;
478 }
479 op->type |= indir;
480 }
481
482 /* XXX: unify with C code output ? */
483 ST_FUNC void gen_expr32(ExprValue *pe)
484 {
485 if (pe->pcrel)
486 /* If PC-relative, always set VT_SYM, even without symbol,
487 so as to force a relocation to be emitted. */
488 gen_addrpc32(VT_SYM, pe->sym, pe->v);
489 else
490 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
491 }
492
493 #ifdef TCC_TARGET_X86_64
494 ST_FUNC void gen_expr64(ExprValue *pe)
495 {
496 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
497 }
498 #endif
499
500 /* XXX: unify with C code output ? */
501 static void gen_disp32(ExprValue *pe)
502 {
503 Sym *sym = pe->sym;
504 ElfSym *esym = elfsym(sym);
505 if (esym && esym->st_shndx == cur_text_section->sh_num) {
506 /* same section: we can output an absolute value. Note
507 that the TCC compiler behaves differently here because
508 it always outputs a relocation to ease (future) code
509 elimination in the linker */
510 gen_le32(pe->v + esym->st_value - ind - 4);
511 } else {
512 if (sym && sym->type.t == VT_VOID) {
513 sym->type.t = VT_FUNC;
514 sym->type.ref = NULL;
515 }
516 gen_addrpc32(VT_SYM, sym, pe->v);
517 }
518 }
519
520 /* generate the modrm operand */
521 static inline int asm_modrm(int reg, Operand *op)
522 {
523 int mod, reg1, reg2, sib_reg1;
524
525 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
526 g(0xc0 + (reg << 3) + op->reg);
527 } else if (op->reg == -1 && op->reg2 == -1) {
528 /* displacement only */
529 #ifdef TCC_TARGET_X86_64
530 g(0x04 + (reg << 3));
531 g(0x25);
532 #else
533 g(0x05 + (reg << 3));
534 #endif
535 gen_expr32(&op->e);
536 #ifdef TCC_TARGET_X86_64
537 } else if (op->reg == -2) {
538 ExprValue *pe = &op->e;
539 g(0x05 + (reg << 3));
540 gen_addrpc32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
541 return ind;
542 #endif
543 } else {
544 sib_reg1 = op->reg;
545 /* fist compute displacement encoding */
546 if (sib_reg1 == -1) {
547 sib_reg1 = 5;
548 mod = 0x00;
549 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
550 mod = 0x00;
551 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
552 mod = 0x40;
553 } else {
554 mod = 0x80;
555 }
556 /* compute if sib byte needed */
557 reg1 = op->reg;
558 if (op->reg2 != -1)
559 reg1 = 4;
560 g(mod + (reg << 3) + reg1);
561 if (reg1 == 4) {
562 /* add sib byte */
563 reg2 = op->reg2;
564 if (reg2 == -1)
565 reg2 = 4; /* indicate no index */
566 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
567 }
568 /* add offset */
569 if (mod == 0x40) {
570 g(op->e.v);
571 } else if (mod == 0x80 || op->reg == -1) {
572 gen_expr32(&op->e);
573 }
574 }
575 return 0;
576 }
577
578 #ifdef TCC_TARGET_X86_64
579 #define REX_W 0x48
580 #define REX_R 0x44
581 #define REX_X 0x42
582 #define REX_B 0x41
583
584 static void asm_rex(int width64, Operand *ops, int nb_ops, int *op_type,
585 int regi, int rmi)
586 {
587 unsigned char rex = width64 ? 0x48 : 0;
588 int saw_high_8bit = 0;
589 int i;
590 if (rmi == -1) {
591 /* No mod/rm byte, but we might have a register op nevertheless
592 (we will add it to the opcode later). */
593 for(i = 0; i < nb_ops; i++) {
594 if (op_type[i] & (OP_REG | OP_ST)) {
595 if (ops[i].reg >= 8) {
596 rex |= REX_B;
597 ops[i].reg -= 8;
598 } else if (ops[i].type & OP_REG8_LOW)
599 rex |= 0x40;
600 else if (ops[i].type & OP_REG8 && ops[i].reg >= 4)
601 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
602 saw_high_8bit = ops[i].reg;
603 break;
604 }
605 }
606 } else {
607 if (regi != -1) {
608 if (ops[regi].reg >= 8) {
609 rex |= REX_R;
610 ops[regi].reg -= 8;
611 } else if (ops[regi].type & OP_REG8_LOW)
612 rex |= 0x40;
613 else if (ops[regi].type & OP_REG8 && ops[regi].reg >= 4)
614 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
615 saw_high_8bit = ops[regi].reg;
616 }
617 if (ops[rmi].type & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_EA)) {
618 if (ops[rmi].reg >= 8) {
619 rex |= REX_B;
620 ops[rmi].reg -= 8;
621 } else if (ops[rmi].type & OP_REG8_LOW)
622 rex |= 0x40;
623 else if (ops[rmi].type & OP_REG8 && ops[rmi].reg >= 4)
624 /* An 8 bit reg >= 4 without REG8 is ah/ch/dh/bh */
625 saw_high_8bit = ops[rmi].reg;
626 }
627 if (ops[rmi].type & OP_EA && ops[rmi].reg2 >= 8) {
628 rex |= REX_X;
629 ops[rmi].reg2 -= 8;
630 }
631 }
632 if (rex) {
633 if (saw_high_8bit)
634 tcc_error("can't encode register %%%ch when REX prefix is required",
635 "acdb"[saw_high_8bit-4]);
636 g(rex);
637 }
638 }
639 #endif
640
641
642 static void maybe_print_stats (void)
643 {
644 static int already;
645
646 if (0 && !already)
647 /* print stats about opcodes */
648 {
649 const struct ASMInstr *pa;
650 int freq[4];
651 int op_vals[500];
652 int nb_op_vals, i, j;
653
654 already = 1;
655 nb_op_vals = 0;
656 memset(freq, 0, sizeof(freq));
657 for(pa = asm_instrs; pa->sym != 0; pa++) {
658 freq[pa->nb_ops]++;
659 //for(i=0;i<pa->nb_ops;i++) {
660 for(j=0;j<nb_op_vals;j++) {
661 //if (pa->op_type[i] == op_vals[j])
662 if (pa->instr_type == op_vals[j])
663 goto found;
664 }
665 //op_vals[nb_op_vals++] = pa->op_type[i];
666 op_vals[nb_op_vals++] = pa->instr_type;
667 found: ;
668 //}
669 }
670 for(i=0;i<nb_op_vals;i++) {
671 int v = op_vals[i];
672 //if ((v & (v - 1)) != 0)
673 printf("%3d: %08x\n", i, v);
674 }
675 printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
676 (int)sizeof(asm_instrs),
677 (int)sizeof(asm_instrs) / (int)sizeof(ASMInstr),
678 freq[0], freq[1], freq[2], freq[3]);
679 }
680 }
681
682 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
683 {
684 const ASMInstr *pa;
685 int i, modrm_index, modreg_index, reg, v, op1, seg_prefix, pc;
686 int nb_ops, s;
687 Operand ops[MAX_OPERANDS], *pop;
688 int op_type[3]; /* decoded op type */
689 int alltypes; /* OR of all operand types */
690 int autosize;
691 int p66;
692 #ifdef TCC_TARGET_X86_64
693 int rex64;
694 #endif
695
696 maybe_print_stats();
697 /* force synthetic ';' after prefix instruction, so we can handle */
698 /* one-line things like "rep stosb" instead of only "rep\nstosb" */
699 if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
700 unget_tok(';');
701
702 /* get operands */
703 pop = ops;
704 nb_ops = 0;
705 seg_prefix = 0;
706 alltypes = 0;
707 for(;;) {
708 if (tok == ';' || tok == TOK_LINEFEED)
709 break;
710 if (nb_ops >= MAX_OPERANDS) {
711 tcc_error("incorrect number of operands");
712 }
713 parse_operand(s1, pop);
714 if (tok == ':') {
715 if (pop->type != OP_SEG || seg_prefix)
716 tcc_error("incorrect prefix");
717 seg_prefix = segment_prefixes[pop->reg];
718 next();
719 parse_operand(s1, pop);
720 if (!(pop->type & OP_EA)) {
721 tcc_error("segment prefix must be followed by memory reference");
722 }
723 }
724 pop++;
725 nb_ops++;
726 if (tok != ',')
727 break;
728 next();
729 }
730
731 s = 0; /* avoid warning */
732
733 again:
734 /* optimize matching by using a lookup table (no hashing is needed
735 !) */
736 for(pa = asm_instrs; pa->sym != 0; pa++) {
737 int it = pa->instr_type & OPCT_MASK;
738 s = 0;
739 if (it == OPC_FARITH) {
740 v = opcode - pa->sym;
741 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
742 continue;
743 } else if (it == OPC_ARITH) {
744 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
745 continue;
746 s = (opcode - pa->sym) % NBWLX;
747 if ((pa->instr_type & OPC_BWLX) == OPC_WLX)
748 {
749 /* We need to reject the xxxb opcodes that we accepted above.
750 Note that pa->sym for WLX opcodes is the 'w' token,
751 to get the 'b' token subtract one. */
752 if (((opcode - pa->sym + 1) % NBWLX) == 0)
753 continue;
754 s++;
755 }
756 } else if (it == OPC_SHIFT) {
757 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
758 continue;
759 s = (opcode - pa->sym) % NBWLX;
760 } else if (it == OPC_TEST) {
761 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
762 continue;
763 /* cmovxx is a test opcode but accepts multiple sizes.
764 The suffixes aren't encoded in the table, instead we
765 simply force size autodetection always and deal with suffixed
766 variants below when we don't find e.g. "cmovzl". */
767 if (pa->instr_type & OPC_WLX)
768 s = NBWLX - 1;
769 } else if (pa->instr_type & OPC_B) {
770 #ifdef TCC_TARGET_X86_64
771 /* Some instructions don't have the full size but only
772 bwl form. insb e.g. */
773 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
774 && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
775 continue;
776 #endif
777 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
778 continue;
779 s = opcode - pa->sym;
780 } else if (pa->instr_type & OPC_WLX) {
781 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
782 continue;
783 s = opcode - pa->sym + 1;
784 } else {
785 if (pa->sym != opcode)
786 continue;
787 }
788 if (pa->nb_ops != nb_ops)
789 continue;
790 #ifdef TCC_TARGET_X86_64
791 /* Special case for moves. Selecting the IM64->REG64 form
792 should only be done if we really have an >32bit imm64, and that
793 is hardcoded. Ignore it here. */
794 if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
795 && (ops[1].type & OP_REG) == OP_REG64
796 && !(pa->instr_type & OPC_0F))
797 continue;
798 #endif
799 /* now decode and check each operand */
800 alltypes = 0;
801 for(i = 0; i < nb_ops; i++) {
802 int op1, op2;
803 op1 = pa->op_type[i];
804 op2 = op1 & 0x1f;
805 switch(op2) {
806 case OPT_IM:
807 v = OP_IM8 | OP_IM16 | OP_IM32;
808 break;
809 case OPT_REG:
810 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
811 break;
812 case OPT_REGW:
813 v = OP_REG16 | OP_REG32 | OP_REG64;
814 break;
815 case OPT_IMW:
816 v = OP_IM16 | OP_IM32;
817 break;
818 case OPT_MMXSSE:
819 v = OP_MMX | OP_SSE;
820 break;
821 case OPT_DISP:
822 case OPT_DISP8:
823 v = OP_ADDR;
824 break;
825 default:
826 v = 1 << op2;
827 break;
828 }
829 if (op1 & OPT_EA)
830 v |= OP_EA;
831 op_type[i] = v;
832 if ((ops[i].type & v) == 0)
833 goto next;
834 alltypes |= ops[i].type;
835 }
836 (void)alltypes; /* maybe unused */
837 /* all is matching ! */
838 break;
839 next: ;
840 }
841 if (pa->sym == 0) {
842 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
843 int b;
844 b = op0_codes[opcode - TOK_ASM_first];
845 if (b & 0xff00)
846 g(b >> 8);
847 g(b);
848 return;
849 } else if (opcode <= TOK_ASM_alllast) {
850 tcc_error("bad operand with opcode '%s'",
851 get_tok_str(opcode, NULL));
852 } else {
853 /* Special case for cmovcc, we accept size suffixes but ignore
854 them, but we don't want them to blow up our tables. */
855 TokenSym *ts = table_ident[opcode - TOK_IDENT];
856 if (ts->len >= 6
857 && strchr("wlq", ts->str[ts->len-1])
858 && !memcmp(ts->str, "cmov", 4)) {
859 opcode = tok_alloc(ts->str, ts->len-1)->tok;
860 goto again;
861 }
862 tcc_error("unknown opcode '%s'", ts->str);
863 }
864 }
865 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
866 autosize = NBWLX-1;
867 #ifdef TCC_TARGET_X86_64
868 /* XXX the autosize should rather be zero, to not have to adjust this
869 all the time. */
870 if ((pa->instr_type & OPC_BWLQ) == OPC_B)
871 autosize = NBWLX-2;
872 #endif
873 if (s == autosize) {
874 /* Check for register operands providing hints about the size.
875 Start from the end, i.e. destination operands. This matters
876 only for opcodes accepting different sized registers, lar and lsl
877 are such opcodes. */
878 for(i = nb_ops - 1; s == autosize && i >= 0; i--) {
879 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
880 s = reg_to_size[ops[i].type & OP_REG];
881 }
882 if (s == autosize) {
883 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
884 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
885 s = 2;
886 else if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
887 (ops[0].type & OP_EA))
888 s = NBWLX - 2;
889 else
890 tcc_error("cannot infer opcode suffix");
891 }
892 }
893
894 #ifdef TCC_TARGET_X86_64
895 /* Generate addr32 prefix if needed */
896 for(i = 0; i < nb_ops; i++) {
897 if (ops[i].type & OP_EA32) {
898 g(0x67);
899 break;
900 }
901 }
902 #endif
903 /* generate data16 prefix if needed */
904 p66 = 0;
905 if (s == 1)
906 p66 = 1;
907 else {
908 /* accepting mmx+sse in all operands --> needs 0x66 to
909 switch to sse mode. Accepting only sse in an operand --> is
910 already SSE insn and needs 0x66/f2/f3 handling. */
911 for (i = 0; i < nb_ops; i++)
912 if ((op_type[i] & (OP_MMX | OP_SSE)) == (OP_MMX | OP_SSE)
913 && ops[i].type & OP_SSE)
914 p66 = 1;
915 }
916 if (p66)
917 g(0x66);
918 #ifdef TCC_TARGET_X86_64
919 rex64 = 0;
920 if (pa->instr_type & OPC_48)
921 rex64 = 1;
922 else if (s == 3 || (alltypes & OP_REG64)) {
923 /* generate REX prefix */
924 int default64 = 0;
925 for(i = 0; i < nb_ops; i++) {
926 if (op_type[i] == OP_REG64 && pa->opcode != 0xb8) {
927 /* If only 64bit regs are accepted in one operand
928 this is a default64 instruction without need for
929 REX prefixes, except for movabs(0xb8). */
930 default64 = 1;
931 break;
932 }
933 }
934 /* XXX find better encoding for the default64 instructions. */
935 if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
936 && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
937 && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
938 && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
939 && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
940 && !default64)
941 rex64 = 1;
942 }
943 #endif
944
945 /* now generates the operation */
946 if (OPCT_IS(pa->instr_type, OPC_FWAIT))
947 g(0x9b);
948 if (seg_prefix)
949 g(seg_prefix);
950
951 v = pa->opcode;
952 if (pa->instr_type & OPC_0F)
953 v = ((v & ~0xff) << 8) | 0x0f00 | (v & 0xff);
954 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
955 /* kludge for imul $im, %reg */
956 nb_ops = 3;
957 ops[2] = ops[1];
958 op_type[2] = op_type[1];
959 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
960 v--; /* int $3 case */
961 nb_ops = 0;
962 } else if ((v == 0x06 || v == 0x07)) {
963 if (ops[0].reg >= 4) {
964 /* push/pop %fs or %gs */
965 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
966 } else {
967 v += ops[0].reg << 3;
968 }
969 nb_ops = 0;
970 } else if (v <= 0x05) {
971 /* arith case */
972 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
973 } else if ((pa->instr_type & (OPCT_MASK | OPC_MODRM)) == OPC_FARITH) {
974 /* fpu arith case */
975 v += ((opcode - pa->sym) / 6) << 3;
976 }
977
978 /* search which operand will be used for modrm */
979 modrm_index = -1;
980 modreg_index = -1;
981 if (pa->instr_type & OPC_MODRM) {
982 if (!nb_ops) {
983 /* A modrm opcode without operands is a special case (e.g. mfence).
984 It has a group and acts as if there's an register operand 0
985 (ax). */
986 i = 0;
987 ops[i].type = OP_REG;
988 ops[i].reg = 0;
989 goto modrm_found;
990 }
991 /* first look for an ea operand */
992 for(i = 0;i < nb_ops; i++) {
993 if (op_type[i] & OP_EA)
994 goto modrm_found;
995 }
996 /* then if not found, a register or indirection (shift instructions) */
997 for(i = 0;i < nb_ops; i++) {
998 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
999 goto modrm_found;
1000 }
1001 #ifdef ASM_DEBUG
1002 tcc_error("bad op table");
1003 #endif
1004 modrm_found:
1005 modrm_index = i;
1006 /* if a register is used in another operand then it is
1007 used instead of group */
1008 for(i = 0;i < nb_ops; i++) {
1009 int t = op_type[i];
1010 if (i != modrm_index &&
1011 (t & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
1012 modreg_index = i;
1013 break;
1014 }
1015 }
1016 }
1017 #ifdef TCC_TARGET_X86_64
1018 asm_rex (rex64, ops, nb_ops, op_type, modreg_index, modrm_index);
1019 #endif
1020
1021 if (pa->instr_type & OPC_REG) {
1022 /* mov $im, %reg case */
1023 if (v == 0xb0 && s >= 1)
1024 v += 7;
1025 for(i = 0; i < nb_ops; i++) {
1026 if (op_type[i] & (OP_REG | OP_ST)) {
1027 v += ops[i].reg;
1028 break;
1029 }
1030 }
1031 }
1032 if (pa->instr_type & OPC_B)
1033 v += s >= 1;
1034 if (nb_ops == 1 && pa->op_type[0] == OPT_DISP8) {
1035 ElfSym *esym;
1036 int jmp_disp;
1037
1038 /* see if we can really generate the jump with a byte offset */
1039 esym = elfsym(ops[0].e.sym);
1040 if (!esym || esym->st_shndx != cur_text_section->sh_num)
1041 goto no_short_jump;
1042 jmp_disp = ops[0].e.v + esym->st_value - ind - 2 - (v >= 0xff);
1043 if (jmp_disp == (int8_t)jmp_disp) {
1044 /* OK to generate jump */
1045 ops[0].e.sym = 0;
1046 ops[0].e.v = jmp_disp;
1047 op_type[0] = OP_IM8S;
1048 } else {
1049 no_short_jump:
1050 /* long jump will be allowed. need to modify the
1051 opcode slightly */
1052 if (v == 0xeb) /* jmp */
1053 v = 0xe9;
1054 else if (v == 0x70) /* jcc */
1055 v += 0x0f10;
1056 else
1057 tcc_error("invalid displacement");
1058 }
1059 }
1060 if (OPCT_IS(pa->instr_type, OPC_TEST))
1061 v += test_bits[opcode - pa->sym];
1062 op1 = v >> 16;
1063 if (op1)
1064 g(op1);
1065 op1 = (v >> 8) & 0xff;
1066 if (op1)
1067 g(op1);
1068 g(v);
1069
1070 if (OPCT_IS(pa->instr_type, OPC_SHIFT)) {
1071 reg = (opcode - pa->sym) / NBWLX;
1072 if (reg == 6)
1073 reg = 7;
1074 } else if (OPCT_IS(pa->instr_type, OPC_ARITH)) {
1075 reg = (opcode - pa->sym) / NBWLX;
1076 } else if (OPCT_IS(pa->instr_type, OPC_FARITH)) {
1077 reg = (opcode - pa->sym) / 6;
1078 } else {
1079 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
1080 }
1081
1082 pc = 0;
1083 if (pa->instr_type & OPC_MODRM) {
1084 /* if a register is used in another operand then it is
1085 used instead of group */
1086 if (modreg_index >= 0)
1087 reg = ops[modreg_index].reg;
1088 pc = asm_modrm(reg, &ops[modrm_index]);
1089 }
1090
1091 /* emit constants */
1092 #ifndef TCC_TARGET_X86_64
1093 if (!(pa->instr_type & OPC_0F)
1094 && (pa->opcode == 0x9a || pa->opcode == 0xea)) {
1095 /* ljmp or lcall kludge */
1096 gen_expr32(&ops[1].e);
1097 if (ops[0].e.sym)
1098 tcc_error("cannot relocate");
1099 gen_le16(ops[0].e.v);
1100 return;
1101 }
1102 #endif
1103 for(i = 0;i < nb_ops; i++) {
1104 v = op_type[i];
1105 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
1106 /* if multiple sizes are given it means we must look
1107 at the op size */
1108 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
1109 if (s == 0)
1110 v = OP_IM8;
1111 else if (s == 1)
1112 v = OP_IM16;
1113 else if (s == 2 || (v & OP_IM64) == 0)
1114 v = OP_IM32;
1115 else
1116 v = OP_IM64;
1117 }
1118
1119 if ((v & (OP_IM8 | OP_IM8S | OP_IM16)) && ops[i].e.sym)
1120 tcc_error("cannot relocate");
1121
1122 if (v & (OP_IM8 | OP_IM8S)) {
1123 g(ops[i].e.v);
1124 } else if (v & OP_IM16) {
1125 gen_le16(ops[i].e.v);
1126 #ifdef TCC_TARGET_X86_64
1127 } else if (v & OP_IM64) {
1128 gen_expr64(&ops[i].e);
1129 #endif
1130 } else if (pa->op_type[i] == OPT_DISP || pa->op_type[i] == OPT_DISP8) {
1131 gen_disp32(&ops[i].e);
1132 } else {
1133 gen_expr32(&ops[i].e);
1134 }
1135 }
1136 }
1137
1138 /* after immediate operands, adjust pc-relative address */
1139 if (pc)
1140 add32le(cur_text_section->data + pc - 4, pc - ind);
1141 }
1142
1143 /* return the constraint priority (we allocate first the lowest
1144 numbered constraints) */
1145 static inline int constraint_priority(const char *str)
1146 {
1147 int priority, c, pr;
1148
1149 /* we take the lowest priority */
1150 priority = 0;
1151 for(;;) {
1152 c = *str;
1153 if (c == '\0')
1154 break;
1155 str++;
1156 switch(c) {
1157 case 'A':
1158 pr = 0;
1159 break;
1160 case 'a':
1161 case 'b':
1162 case 'c':
1163 case 'd':
1164 case 'S':
1165 case 'D':
1166 pr = 1;
1167 break;
1168 case 'q':
1169 pr = 2;
1170 break;
1171 case 'r':
1172 case 'R':
1173 case 'p':
1174 pr = 3;
1175 break;
1176 case 'N':
1177 case 'M':
1178 case 'I':
1179 case 'e':
1180 case 'i':
1181 case 'm':
1182 case 'g':
1183 pr = 4;
1184 break;
1185 default:
1186 tcc_error("unknown constraint '%c'", c);
1187 pr = 0;
1188 }
1189 if (pr > priority)
1190 priority = pr;
1191 }
1192 return priority;
1193 }
1194
1195 static const char *skip_constraint_modifiers(const char *p)
1196 {
1197 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1198 p++;
1199 return p;
1200 }
1201
1202 /* If T (a token) is of the form "%reg" returns the register
1203 number and type, otherwise return -1. */
1204 ST_FUNC int asm_parse_regvar (int t)
1205 {
1206 const char *s;
1207 Operand op;
1208 if (t < TOK_IDENT || (t & SYM_FIELD))
1209 return -1;
1210 s = table_ident[t - TOK_IDENT]->str;
1211 if (s[0] != '%')
1212 return -1;
1213 t = tok_alloc_const(s + 1);
1214 unget_tok(t);
1215 unget_tok('%');
1216 parse_operand(tcc_state, &op);
1217 /* Accept only integer regs for now. */
1218 if (op.type & OP_REG)
1219 return op.reg;
1220 else
1221 return -1;
1222 }
1223
1224 #define REG_OUT_MASK 0x01
1225 #define REG_IN_MASK 0x02
1226
1227 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1228
1229 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1230 int nb_operands, int nb_outputs,
1231 const uint8_t *clobber_regs,
1232 int *pout_reg)
1233 {
1234 ASMOperand *op;
1235 int sorted_op[MAX_ASM_OPERANDS];
1236 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1237 const char *str;
1238 uint8_t regs_allocated[NB_ASM_REGS];
1239
1240 /* init fields */
1241 for(i=0;i<nb_operands;i++) {
1242 op = &operands[i];
1243 op->input_index = -1;
1244 op->ref_index = -1;
1245 op->reg = -1;
1246 op->is_memory = 0;
1247 op->is_rw = 0;
1248 }
1249 /* compute constraint priority and evaluate references to output
1250 constraints if input constraints */
1251 for(i=0;i<nb_operands;i++) {
1252 op = &operands[i];
1253 str = op->constraint;
1254 str = skip_constraint_modifiers(str);
1255 if (isnum(*str) || *str == '[') {
1256 /* this is a reference to another constraint */
1257 k = find_constraint(operands, nb_operands, str, NULL);
1258 if ((unsigned)k >= i || i < nb_outputs)
1259 tcc_error("invalid reference in constraint %d ('%s')",
1260 i, str);
1261 op->ref_index = k;
1262 if (operands[k].input_index >= 0)
1263 tcc_error("cannot reference twice the same operand");
1264 operands[k].input_index = i;
1265 op->priority = 5;
1266 } else if ((op->vt->r & VT_VALMASK) == VT_LOCAL
1267 && op->vt->sym
1268 && (reg = op->vt->sym->r & VT_VALMASK) < VT_CONST) {
1269 op->priority = 1;
1270 op->reg = reg;
1271 } else {
1272 op->priority = constraint_priority(str);
1273 }
1274 }
1275
1276 /* sort operands according to their priority */
1277 for(i=0;i<nb_operands;i++)
1278 sorted_op[i] = i;
1279 for(i=0;i<nb_operands - 1;i++) {
1280 for(j=i+1;j<nb_operands;j++) {
1281 p1 = operands[sorted_op[i]].priority;
1282 p2 = operands[sorted_op[j]].priority;
1283 if (p2 < p1) {
1284 tmp = sorted_op[i];
1285 sorted_op[i] = sorted_op[j];
1286 sorted_op[j] = tmp;
1287 }
1288 }
1289 }
1290
1291 for(i = 0;i < NB_ASM_REGS; i++) {
1292 if (clobber_regs[i])
1293 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1294 else
1295 regs_allocated[i] = 0;
1296 }
1297 /* esp cannot be used */
1298 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1299 /* ebp cannot be used yet */
1300 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1301
1302 /* allocate registers and generate corresponding asm moves */
1303 for(i=0;i<nb_operands;i++) {
1304 j = sorted_op[i];
1305 op = &operands[j];
1306 str = op->constraint;
1307 /* no need to allocate references */
1308 if (op->ref_index >= 0)
1309 continue;
1310 /* select if register is used for output, input or both */
1311 if (op->input_index >= 0) {
1312 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1313 } else if (j < nb_outputs) {
1314 reg_mask = REG_OUT_MASK;
1315 } else {
1316 reg_mask = REG_IN_MASK;
1317 }
1318 if (op->reg >= 0) {
1319 if (is_reg_allocated(op->reg))
1320 tcc_error("asm regvar requests register that's taken already");
1321 reg = op->reg;
1322 goto reg_found;
1323 }
1324 try_next:
1325 c = *str++;
1326 switch(c) {
1327 case '=':
1328 goto try_next;
1329 case '+':
1330 op->is_rw = 1;
1331 /* FALL THRU */
1332 case '&':
1333 if (j >= nb_outputs)
1334 tcc_error("'%c' modifier can only be applied to outputs", c);
1335 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1336 goto try_next;
1337 case 'A':
1338 /* allocate both eax and edx */
1339 if (is_reg_allocated(TREG_XAX) ||
1340 is_reg_allocated(TREG_XDX))
1341 goto try_next;
1342 op->is_llong = 1;
1343 op->reg = TREG_XAX;
1344 regs_allocated[TREG_XAX] |= reg_mask;
1345 regs_allocated[TREG_XDX] |= reg_mask;
1346 break;
1347 case 'a':
1348 reg = TREG_XAX;
1349 goto alloc_reg;
1350 case 'b':
1351 reg = 3;
1352 goto alloc_reg;
1353 case 'c':
1354 reg = TREG_XCX;
1355 goto alloc_reg;
1356 case 'd':
1357 reg = TREG_XDX;
1358 goto alloc_reg;
1359 case 'S':
1360 reg = 6;
1361 goto alloc_reg;
1362 case 'D':
1363 reg = 7;
1364 alloc_reg:
1365 if (is_reg_allocated(reg))
1366 goto try_next;
1367 goto reg_found;
1368 case 'q':
1369 /* eax, ebx, ecx or edx */
1370 for(reg = 0; reg < 4; reg++) {
1371 if (!is_reg_allocated(reg))
1372 goto reg_found;
1373 }
1374 goto try_next;
1375 case 'r':
1376 case 'R':
1377 case 'p': /* A general address, for x86(64) any register is acceptable*/
1378 /* any general register */
1379 for(reg = 0; reg < 8; reg++) {
1380 if (!is_reg_allocated(reg))
1381 goto reg_found;
1382 }
1383 goto try_next;
1384 reg_found:
1385 /* now we can reload in the register */
1386 op->is_llong = 0;
1387 op->reg = reg;
1388 regs_allocated[reg] |= reg_mask;
1389 break;
1390 case 'e':
1391 case 'i':
1392 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1393 goto try_next;
1394 break;
1395 case 'I':
1396 case 'N':
1397 case 'M':
1398 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1399 goto try_next;
1400 break;
1401 case 'm':
1402 case 'g':
1403 /* nothing special to do because the operand is already in
1404 memory, except if the pointer itself is stored in a
1405 memory variable (VT_LLOCAL case) */
1406 /* XXX: fix constant case */
1407 /* if it is a reference to a memory zone, it must lie
1408 in a register, so we reserve the register in the
1409 input registers and a load will be generated
1410 later */
1411 if (j < nb_outputs || c == 'm') {
1412 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1413 /* any general register */
1414 for(reg = 0; reg < 8; reg++) {
1415 if (!(regs_allocated[reg] & REG_IN_MASK))
1416 goto reg_found1;
1417 }
1418 goto try_next;
1419 reg_found1:
1420 /* now we can reload in the register */
1421 regs_allocated[reg] |= REG_IN_MASK;
1422 op->reg = reg;
1423 op->is_memory = 1;
1424 }
1425 }
1426 break;
1427 default:
1428 tcc_error("asm constraint %d ('%s') could not be satisfied",
1429 j, op->constraint);
1430 break;
1431 }
1432 /* if a reference is present for that operand, we assign it too */
1433 if (op->input_index >= 0) {
1434 operands[op->input_index].reg = op->reg;
1435 operands[op->input_index].is_llong = op->is_llong;
1436 }
1437 }
1438
1439 /* compute out_reg. It is used to store outputs registers to memory
1440 locations references by pointers (VT_LLOCAL case) */
1441 *pout_reg = -1;
1442 for(i=0;i<nb_operands;i++) {
1443 op = &operands[i];
1444 if (op->reg >= 0 &&
1445 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1446 !op->is_memory) {
1447 for(reg = 0; reg < 8; reg++) {
1448 if (!(regs_allocated[reg] & REG_OUT_MASK))
1449 goto reg_found2;
1450 }
1451 tcc_error("could not find free output register for reloading");
1452 reg_found2:
1453 *pout_reg = reg;
1454 break;
1455 }
1456 }
1457
1458 /* print sorted constraints */
1459 #ifdef ASM_DEBUG
1460 for(i=0;i<nb_operands;i++) {
1461 j = sorted_op[i];
1462 op = &operands[j];
1463 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1464 j,
1465 op->id ? get_tok_str(op->id, NULL) : "",
1466 op->constraint,
1467 op->vt->r,
1468 op->reg);
1469 }
1470 if (*pout_reg >= 0)
1471 printf("out_reg=%d\n", *pout_reg);
1472 #endif
1473 }
1474
1475 ST_FUNC void subst_asm_operand(CString *add_str,
1476 SValue *sv, int modifier)
1477 {
1478 int r, reg, size, val;
1479 char buf[64];
1480
1481 r = sv->r;
1482 if ((r & VT_VALMASK) == VT_CONST) {
1483 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n' &&
1484 modifier != 'P')
1485 cstr_ccat(add_str, '$');
1486 if (r & VT_SYM) {
1487 const char *name = get_tok_str(sv->sym->v, NULL);
1488 if (sv->sym->v >= SYM_FIRST_ANOM) {
1489 /* In case of anonymous symbols ("L.42", used
1490 for static data labels) we can't find them
1491 in the C symbol table when later looking up
1492 this name. So enter them now into the asm label
1493 list when we still know the symbol. */
1494 get_asm_sym(tok_alloc_const(name), sv->sym);
1495 }
1496 if (tcc_state->leading_underscore)
1497 cstr_ccat(add_str, '_');
1498 cstr_cat(add_str, name, -1);
1499 if ((uint32_t)sv->c.i == 0)
1500 goto no_offset;
1501 cstr_ccat(add_str, '+');
1502 }
1503 val = sv->c.i;
1504 if (modifier == 'n')
1505 val = -val;
1506 snprintf(buf, sizeof(buf), "%d", (int)sv->c.i);
1507 cstr_cat(add_str, buf, -1);
1508 no_offset:;
1509 #ifdef TCC_TARGET_X86_64
1510 if (r & VT_LVAL)
1511 cstr_cat(add_str, "(%rip)", -1);
1512 #endif
1513 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1514 #ifdef TCC_TARGET_X86_64
1515 snprintf(buf, sizeof(buf), "%d(%%rbp)", (int)sv->c.i);
1516 #else
1517 snprintf(buf, sizeof(buf), "%d(%%ebp)", (int)sv->c.i);
1518 #endif
1519 cstr_cat(add_str, buf, -1);
1520 } else if (r & VT_LVAL) {
1521 reg = r & VT_VALMASK;
1522 if (reg >= VT_CONST)
1523 tcc_internal_error("");
1524 snprintf(buf, sizeof(buf), "(%%%s)",
1525 #ifdef TCC_TARGET_X86_64
1526 get_tok_str(TOK_ASM_rax + reg, NULL)
1527 #else
1528 get_tok_str(TOK_ASM_eax + reg, NULL)
1529 #endif
1530 );
1531 cstr_cat(add_str, buf, -1);
1532 } else {
1533 /* register case */
1534 reg = r & VT_VALMASK;
1535 if (reg >= VT_CONST)
1536 tcc_internal_error("");
1537
1538 /* choose register operand size */
1539 if ((sv->type.t & VT_BTYPE) == VT_BYTE ||
1540 (sv->type.t & VT_BTYPE) == VT_BOOL)
1541 size = 1;
1542 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1543 size = 2;
1544 #ifdef TCC_TARGET_X86_64
1545 else if ((sv->type.t & VT_BTYPE) == VT_LLONG ||
1546 (sv->type.t & VT_BTYPE) == VT_PTR)
1547 size = 8;
1548 #endif
1549 else
1550 size = 4;
1551 if (size == 1 && reg >= 4)
1552 size = 4;
1553
1554 if (modifier == 'b') {
1555 if (reg >= 4)
1556 tcc_error("cannot use byte register");
1557 size = 1;
1558 } else if (modifier == 'h') {
1559 if (reg >= 4)
1560 tcc_error("cannot use byte register");
1561 size = -1;
1562 } else if (modifier == 'w') {
1563 size = 2;
1564 } else if (modifier == 'k') {
1565 size = 4;
1566 #ifdef TCC_TARGET_X86_64
1567 } else if (modifier == 'q') {
1568 size = 8;
1569 #endif
1570 }
1571
1572 switch(size) {
1573 case -1:
1574 reg = TOK_ASM_ah + reg;
1575 break;
1576 case 1:
1577 reg = TOK_ASM_al + reg;
1578 break;
1579 case 2:
1580 reg = TOK_ASM_ax + reg;
1581 break;
1582 default:
1583 reg = TOK_ASM_eax + reg;
1584 break;
1585 #ifdef TCC_TARGET_X86_64
1586 case 8:
1587 reg = TOK_ASM_rax + reg;
1588 break;
1589 #endif
1590 }
1591 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1592 cstr_cat(add_str, buf, -1);
1593 }
1594 }
1595
1596 /* generate prolog and epilog code for asm statement */
1597 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1598 int nb_outputs, int is_output,
1599 uint8_t *clobber_regs,
1600 int out_reg)
1601 {
1602 uint8_t regs_allocated[NB_ASM_REGS];
1603 ASMOperand *op;
1604 int i, reg;
1605
1606 /* Strictly speaking %Xbp and %Xsp should be included in the
1607 call-preserved registers, but currently it doesn't matter. */
1608 #ifdef TCC_TARGET_X86_64
1609 #ifdef TCC_TARGET_PE
1610 static const uint8_t reg_saved[] = { 3, 6, 7, 12, 13, 14, 15 };
1611 #else
1612 static const uint8_t reg_saved[] = { 3, 12, 13, 14, 15 };
1613 #endif
1614 #else
1615 static const uint8_t reg_saved[] = { 3, 6, 7 };
1616 #endif
1617
1618 /* mark all used registers */
1619 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1620 for(i = 0; i < nb_operands;i++) {
1621 op = &operands[i];
1622 if (op->reg >= 0)
1623 regs_allocated[op->reg] = 1;
1624 }
1625 if (!is_output) {
1626 /* generate reg save code */
1627 for(i = 0; i < sizeof(reg_saved)/sizeof(reg_saved[0]); i++) {
1628 reg = reg_saved[i];
1629 if (regs_allocated[reg]) {
1630 if (reg >= 8)
1631 g(0x41), reg-=8;
1632 g(0x50 + reg);
1633 }
1634 }
1635
1636 /* generate load code */
1637 for(i = 0; i < nb_operands; i++) {
1638 op = &operands[i];
1639 if (op->reg >= 0) {
1640 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1641 op->is_memory) {
1642 /* memory reference case (for both input and
1643 output cases) */
1644 SValue sv;
1645 sv = *op->vt;
1646 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
1647 sv.type.t = VT_PTR;
1648 load(op->reg, &sv);
1649 } else if (i >= nb_outputs || op->is_rw) {
1650 /* load value in register */
1651 load(op->reg, op->vt);
1652 if (op->is_llong) {
1653 SValue sv;
1654 sv = *op->vt;
1655 sv.c.i += 4;
1656 load(TREG_XDX, &sv);
1657 }
1658 }
1659 }
1660 }
1661 } else {
1662 /* generate save code */
1663 for(i = 0 ; i < nb_outputs; i++) {
1664 op = &operands[i];
1665 if (op->reg >= 0) {
1666 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1667 if (!op->is_memory) {
1668 SValue sv;
1669 sv = *op->vt;
1670 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1671 sv.type.t = VT_PTR;
1672 load(out_reg, &sv);
1673
1674 sv = *op->vt;
1675 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1676 store(op->reg, &sv);
1677 }
1678 } else {
1679 store(op->reg, op->vt);
1680 if (op->is_llong) {
1681 SValue sv;
1682 sv = *op->vt;
1683 sv.c.i += 4;
1684 store(TREG_XDX, &sv);
1685 }
1686 }
1687 }
1688 }
1689 /* generate reg restore code */
1690 for(i = sizeof(reg_saved)/sizeof(reg_saved[0]) - 1; i >= 0; i--) {
1691 reg = reg_saved[i];
1692 if (regs_allocated[reg]) {
1693 if (reg >= 8)
1694 g(0x41), reg-=8;
1695 g(0x58 + reg);
1696 }
1697 }
1698 }
1699 }
1700
1701 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1702 {
1703 int reg;
1704 #ifdef TCC_TARGET_X86_64
1705 unsigned int type;
1706 #endif
1707
1708 if (!strcmp(str, "memory") ||
1709 !strcmp(str, "cc") ||
1710 !strcmp(str, "flags"))
1711 return;
1712 reg = tok_alloc_const(str);
1713 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1714 reg -= TOK_ASM_eax;
1715 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1716 reg -= TOK_ASM_ax;
1717 #ifdef TCC_TARGET_X86_64
1718 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1719 reg -= TOK_ASM_rax;
1720 } else if ((reg = asm_parse_numeric_reg(reg, &type)) >= 0) {
1721 ;
1722 #endif
1723 } else {
1724 tcc_error("invalid clobber register '%s'", str);
1725 }
1726 clobber_regs[reg] = 1;
1727 }
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