Fix init bitfield padding with size 32/64
[tinycc.git] / x86_64-gen.c
blob0fe9ceeec93803d251126ea963a2a045387585db
1 /*
2 * x86-64 code generator for TCC
4 * Copyright (c) 2008 Shinichiro Hamaji
6 * Based on i386-gen.c by Fabrice Bellard
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifdef TARGET_DEFS_ONLY
25 /* number of available registers */
26 #define NB_REGS 25
27 #define NB_ASM_REGS 16
28 #define CONFIG_TCC_ASM
30 /* a register can belong to several classes. The classes must be
31 sorted from more general to more precise (see gv2() code which does
32 assumptions on it). */
33 #define RC_INT 0x0001 /* generic integer register */
34 #define RC_FLOAT 0x0002 /* generic float register */
35 #define RC_RAX 0x0004
36 #define RC_RCX 0x0008
37 #define RC_RDX 0x0010
38 #define RC_RSI 0x0020
39 #define RC_RDI 0x0040
40 #define RC_ST0 0x0080 /* only for long double */
41 #define RC_R8 0x0100
42 #define RC_R9 0x0200
43 #define RC_R10 0x0400
44 #define RC_R11 0x0800
45 #define RC_XMM0 0x1000
46 #define RC_XMM1 0x2000
47 #define RC_XMM2 0x4000
48 #define RC_XMM3 0x8000
49 #define RC_XMM4 0x10000
50 #define RC_XMM5 0x20000
51 #define RC_XMM6 0x40000
52 #define RC_XMM7 0x80000
53 #define RC_IRET RC_RAX /* function return: integer register */
54 #define RC_IRE2 RC_RDX /* function return: second integer register */
55 #define RC_FRET RC_XMM0 /* function return: float register */
56 #define RC_FRE2 RC_XMM1 /* function return: second float register */
58 /* pretty names for the registers */
59 enum {
60 TREG_RAX = 0,
61 TREG_RCX = 1,
62 TREG_RDX = 2,
63 TREG_RSP = 4,
64 TREG_RSI = 6,
65 TREG_RDI = 7,
67 TREG_R8 = 8,
68 TREG_R9 = 9,
69 TREG_R10 = 10,
70 TREG_R11 = 11,
72 TREG_XMM0 = 16,
73 TREG_XMM1 = 17,
74 TREG_XMM2 = 18,
75 TREG_XMM3 = 19,
76 TREG_XMM4 = 20,
77 TREG_XMM5 = 21,
78 TREG_XMM6 = 22,
79 TREG_XMM7 = 23,
81 TREG_ST0 = 24,
83 TREG_MEM = 0x20
86 #define REX_BASE(reg) (((reg) >> 3) & 1)
87 #define REG_VALUE(reg) ((reg) & 7)
89 /* return registers for function */
90 #define REG_IRET TREG_RAX /* single word int return register */
91 #define REG_IRE2 TREG_RDX /* second word return register (for long long) */
92 #define REG_FRET TREG_XMM0 /* float return register */
93 #define REG_FRE2 TREG_XMM1 /* second float return register */
95 /* defined if function parameters must be evaluated in reverse order */
96 #define INVERT_FUNC_PARAMS
98 /* pointer size, in bytes */
99 #define PTR_SIZE 8
101 /* long double size and alignment, in bytes */
102 #define LDOUBLE_SIZE 16
103 #define LDOUBLE_ALIGN 16
104 /* maximum alignment (for aligned attribute support) */
105 #define MAX_ALIGN 16
107 /* define if return values need to be extended explicitely
108 at caller side (for interfacing with non-TCC compilers) */
109 #define PROMOTE_RET
111 #define TCC_TARGET_NATIVE_STRUCT_COPY
112 ST_FUNC void gen_struct_copy(int size);
114 /******************************************************/
115 #else /* ! TARGET_DEFS_ONLY */
116 /******************************************************/
117 #define USING_GLOBALS
118 #include "tcc.h"
119 #include <assert.h>
121 ST_DATA const char * const target_machine_defs =
122 "__x86_64__\0"
123 "__amd64__\0"
126 ST_DATA const int reg_classes[NB_REGS] = {
127 /* eax */ RC_INT | RC_RAX,
128 /* ecx */ RC_INT | RC_RCX,
129 /* edx */ RC_INT | RC_RDX,
133 RC_RSI,
134 RC_RDI,
135 RC_R8,
136 RC_R9,
137 RC_R10,
138 RC_R11,
143 /* xmm0 */ RC_FLOAT | RC_XMM0,
144 /* xmm1 */ RC_FLOAT | RC_XMM1,
145 /* xmm2 */ RC_FLOAT | RC_XMM2,
146 /* xmm3 */ RC_FLOAT | RC_XMM3,
147 /* xmm4 */ RC_FLOAT | RC_XMM4,
148 /* xmm5 */ RC_FLOAT | RC_XMM5,
149 /* xmm6 an xmm7 are included so gv() can be used on them,
150 but they are not tagged with RC_FLOAT because they are
151 callee saved on Windows */
152 RC_XMM6,
153 RC_XMM7,
154 /* st0 */ RC_ST0
157 static unsigned long func_sub_sp_offset;
158 static int func_ret_sub;
160 #if defined(CONFIG_TCC_BCHECK)
161 static addr_t func_bound_offset;
162 static unsigned long func_bound_ind;
163 ST_DATA int func_bound_add_epilog;
164 #endif
166 #ifdef TCC_TARGET_PE
167 static int func_scratch, func_alloca;
168 #endif
170 /* XXX: make it faster ? */
171 ST_FUNC void g(int c)
173 int ind1;
174 if (nocode_wanted)
175 return;
176 ind1 = ind + 1;
177 if (ind1 > cur_text_section->data_allocated)
178 section_realloc(cur_text_section, ind1);
179 cur_text_section->data[ind] = c;
180 ind = ind1;
183 ST_FUNC void o(unsigned int c)
185 while (c) {
186 g(c);
187 c = c >> 8;
191 ST_FUNC void gen_le16(int v)
193 g(v);
194 g(v >> 8);
197 ST_FUNC void gen_le32(int c)
199 g(c);
200 g(c >> 8);
201 g(c >> 16);
202 g(c >> 24);
205 ST_FUNC void gen_le64(int64_t c)
207 g(c);
208 g(c >> 8);
209 g(c >> 16);
210 g(c >> 24);
211 g(c >> 32);
212 g(c >> 40);
213 g(c >> 48);
214 g(c >> 56);
217 static void orex(int ll, int r, int r2, int b)
219 if ((r & VT_VALMASK) >= VT_CONST)
220 r = 0;
221 if ((r2 & VT_VALMASK) >= VT_CONST)
222 r2 = 0;
223 if (ll || REX_BASE(r) || REX_BASE(r2))
224 o(0x40 | REX_BASE(r) | (REX_BASE(r2) << 2) | (ll << 3));
225 o(b);
228 /* output a symbol and patch all calls to it */
229 ST_FUNC void gsym_addr(int t, int a)
231 while (t) {
232 unsigned char *ptr = cur_text_section->data + t;
233 uint32_t n = read32le(ptr); /* next value */
234 write32le(ptr, a < 0 ? -a : a - t - 4);
235 t = n;
239 static int is64_type(int t)
241 return ((t & VT_BTYPE) == VT_PTR ||
242 (t & VT_BTYPE) == VT_FUNC ||
243 (t & VT_BTYPE) == VT_LLONG);
246 /* instruction + 4 bytes data. Return the address of the data */
247 static int oad(int c, int s)
249 int t;
250 if (nocode_wanted)
251 return s;
252 o(c);
253 t = ind;
254 gen_le32(s);
255 return t;
258 /* generate jmp to a label */
259 #define gjmp2(instr,lbl) oad(instr,lbl)
261 ST_FUNC void gen_addr32(int r, Sym *sym, int c)
263 if (r & VT_SYM)
264 greloca(cur_text_section, sym, ind, R_X86_64_32S, c), c=0;
265 gen_le32(c);
268 /* output constant with relocation if 'r & VT_SYM' is true */
269 ST_FUNC void gen_addr64(int r, Sym *sym, int64_t c)
271 if (r & VT_SYM)
272 greloca(cur_text_section, sym, ind, R_X86_64_64, c), c=0;
273 gen_le64(c);
276 /* output constant with relocation if 'r & VT_SYM' is true */
277 ST_FUNC void gen_addrpc32(int r, Sym *sym, int c)
279 if (r & VT_SYM)
280 greloca(cur_text_section, sym, ind, R_X86_64_PC32, c-4), c=4;
281 gen_le32(c-4);
284 /* output got address with relocation */
285 static void gen_gotpcrel(int r, Sym *sym, int c)
287 #ifdef TCC_TARGET_PE
288 tcc_error("internal error: no GOT on PE: %s %x %x | %02x %02x %02x\n",
289 get_tok_str(sym->v, NULL), c, r,
290 cur_text_section->data[ind-3],
291 cur_text_section->data[ind-2],
292 cur_text_section->data[ind-1]
294 #endif
295 greloca(cur_text_section, sym, ind, R_X86_64_GOTPCREL, -4);
296 gen_le32(0);
297 if (c) {
298 /* we use add c, %xxx for displacement */
299 orex(1, r, 0, 0x81);
300 o(0xc0 + REG_VALUE(r));
301 gen_le32(c);
305 static void gen_modrm_impl(int op_reg, int r, Sym *sym, int c, int is_got)
307 op_reg = REG_VALUE(op_reg) << 3;
308 if ((r & VT_VALMASK) == VT_CONST) {
309 /* constant memory reference */
310 if (!(r & VT_SYM)) {
311 /* Absolute memory reference */
312 o(0x04 | op_reg); /* [sib] | destreg */
313 oad(0x25, c); /* disp32 */
314 } else {
315 o(0x05 | op_reg); /* (%rip)+disp32 | destreg */
316 if (is_got) {
317 gen_gotpcrel(r, sym, c);
318 } else {
319 gen_addrpc32(r, sym, c);
322 } else if ((r & VT_VALMASK) == VT_LOCAL) {
323 /* currently, we use only ebp as base */
324 if (c == (char)c) {
325 /* short reference */
326 o(0x45 | op_reg);
327 g(c);
328 } else {
329 oad(0x85 | op_reg, c);
331 } else if ((r & VT_VALMASK) >= TREG_MEM) {
332 if (c) {
333 g(0x80 | op_reg | REG_VALUE(r));
334 gen_le32(c);
335 } else {
336 g(0x00 | op_reg | REG_VALUE(r));
338 } else {
339 g(0x00 | op_reg | REG_VALUE(r));
343 /* generate a modrm reference. 'op_reg' contains the additional 3
344 opcode bits */
345 static void gen_modrm(int op_reg, int r, Sym *sym, int c)
347 gen_modrm_impl(op_reg, r, sym, c, 0);
350 /* generate a modrm reference. 'op_reg' contains the additional 3
351 opcode bits */
352 static void gen_modrm64(int opcode, int op_reg, int r, Sym *sym, int c)
354 int is_got;
355 is_got = (op_reg & TREG_MEM) && !(sym->type.t & VT_STATIC);
356 orex(1, r, op_reg, opcode);
357 gen_modrm_impl(op_reg, r, sym, c, is_got);
361 /* load 'r' from value 'sv' */
362 void load(int r, SValue *sv)
364 int v, t, ft, fc, fr;
365 SValue v1;
367 #ifdef TCC_TARGET_PE
368 SValue v2;
369 sv = pe_getimport(sv, &v2);
370 #endif
372 fr = sv->r;
373 ft = sv->type.t & ~VT_DEFSIGN;
374 fc = sv->c.i;
375 if (fc != sv->c.i && (fr & VT_SYM))
376 tcc_error("64 bit addend in load");
378 ft &= ~(VT_VOLATILE | VT_CONSTANT);
380 #ifndef TCC_TARGET_PE
381 /* we use indirect access via got */
382 if ((fr & VT_VALMASK) == VT_CONST && (fr & VT_SYM) &&
383 (fr & VT_LVAL) && !(sv->sym->type.t & VT_STATIC)) {
384 /* use the result register as a temporal register */
385 int tr = r | TREG_MEM;
386 if (is_float(ft)) {
387 /* we cannot use float registers as a temporal register */
388 tr = get_reg(RC_INT) | TREG_MEM;
390 gen_modrm64(0x8b, tr, fr, sv->sym, 0);
392 /* load from the temporal register */
393 fr = tr | VT_LVAL;
395 #endif
397 v = fr & VT_VALMASK;
398 if (fr & VT_LVAL) {
399 int b, ll;
400 if (v == VT_LLOCAL) {
401 v1.type.t = VT_PTR;
402 v1.r = VT_LOCAL | VT_LVAL;
403 v1.c.i = fc;
404 fr = r;
405 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
406 fr = get_reg(RC_INT);
407 load(fr, &v1);
409 if (fc != sv->c.i) {
410 /* If the addends doesn't fit into a 32bit signed
411 we must use a 64bit move. We've checked above
412 that this doesn't have a sym associated. */
413 v1.type.t = VT_LLONG;
414 v1.r = VT_CONST;
415 v1.c.i = sv->c.i;
416 fr = r;
417 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
418 fr = get_reg(RC_INT);
419 load(fr, &v1);
420 fc = 0;
422 ll = 0;
423 /* Like GCC we can load from small enough properly sized
424 structs and unions as well.
425 XXX maybe move to generic operand handling, but should
426 occur only with asm, so tccasm.c might also be a better place */
427 if ((ft & VT_BTYPE) == VT_STRUCT) {
428 int align;
429 switch (type_size(&sv->type, &align)) {
430 case 1: ft = VT_BYTE; break;
431 case 2: ft = VT_SHORT; break;
432 case 4: ft = VT_INT; break;
433 case 8: ft = VT_LLONG; break;
434 default:
435 tcc_error("invalid aggregate type for register load");
436 break;
439 if ((ft & VT_BTYPE) == VT_FLOAT) {
440 b = 0x6e0f66;
441 r = REG_VALUE(r); /* movd */
442 } else if ((ft & VT_BTYPE) == VT_DOUBLE) {
443 b = 0x7e0ff3; /* movq */
444 r = REG_VALUE(r);
445 } else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
446 b = 0xdb, r = 5; /* fldt */
447 } else if ((ft & VT_TYPE) == VT_BYTE || (ft & VT_TYPE) == VT_BOOL) {
448 b = 0xbe0f; /* movsbl */
449 } else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
450 b = 0xb60f; /* movzbl */
451 } else if ((ft & VT_TYPE) == VT_SHORT) {
452 b = 0xbf0f; /* movswl */
453 } else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
454 b = 0xb70f; /* movzwl */
455 } else if ((ft & VT_TYPE) == (VT_VOID)) {
456 /* Can happen with zero size structs */
457 return;
458 } else {
459 assert(((ft & VT_BTYPE) == VT_INT)
460 || ((ft & VT_BTYPE) == VT_LLONG)
461 || ((ft & VT_BTYPE) == VT_PTR)
462 || ((ft & VT_BTYPE) == VT_FUNC)
464 ll = is64_type(ft);
465 b = 0x8b;
467 if (ll) {
468 gen_modrm64(b, r, fr, sv->sym, fc);
469 } else {
470 orex(ll, fr, r, b);
471 gen_modrm(r, fr, sv->sym, fc);
473 } else {
474 if (v == VT_CONST) {
475 if (fr & VT_SYM) {
476 #ifdef TCC_TARGET_PE
477 orex(1,0,r,0x8d);
478 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
479 gen_addrpc32(fr, sv->sym, fc);
480 #else
481 if (sv->sym->type.t & VT_STATIC) {
482 orex(1,0,r,0x8d);
483 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
484 gen_addrpc32(fr, sv->sym, fc);
485 } else {
486 orex(1,0,r,0x8b);
487 o(0x05 + REG_VALUE(r) * 8); /* mov xx(%rip), r */
488 gen_gotpcrel(r, sv->sym, fc);
490 #endif
491 } else if (is64_type(ft)) {
492 orex(1,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
493 gen_le64(sv->c.i);
494 } else {
495 orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
496 gen_le32(fc);
498 } else if (v == VT_LOCAL) {
499 orex(1,0,r,0x8d); /* lea xxx(%ebp), r */
500 gen_modrm(r, VT_LOCAL, sv->sym, fc);
501 } else if (v == VT_CMP) {
502 if (fc & 0x100)
504 v = vtop->cmp_r;
505 fc &= ~0x100;
506 /* This was a float compare. If the parity bit is
507 set the result was unordered, meaning false for everything
508 except TOK_NE, and true for TOK_NE. */
509 orex(0, r, 0, 0xb0 + REG_VALUE(r)); /* mov $0/1,%al */
510 g(v ^ fc ^ (v == TOK_NE));
511 o(0x037a + (REX_BASE(r) << 8));
513 orex(0,r,0, 0x0f); /* setxx %br */
514 o(fc);
515 o(0xc0 + REG_VALUE(r));
516 orex(0,r,0, 0x0f);
517 o(0xc0b6 + REG_VALUE(r) * 0x900); /* movzbl %al, %eax */
518 } else if (v == VT_JMP || v == VT_JMPI) {
519 t = v & 1;
520 orex(0,r,0,0);
521 oad(0xb8 + REG_VALUE(r), t); /* mov $1, r */
522 o(0x05eb + (REX_BASE(r) << 8)); /* jmp after */
523 gsym(fc);
524 orex(0,r,0,0);
525 oad(0xb8 + REG_VALUE(r), t ^ 1); /* mov $0, r */
526 } else if (v != r) {
527 if ((r >= TREG_XMM0) && (r <= TREG_XMM7)) {
528 if (v == TREG_ST0) {
529 /* gen_cvt_ftof(VT_DOUBLE); */
530 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
531 /* movsd -0x10(%rsp),%xmmN */
532 o(0x100ff2);
533 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
534 o(0xf024);
535 } else {
536 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
537 if ((ft & VT_BTYPE) == VT_FLOAT) {
538 o(0x100ff3);
539 } else {
540 assert((ft & VT_BTYPE) == VT_DOUBLE);
541 o(0x100ff2);
543 o(0xc0 + REG_VALUE(v) + REG_VALUE(r)*8);
545 } else if (r == TREG_ST0) {
546 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
547 /* gen_cvt_ftof(VT_LDOUBLE); */
548 /* movsd %xmmN,-0x10(%rsp) */
549 o(0x110ff2);
550 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
551 o(0xf024);
552 o(0xf02444dd); /* fldl -0x10(%rsp) */
553 } else {
554 orex(is64_type(ft), r, v, 0x89);
555 o(0xc0 + REG_VALUE(r) + REG_VALUE(v) * 8); /* mov v, r */
561 /* store register 'r' in lvalue 'v' */
562 void store(int r, SValue *v)
564 int fr, bt, ft, fc;
565 int op64 = 0;
566 /* store the REX prefix in this variable when PIC is enabled */
567 int pic = 0;
569 #ifdef TCC_TARGET_PE
570 SValue v2;
571 v = pe_getimport(v, &v2);
572 #endif
574 fr = v->r & VT_VALMASK;
575 ft = v->type.t;
576 fc = v->c.i;
577 if (fc != v->c.i && (fr & VT_SYM))
578 tcc_error("64 bit addend in store");
579 ft &= ~(VT_VOLATILE | VT_CONSTANT);
580 bt = ft & VT_BTYPE;
582 #ifndef TCC_TARGET_PE
583 /* we need to access the variable via got */
584 if (fr == VT_CONST
585 && (v->r & VT_SYM)
586 && !(v->sym->type.t & VT_STATIC)) {
587 /* mov xx(%rip), %r11 */
588 o(0x1d8b4c);
589 gen_gotpcrel(TREG_R11, v->sym, v->c.i);
590 pic = is64_type(bt) ? 0x49 : 0x41;
592 #endif
594 /* XXX: incorrect if float reg to reg */
595 if (bt == VT_FLOAT) {
596 o(0x66);
597 o(pic);
598 o(0x7e0f); /* movd */
599 r = REG_VALUE(r);
600 } else if (bt == VT_DOUBLE) {
601 o(0x66);
602 o(pic);
603 o(0xd60f); /* movq */
604 r = REG_VALUE(r);
605 } else if (bt == VT_LDOUBLE) {
606 o(0xc0d9); /* fld %st(0) */
607 o(pic);
608 o(0xdb); /* fstpt */
609 r = 7;
610 } else {
611 if (bt == VT_SHORT)
612 o(0x66);
613 o(pic);
614 if (bt == VT_BYTE || bt == VT_BOOL)
615 orex(0, 0, r, 0x88);
616 else if (is64_type(bt))
617 op64 = 0x89;
618 else
619 orex(0, 0, r, 0x89);
621 if (pic) {
622 /* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
623 if (op64)
624 o(op64);
625 o(3 + (r << 3));
626 } else if (op64) {
627 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
628 gen_modrm64(op64, r, v->r, v->sym, fc);
629 } else if (fr != r) {
630 orex(1, fr, r, op64);
631 o(0xc0 + fr + r * 8); /* mov r, fr */
633 } else {
634 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
635 gen_modrm(r, v->r, v->sym, fc);
636 } else if (fr != r) {
637 o(0xc0 + fr + r * 8); /* mov r, fr */
642 /* 'is_jmp' is '1' if it is a jump */
643 static void gcall_or_jmp(int is_jmp)
645 int r;
646 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
647 ((vtop->r & VT_SYM) && (vtop->c.i-4) == (int)(vtop->c.i-4))) {
648 /* constant symbolic case -> simple relocation */
649 #ifdef TCC_TARGET_PE
650 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PC32, (int)(vtop->c.i-4));
651 #else
652 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PLT32, (int)(vtop->c.i-4));
653 #endif
654 oad(0xe8 + is_jmp, 0); /* call/jmp im */
655 } else {
656 /* otherwise, indirect call */
657 r = TREG_R11;
658 load(r, vtop);
659 o(0x41); /* REX */
660 o(0xff); /* call/jmp *r */
661 o(0xd0 + REG_VALUE(r) + (is_jmp << 4));
665 #if defined(CONFIG_TCC_BCHECK)
667 static void gen_bounds_call(int v)
669 Sym *sym = external_helper_sym(v);
670 oad(0xe8, 0);
671 #ifdef TCC_TARGET_PE
672 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
673 #else
674 greloca(cur_text_section, sym, ind-4, R_X86_64_PLT32, -4);
675 #endif
678 #ifdef TCC_TARGET_PE
679 # define TREG_FASTCALL_1 TREG_RCX
680 #else
681 # define TREG_FASTCALL_1 TREG_RDI
682 #endif
684 static void gen_bounds_prolog(void)
686 /* leave some room for bound checking code */
687 func_bound_offset = lbounds_section->data_offset;
688 func_bound_ind = ind;
689 func_bound_add_epilog = 0;
690 o(0x0d8d48 + ((TREG_FASTCALL_1 == TREG_RDI) * 0x300000)); /*lbound section pointer */
691 gen_le32 (0);
692 oad(0xb8, 0); /* call to function */
695 static void gen_bounds_epilog(void)
697 addr_t saved_ind;
698 addr_t *bounds_ptr;
699 Sym *sym_data;
700 int offset_modified = func_bound_offset != lbounds_section->data_offset;
702 if (!offset_modified && !func_bound_add_epilog)
703 return;
705 /* add end of table info */
706 bounds_ptr = section_ptr_add(lbounds_section, sizeof(addr_t));
707 *bounds_ptr = 0;
709 sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
710 func_bound_offset, PTR_SIZE);
712 /* generate bound local allocation */
713 if (offset_modified) {
714 saved_ind = ind;
715 ind = func_bound_ind;
716 greloca(cur_text_section, sym_data, ind + 3, R_X86_64_PC32, -4);
717 ind = ind + 7;
718 gen_bounds_call(TOK___bound_local_new);
719 ind = saved_ind;
722 /* generate bound check local freeing */
723 o(0x5250); /* save returned value, if any */
724 o(0x20ec8348); /* sub $32,%rsp */
725 o(0x290f); /* movaps %xmm0,0x10(%rsp) */
726 o(0x102444);
727 o(0x240c290f); /* movaps %xmm1,(%rsp) */
728 greloca(cur_text_section, sym_data, ind + 3, R_X86_64_PC32, -4);
729 o(0x0d8d48 + ((TREG_FASTCALL_1 == TREG_RDI) * 0x300000)); /* lea xxx(%rip), %rcx/rdi */
730 gen_le32 (0);
731 gen_bounds_call(TOK___bound_local_delete);
732 o(0x280f); /* movaps 0x10(%rsp),%xmm0 */
733 o(0x102444);
734 o(0x240c280f); /* movaps (%rsp),%xmm1 */
735 o(0x20c48348); /* add $32,%rsp */
736 o(0x585a); /* restore returned value, if any */
738 #endif
740 #ifdef TCC_TARGET_PE
742 #define REGN 4
743 static const uint8_t arg_regs[REGN] = {
744 TREG_RCX, TREG_RDX, TREG_R8, TREG_R9
747 /* Prepare arguments in R10 and R11 rather than RCX and RDX
748 because gv() will not ever use these */
749 static int arg_prepare_reg(int idx) {
750 if (idx == 0 || idx == 1)
751 /* idx=0: r10, idx=1: r11 */
752 return idx + 10;
753 else
754 return idx >= 0 && idx < REGN ? arg_regs[idx] : 0;
757 /* Generate function call. The function address is pushed first, then
758 all the parameters in call order. This functions pops all the
759 parameters and the function address. */
761 static void gen_offs_sp(int b, int r, int d)
763 orex(1,0,r & 0x100 ? 0 : r, b);
764 if (d == (char)d) {
765 o(0x2444 | (REG_VALUE(r) << 3));
766 g(d);
767 } else {
768 o(0x2484 | (REG_VALUE(r) << 3));
769 gen_le32(d);
773 static int using_regs(int size)
775 return !(size > 8 || (size & (size - 1)));
778 /* Return the number of registers needed to return the struct, or 0 if
779 returning via struct pointer. */
780 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
782 int size, align;
783 *ret_align = 1; // Never have to re-align return values for x86-64
784 *regsize = 8;
785 size = type_size(vt, &align);
786 if (!using_regs(size))
787 return 0;
788 if (size == 8)
789 ret->t = VT_LLONG;
790 else if (size == 4)
791 ret->t = VT_INT;
792 else if (size == 2)
793 ret->t = VT_SHORT;
794 else
795 ret->t = VT_BYTE;
796 ret->ref = NULL;
797 return 1;
800 static int is_sse_float(int t) {
801 int bt;
802 bt = t & VT_BTYPE;
803 return bt == VT_DOUBLE || bt == VT_FLOAT;
806 static int gfunc_arg_size(CType *type) {
807 int align;
808 if (type->t & (VT_ARRAY|VT_BITFIELD))
809 return 8;
810 return type_size(type, &align);
813 void gfunc_call(int nb_args)
815 int size, r, args_size, i, d, bt, struct_size;
816 int arg;
818 #ifdef CONFIG_TCC_BCHECK
819 if (tcc_state->do_bounds_check)
820 gbound_args(nb_args);
821 #endif
823 args_size = (nb_args < REGN ? REGN : nb_args) * PTR_SIZE;
824 arg = nb_args;
826 /* for struct arguments, we need to call memcpy and the function
827 call breaks register passing arguments we are preparing.
828 So, we process arguments which will be passed by stack first. */
829 struct_size = args_size;
830 for(i = 0; i < nb_args; i++) {
831 SValue *sv;
833 --arg;
834 sv = &vtop[-i];
835 bt = (sv->type.t & VT_BTYPE);
836 size = gfunc_arg_size(&sv->type);
838 if (using_regs(size))
839 continue; /* arguments smaller than 8 bytes passed in registers or on stack */
841 if (bt == VT_STRUCT) {
842 /* align to stack align size */
843 size = (size + 15) & ~15;
844 /* generate structure store */
845 r = get_reg(RC_INT);
846 gen_offs_sp(0x8d, r, struct_size);
847 struct_size += size;
849 /* generate memcpy call */
850 vset(&sv->type, r | VT_LVAL, 0);
851 vpushv(sv);
852 vstore();
853 --vtop;
854 } else if (bt == VT_LDOUBLE) {
855 gv(RC_ST0);
856 gen_offs_sp(0xdb, 0x107, struct_size);
857 struct_size += 16;
861 if (func_scratch < struct_size)
862 func_scratch = struct_size;
864 arg = nb_args;
865 struct_size = args_size;
867 for(i = 0; i < nb_args; i++) {
868 --arg;
869 bt = (vtop->type.t & VT_BTYPE);
871 size = gfunc_arg_size(&vtop->type);
872 if (!using_regs(size)) {
873 /* align to stack align size */
874 size = (size + 15) & ~15;
875 if (arg >= REGN) {
876 d = get_reg(RC_INT);
877 gen_offs_sp(0x8d, d, struct_size);
878 gen_offs_sp(0x89, d, arg*8);
879 } else {
880 d = arg_prepare_reg(arg);
881 gen_offs_sp(0x8d, d, struct_size);
883 struct_size += size;
884 } else {
885 if (is_sse_float(vtop->type.t)) {
886 if (tcc_state->nosse)
887 tcc_error("SSE disabled");
888 if (arg >= REGN) {
889 gv(RC_XMM0);
890 /* movq %xmm0, j*8(%rsp) */
891 gen_offs_sp(0xd60f66, 0x100, arg*8);
892 } else {
893 /* Load directly to xmmN register */
894 gv(RC_XMM0 << arg);
895 d = arg_prepare_reg(arg);
896 /* mov %xmmN, %rxx */
897 o(0x66);
898 orex(1,d,0, 0x7e0f);
899 o(0xc0 + arg*8 + REG_VALUE(d));
901 } else {
902 if (bt == VT_STRUCT) {
903 vtop->type.ref = NULL;
904 vtop->type.t = size > 4 ? VT_LLONG : size > 2 ? VT_INT
905 : size > 1 ? VT_SHORT : VT_BYTE;
908 r = gv(RC_INT);
909 if (arg >= REGN) {
910 gen_offs_sp(0x89, r, arg*8);
911 } else {
912 d = arg_prepare_reg(arg);
913 orex(1,d,r,0x89); /* mov */
914 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
918 vtop--;
920 save_regs(0);
921 /* Copy R10 and R11 into RCX and RDX, respectively */
922 if (nb_args > 0) {
923 o(0xd1894c); /* mov %r10, %rcx */
924 if (nb_args > 1) {
925 o(0xda894c); /* mov %r11, %rdx */
929 gcall_or_jmp(0);
931 if ((vtop->r & VT_SYM) && vtop->sym->v == TOK_alloca) {
932 /* need to add the "func_scratch" area after alloca */
933 o(0x48); func_alloca = oad(0x05, func_alloca); /* add $NN, %rax */
934 #ifdef CONFIG_TCC_BCHECK
935 if (tcc_state->do_bounds_check)
936 gen_bounds_call(TOK___bound_alloca_nr); /* new region */
937 #endif
939 vtop--;
943 #define FUNC_PROLOG_SIZE 11
945 /* generate function prolog of type 't' */
946 void gfunc_prolog(Sym *func_sym)
948 CType *func_type = &func_sym->type;
949 int addr, reg_param_index, bt, size;
950 Sym *sym;
951 CType *type;
953 func_ret_sub = 0;
954 func_scratch = 32;
955 func_alloca = 0;
956 loc = 0;
958 addr = PTR_SIZE * 2;
959 ind += FUNC_PROLOG_SIZE;
960 func_sub_sp_offset = ind;
961 reg_param_index = 0;
963 sym = func_type->ref;
965 /* if the function returns a structure, then add an
966 implicit pointer parameter */
967 size = gfunc_arg_size(&func_vt);
968 if (!using_regs(size)) {
969 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
970 func_vc = addr;
971 reg_param_index++;
972 addr += 8;
975 /* define parameters */
976 while ((sym = sym->next) != NULL) {
977 type = &sym->type;
978 bt = type->t & VT_BTYPE;
979 size = gfunc_arg_size(type);
980 if (!using_regs(size)) {
981 if (reg_param_index < REGN) {
982 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
984 sym_push(sym->v & ~SYM_FIELD, type,
985 VT_LLOCAL | VT_LVAL, addr);
986 } else {
987 if (reg_param_index < REGN) {
988 /* save arguments passed by register */
989 if ((bt == VT_FLOAT) || (bt == VT_DOUBLE)) {
990 if (tcc_state->nosse)
991 tcc_error("SSE disabled");
992 o(0xd60f66); /* movq */
993 gen_modrm(reg_param_index, VT_LOCAL, NULL, addr);
994 } else {
995 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
998 sym_push(sym->v & ~SYM_FIELD, type,
999 VT_LOCAL | VT_LVAL, addr);
1001 addr += 8;
1002 reg_param_index++;
1005 while (reg_param_index < REGN) {
1006 if (func_var) {
1007 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
1008 addr += 8;
1010 reg_param_index++;
1012 #ifdef CONFIG_TCC_BCHECK
1013 if (tcc_state->do_bounds_check)
1014 gen_bounds_prolog();
1015 #endif
1018 /* generate function epilog */
1019 void gfunc_epilog(void)
1021 int v, saved_ind;
1023 /* align local size to word & save local variables */
1024 func_scratch = (func_scratch + 15) & -16;
1025 loc = (loc & -16) - func_scratch;
1027 #ifdef CONFIG_TCC_BCHECK
1028 if (tcc_state->do_bounds_check)
1029 gen_bounds_epilog();
1030 #endif
1032 o(0xc9); /* leave */
1033 if (func_ret_sub == 0) {
1034 o(0xc3); /* ret */
1035 } else {
1036 o(0xc2); /* ret n */
1037 g(func_ret_sub);
1038 g(func_ret_sub >> 8);
1041 saved_ind = ind;
1042 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1043 v = -loc;
1045 if (v >= 4096) {
1046 Sym *sym = external_helper_sym(TOK___chkstk);
1047 oad(0xb8, v); /* mov stacksize, %eax */
1048 oad(0xe8, 0); /* call __chkstk, (does the stackframe too) */
1049 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
1050 o(0x90); /* fill for FUNC_PROLOG_SIZE = 11 bytes */
1051 } else {
1052 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1053 o(0xec8148); /* sub rsp, stacksize */
1054 gen_le32(v);
1057 /* add the "func_scratch" area after each alloca seen */
1058 gsym_addr(func_alloca, -func_scratch);
1060 cur_text_section->data_offset = saved_ind;
1061 pe_add_unwind_data(ind, saved_ind, v);
1062 ind = cur_text_section->data_offset;
1065 #else
1067 static void gadd_sp(int val)
1069 if (val == (char)val) {
1070 o(0xc48348);
1071 g(val);
1072 } else {
1073 oad(0xc48148, val); /* add $xxx, %rsp */
1077 typedef enum X86_64_Mode {
1078 x86_64_mode_none,
1079 x86_64_mode_memory,
1080 x86_64_mode_integer,
1081 x86_64_mode_sse,
1082 x86_64_mode_x87
1083 } X86_64_Mode;
1085 static X86_64_Mode classify_x86_64_merge(X86_64_Mode a, X86_64_Mode b)
1087 if (a == b)
1088 return a;
1089 else if (a == x86_64_mode_none)
1090 return b;
1091 else if (b == x86_64_mode_none)
1092 return a;
1093 else if ((a == x86_64_mode_memory) || (b == x86_64_mode_memory))
1094 return x86_64_mode_memory;
1095 else if ((a == x86_64_mode_integer) || (b == x86_64_mode_integer))
1096 return x86_64_mode_integer;
1097 else if ((a == x86_64_mode_x87) || (b == x86_64_mode_x87))
1098 return x86_64_mode_memory;
1099 else
1100 return x86_64_mode_sse;
1103 static X86_64_Mode classify_x86_64_inner(CType *ty)
1105 X86_64_Mode mode;
1106 Sym *f;
1108 switch (ty->t & VT_BTYPE) {
1109 case VT_VOID: return x86_64_mode_none;
1111 case VT_INT:
1112 case VT_BYTE:
1113 case VT_SHORT:
1114 case VT_LLONG:
1115 case VT_BOOL:
1116 case VT_PTR:
1117 case VT_FUNC:
1118 return x86_64_mode_integer;
1120 case VT_FLOAT:
1121 case VT_DOUBLE: return x86_64_mode_sse;
1123 case VT_LDOUBLE: return x86_64_mode_x87;
1125 case VT_STRUCT:
1126 f = ty->ref;
1128 mode = x86_64_mode_none;
1129 for (f = f->next; f; f = f->next)
1130 mode = classify_x86_64_merge(mode, classify_x86_64_inner(&f->type));
1132 return mode;
1134 assert(0);
1135 return 0;
1138 static X86_64_Mode classify_x86_64_arg(CType *ty, CType *ret, int *psize, int *palign, int *reg_count)
1140 X86_64_Mode mode;
1141 int size, align, ret_t = 0;
1143 if (ty->t & (VT_BITFIELD|VT_ARRAY)) {
1144 *psize = 8;
1145 *palign = 8;
1146 *reg_count = 1;
1147 ret_t = ty->t;
1148 mode = x86_64_mode_integer;
1149 } else {
1150 size = type_size(ty, &align);
1151 *psize = (size + 7) & ~7;
1152 *palign = (align + 7) & ~7;
1153 *reg_count = 0; /* avoid compiler warning */
1155 if (size > 16) {
1156 mode = x86_64_mode_memory;
1157 } else {
1158 mode = classify_x86_64_inner(ty);
1159 switch (mode) {
1160 case x86_64_mode_integer:
1161 if (size > 8) {
1162 *reg_count = 2;
1163 ret_t = VT_QLONG;
1164 } else {
1165 *reg_count = 1;
1166 if (size > 4)
1167 ret_t = VT_LLONG;
1168 else if (size > 2)
1169 ret_t = VT_INT;
1170 else if (size > 1)
1171 ret_t = VT_SHORT;
1172 else
1173 ret_t = VT_BYTE;
1174 if ((ty->t & VT_BTYPE) == VT_STRUCT || (ty->t & VT_UNSIGNED))
1175 ret_t |= VT_UNSIGNED;
1177 break;
1179 case x86_64_mode_x87:
1180 *reg_count = 1;
1181 ret_t = VT_LDOUBLE;
1182 break;
1184 case x86_64_mode_sse:
1185 if (size > 8) {
1186 *reg_count = 2;
1187 ret_t = VT_QFLOAT;
1188 } else {
1189 *reg_count = 1;
1190 ret_t = (size > 4) ? VT_DOUBLE : VT_FLOAT;
1192 break;
1193 default: break; /* nothing to be done for x86_64_mode_memory and x86_64_mode_none*/
1198 if (ret) {
1199 ret->ref = NULL;
1200 ret->t = ret_t;
1203 return mode;
1206 ST_FUNC int classify_x86_64_va_arg(CType *ty)
1208 /* This definition must be synced with stdarg.h */
1209 enum __va_arg_type {
1210 __va_gen_reg, __va_float_reg, __va_stack
1212 int size, align, reg_count;
1213 X86_64_Mode mode = classify_x86_64_arg(ty, NULL, &size, &align, &reg_count);
1214 switch (mode) {
1215 default: return __va_stack;
1216 case x86_64_mode_integer: return __va_gen_reg;
1217 case x86_64_mode_sse: return __va_float_reg;
1221 /* Return the number of registers needed to return the struct, or 0 if
1222 returning via struct pointer. */
1223 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
1225 int size, align, reg_count;
1226 *ret_align = 1; // Never have to re-align return values for x86-64
1227 *regsize = 8;
1228 return (classify_x86_64_arg(vt, ret, &size, &align, &reg_count) != x86_64_mode_memory);
1231 #define REGN 6
1232 static const uint8_t arg_regs[REGN] = {
1233 TREG_RDI, TREG_RSI, TREG_RDX, TREG_RCX, TREG_R8, TREG_R9
1236 static int arg_prepare_reg(int idx) {
1237 if (idx == 2 || idx == 3)
1238 /* idx=2: r10, idx=3: r11 */
1239 return idx + 8;
1240 else
1241 return idx >= 0 && idx < REGN ? arg_regs[idx] : 0;
1244 /* Generate function call. The function address is pushed first, then
1245 all the parameters in call order. This functions pops all the
1246 parameters and the function address. */
1247 void gfunc_call(int nb_args)
1249 X86_64_Mode mode;
1250 CType type;
1251 int size, align, r, args_size, stack_adjust, i, reg_count, k;
1252 int nb_reg_args = 0;
1253 int nb_sse_args = 0;
1254 int sse_reg, gen_reg;
1255 char *onstack = tcc_malloc((nb_args + 1) * sizeof (char));
1257 #ifdef CONFIG_TCC_BCHECK
1258 if (tcc_state->do_bounds_check)
1259 gbound_args(nb_args);
1260 #endif
1262 /* calculate the number of integer/float register arguments, remember
1263 arguments to be passed via stack (in onstack[]), and also remember
1264 if we have to align the stack pointer to 16 (onstack[i] == 2). Needs
1265 to be done in a left-to-right pass over arguments. */
1266 stack_adjust = 0;
1267 for(i = nb_args - 1; i >= 0; i--) {
1268 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1269 if (size == 0) continue;
1270 if (mode == x86_64_mode_sse && nb_sse_args + reg_count <= 8) {
1271 nb_sse_args += reg_count;
1272 onstack[i] = 0;
1273 } else if (mode == x86_64_mode_integer && nb_reg_args + reg_count <= REGN) {
1274 nb_reg_args += reg_count;
1275 onstack[i] = 0;
1276 } else if (mode == x86_64_mode_none) {
1277 onstack[i] = 0;
1278 } else {
1279 if (align == 16 && (stack_adjust &= 15)) {
1280 onstack[i] = 2;
1281 stack_adjust = 0;
1282 } else
1283 onstack[i] = 1;
1284 stack_adjust += size;
1288 if (nb_sse_args && tcc_state->nosse)
1289 tcc_error("SSE disabled but floating point arguments passed");
1291 /* fetch cpu flag before generating any code */
1292 if ((vtop->r & VT_VALMASK) == VT_CMP)
1293 gv(RC_INT);
1295 /* for struct arguments, we need to call memcpy and the function
1296 call breaks register passing arguments we are preparing.
1297 So, we process arguments which will be passed by stack first. */
1298 gen_reg = nb_reg_args;
1299 sse_reg = nb_sse_args;
1300 args_size = 0;
1301 stack_adjust &= 15;
1302 for (i = k = 0; i < nb_args;) {
1303 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1304 if (size) {
1305 if (!onstack[i + k]) {
1306 ++i;
1307 continue;
1309 /* Possibly adjust stack to align SSE boundary. We're processing
1310 args from right to left while allocating happens left to right
1311 (stack grows down), so the adjustment needs to happen _after_
1312 an argument that requires it. */
1313 if (stack_adjust) {
1314 o(0x50); /* push %rax; aka sub $8,%rsp */
1315 args_size += 8;
1316 stack_adjust = 0;
1318 if (onstack[i + k] == 2)
1319 stack_adjust = 1;
1322 vrotb(i+1);
1324 switch (vtop->type.t & VT_BTYPE) {
1325 case VT_STRUCT:
1326 /* allocate the necessary size on stack */
1327 o(0x48);
1328 oad(0xec81, size); /* sub $xxx, %rsp */
1329 /* generate structure store */
1330 r = get_reg(RC_INT);
1331 orex(1, r, 0, 0x89); /* mov %rsp, r */
1332 o(0xe0 + REG_VALUE(r));
1333 vset(&vtop->type, r | VT_LVAL, 0);
1334 vswap();
1335 /* keep stack aligned for (__bound_)memmove call */
1336 o(0x10ec8348); /* sub $16,%rsp */
1337 o(0xf0e48348); /* and $-16,%rsp */
1338 orex(0,r,0,0x50 + REG_VALUE(r)); /* push r (last %rsp) */
1339 o(0x08ec8348); /* sub $8,%rsp */
1340 vstore();
1341 o(0x08c48348); /* add $8,%rsp */
1342 o(0x5c); /* pop %rsp */
1343 break;
1345 case VT_LDOUBLE:
1346 gv(RC_ST0);
1347 oad(0xec8148, size); /* sub $xxx, %rsp */
1348 o(0x7cdb); /* fstpt 0(%rsp) */
1349 g(0x24);
1350 g(0x00);
1351 break;
1353 case VT_FLOAT:
1354 case VT_DOUBLE:
1355 assert(mode == x86_64_mode_sse);
1356 r = gv(RC_FLOAT);
1357 o(0x50); /* push $rax */
1358 /* movq %xmmN, (%rsp) */
1359 o(0xd60f66);
1360 o(0x04 + REG_VALUE(r)*8);
1361 o(0x24);
1362 break;
1364 default:
1365 assert(mode == x86_64_mode_integer);
1366 /* simple type */
1367 /* XXX: implicit cast ? */
1368 r = gv(RC_INT);
1369 orex(0,r,0,0x50 + REG_VALUE(r)); /* push r */
1370 break;
1372 args_size += size;
1374 vpop();
1375 --nb_args;
1376 k++;
1379 tcc_free(onstack);
1381 /* XXX This should be superfluous. */
1382 save_regs(0); /* save used temporary registers */
1384 /* then, we prepare register passing arguments.
1385 Note that we cannot set RDX and RCX in this loop because gv()
1386 may break these temporary registers. Let's use R10 and R11
1387 instead of them */
1388 assert(gen_reg <= REGN);
1389 assert(sse_reg <= 8);
1390 for(i = 0; i < nb_args; i++) {
1391 mode = classify_x86_64_arg(&vtop->type, &type, &size, &align, &reg_count);
1392 if (size == 0) continue;
1393 /* Alter stack entry type so that gv() knows how to treat it */
1394 vtop->type = type;
1395 if (mode == x86_64_mode_sse) {
1396 if (reg_count == 2) {
1397 sse_reg -= 2;
1398 gv(RC_FRET); /* Use pair load into xmm0 & xmm1 */
1399 if (sse_reg) { /* avoid redundant movaps %xmm0, %xmm0 */
1400 /* movaps %xmm1, %xmmN */
1401 o(0x280f);
1402 o(0xc1 + ((sse_reg+1) << 3));
1403 /* movaps %xmm0, %xmmN */
1404 o(0x280f);
1405 o(0xc0 + (sse_reg << 3));
1407 } else {
1408 assert(reg_count == 1);
1409 --sse_reg;
1410 /* Load directly to register */
1411 gv(RC_XMM0 << sse_reg);
1413 } else if (mode == x86_64_mode_integer) {
1414 /* simple type */
1415 /* XXX: implicit cast ? */
1416 int d;
1417 gen_reg -= reg_count;
1418 r = gv(RC_INT);
1419 d = arg_prepare_reg(gen_reg);
1420 orex(1,d,r,0x89); /* mov */
1421 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
1422 if (reg_count == 2) {
1423 d = arg_prepare_reg(gen_reg+1);
1424 orex(1,d,vtop->r2,0x89); /* mov */
1425 o(0xc0 + REG_VALUE(vtop->r2) * 8 + REG_VALUE(d));
1428 vtop--;
1430 assert(gen_reg == 0);
1431 assert(sse_reg == 0);
1433 /* We shouldn't have many operands on the stack anymore, but the
1434 call address itself is still there, and it might be in %eax
1435 (or edx/ecx) currently, which the below writes would clobber.
1436 So evict all remaining operands here. */
1437 save_regs(0);
1439 /* Copy R10 and R11 into RDX and RCX, respectively */
1440 if (nb_reg_args > 2) {
1441 o(0xd2894c); /* mov %r10, %rdx */
1442 if (nb_reg_args > 3) {
1443 o(0xd9894c); /* mov %r11, %rcx */
1447 if (vtop->type.ref->f.func_type != FUNC_NEW) /* implies FUNC_OLD or FUNC_ELLIPSIS */
1448 oad(0xb8, nb_sse_args < 8 ? nb_sse_args : 8); /* mov nb_sse_args, %eax */
1449 gcall_or_jmp(0);
1450 if (args_size)
1451 gadd_sp(args_size);
1452 vtop--;
1455 #define FUNC_PROLOG_SIZE 11
1457 static void push_arg_reg(int i) {
1458 loc -= 8;
1459 gen_modrm64(0x89, arg_regs[i], VT_LOCAL, NULL, loc);
1462 /* generate function prolog of type 't' */
1463 void gfunc_prolog(Sym *func_sym)
1465 CType *func_type = &func_sym->type;
1466 X86_64_Mode mode, ret_mode;
1467 int i, addr, align, size, reg_count;
1468 int param_addr = 0, reg_param_index, sse_param_index;
1469 Sym *sym;
1470 CType *type;
1472 sym = func_type->ref;
1473 addr = PTR_SIZE * 2;
1474 loc = 0;
1475 ind += FUNC_PROLOG_SIZE;
1476 func_sub_sp_offset = ind;
1477 func_ret_sub = 0;
1478 ret_mode = classify_x86_64_arg(&func_vt, NULL, &size, &align, &reg_count);
1480 if (func_var) {
1481 int seen_reg_num, seen_sse_num, seen_stack_size;
1482 seen_reg_num = ret_mode == x86_64_mode_memory;
1483 seen_sse_num = 0;
1484 /* frame pointer and return address */
1485 seen_stack_size = PTR_SIZE * 2;
1486 /* count the number of seen parameters */
1487 sym = func_type->ref;
1488 while ((sym = sym->next) != NULL) {
1489 type = &sym->type;
1490 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1491 switch (mode) {
1492 default:
1493 stack_arg:
1494 seen_stack_size = ((seen_stack_size + align - 1) & -align) + size;
1495 break;
1497 case x86_64_mode_integer:
1498 if (seen_reg_num + reg_count > REGN)
1499 goto stack_arg;
1500 seen_reg_num += reg_count;
1501 break;
1503 case x86_64_mode_sse:
1504 if (seen_sse_num + reg_count > 8)
1505 goto stack_arg;
1506 seen_sse_num += reg_count;
1507 break;
1511 loc -= 24;
1512 /* movl $0x????????, -0x18(%rbp) */
1513 o(0xe845c7);
1514 gen_le32(seen_reg_num * 8);
1515 /* movl $0x????????, -0x14(%rbp) */
1516 o(0xec45c7);
1517 gen_le32(seen_sse_num * 16 + 48);
1518 /* leaq $0x????????, %r11 */
1519 o(0x9d8d4c);
1520 gen_le32(seen_stack_size);
1521 /* movq %r11, -0x10(%rbp) */
1522 o(0xf05d894c);
1523 /* leaq $-192(%rbp), %r11 */
1524 o(0x9d8d4c);
1525 gen_le32(-176 - 24);
1526 /* movq %r11, -0x8(%rbp) */
1527 o(0xf85d894c);
1529 /* save all register passing arguments */
1530 for (i = 0; i < 8; i++) {
1531 loc -= 16;
1532 if (!tcc_state->nosse) {
1533 o(0xd60f66); /* movq */
1534 gen_modrm(7 - i, VT_LOCAL, NULL, loc);
1536 /* movq $0, loc+8(%rbp) */
1537 o(0x85c748);
1538 gen_le32(loc + 8);
1539 gen_le32(0);
1541 for (i = 0; i < REGN; i++) {
1542 push_arg_reg(REGN-1-i);
1546 sym = func_type->ref;
1547 reg_param_index = 0;
1548 sse_param_index = 0;
1550 /* if the function returns a structure, then add an
1551 implicit pointer parameter */
1552 if (ret_mode == x86_64_mode_memory) {
1553 push_arg_reg(reg_param_index);
1554 func_vc = loc;
1555 reg_param_index++;
1557 /* define parameters */
1558 while ((sym = sym->next) != NULL) {
1559 type = &sym->type;
1560 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1561 switch (mode) {
1562 case x86_64_mode_sse:
1563 if (tcc_state->nosse)
1564 tcc_error("SSE disabled but floating point arguments used");
1565 if (sse_param_index + reg_count <= 8) {
1566 /* save arguments passed by register */
1567 loc -= reg_count * 8;
1568 param_addr = loc;
1569 for (i = 0; i < reg_count; ++i) {
1570 o(0xd60f66); /* movq */
1571 gen_modrm(sse_param_index, VT_LOCAL, NULL, param_addr + i*8);
1572 ++sse_param_index;
1574 } else {
1575 addr = (addr + align - 1) & -align;
1576 param_addr = addr;
1577 addr += size;
1579 break;
1581 case x86_64_mode_memory:
1582 case x86_64_mode_x87:
1583 addr = (addr + align - 1) & -align;
1584 param_addr = addr;
1585 addr += size;
1586 break;
1588 case x86_64_mode_integer: {
1589 if (reg_param_index + reg_count <= REGN) {
1590 /* save arguments passed by register */
1591 loc -= reg_count * 8;
1592 param_addr = loc;
1593 for (i = 0; i < reg_count; ++i) {
1594 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, param_addr + i*8);
1595 ++reg_param_index;
1597 } else {
1598 addr = (addr + align - 1) & -align;
1599 param_addr = addr;
1600 addr += size;
1602 break;
1604 default: break; /* nothing to be done for x86_64_mode_none */
1606 sym_push(sym->v & ~SYM_FIELD, type,
1607 VT_LOCAL | VT_LVAL, param_addr);
1610 #ifdef CONFIG_TCC_BCHECK
1611 if (tcc_state->do_bounds_check)
1612 gen_bounds_prolog();
1613 #endif
1616 /* generate function epilog */
1617 void gfunc_epilog(void)
1619 int v, saved_ind;
1621 #ifdef CONFIG_TCC_BCHECK
1622 if (tcc_state->do_bounds_check)
1623 gen_bounds_epilog();
1624 #endif
1625 o(0xc9); /* leave */
1626 if (func_ret_sub == 0) {
1627 o(0xc3); /* ret */
1628 } else {
1629 o(0xc2); /* ret n */
1630 g(func_ret_sub);
1631 g(func_ret_sub >> 8);
1633 /* align local size to word & save local variables */
1634 v = (-loc + 15) & -16;
1635 saved_ind = ind;
1636 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1637 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1638 o(0xec8148); /* sub rsp, stacksize */
1639 gen_le32(v);
1640 ind = saved_ind;
1643 #endif /* not PE */
1645 ST_FUNC void gen_fill_nops(int bytes)
1647 while (bytes--)
1648 g(0x90);
1651 /* generate a jump to a label */
1652 int gjmp(int t)
1654 return gjmp2(0xe9, t);
1657 /* generate a jump to a fixed address */
1658 void gjmp_addr(int a)
1660 int r;
1661 r = a - ind - 2;
1662 if (r == (char)r) {
1663 g(0xeb);
1664 g(r);
1665 } else {
1666 oad(0xe9, a - ind - 5);
1670 ST_FUNC int gjmp_append(int n, int t)
1672 void *p;
1673 /* insert vtop->c jump list in t */
1674 if (n) {
1675 uint32_t n1 = n, n2;
1676 while ((n2 = read32le(p = cur_text_section->data + n1)))
1677 n1 = n2;
1678 write32le(p, t);
1679 t = n;
1681 return t;
1684 ST_FUNC int gjmp_cond(int op, int t)
1686 if (op & 0x100)
1688 /* This was a float compare. If the parity flag is set
1689 the result was unordered. For anything except != this
1690 means false and we don't jump (anding both conditions).
1691 For != this means true (oring both).
1692 Take care about inverting the test. We need to jump
1693 to our target if the result was unordered and test wasn't NE,
1694 otherwise if unordered we don't want to jump. */
1695 int v = vtop->cmp_r;
1696 op &= ~0x100;
1697 if (op ^ v ^ (v != TOK_NE))
1698 o(0x067a); /* jp +6 */
1699 else
1701 g(0x0f);
1702 t = gjmp2(0x8a, t); /* jp t */
1705 g(0x0f);
1706 t = gjmp2(op - 16, t);
1707 return t;
1710 /* generate an integer binary operation */
1711 void gen_opi(int op)
1713 int r, fr, opc, c;
1714 int ll, uu, cc;
1716 ll = is64_type(vtop[-1].type.t);
1717 uu = (vtop[-1].type.t & VT_UNSIGNED) != 0;
1718 cc = (vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST;
1720 switch(op) {
1721 case '+':
1722 case TOK_ADDC1: /* add with carry generation */
1723 opc = 0;
1724 gen_op8:
1725 if (cc && (!ll || (int)vtop->c.i == vtop->c.i)) {
1726 /* constant case */
1727 vswap();
1728 r = gv(RC_INT);
1729 vswap();
1730 c = vtop->c.i;
1731 if (c == (char)c) {
1732 /* XXX: generate inc and dec for smaller code ? */
1733 orex(ll, r, 0, 0x83);
1734 o(0xc0 | (opc << 3) | REG_VALUE(r));
1735 g(c);
1736 } else {
1737 orex(ll, r, 0, 0x81);
1738 oad(0xc0 | (opc << 3) | REG_VALUE(r), c);
1740 } else {
1741 gv2(RC_INT, RC_INT);
1742 r = vtop[-1].r;
1743 fr = vtop[0].r;
1744 orex(ll, r, fr, (opc << 3) | 0x01);
1745 o(0xc0 + REG_VALUE(r) + REG_VALUE(fr) * 8);
1747 vtop--;
1748 if (op >= TOK_ULT && op <= TOK_GT)
1749 vset_VT_CMP(op);
1750 break;
1751 case '-':
1752 case TOK_SUBC1: /* sub with carry generation */
1753 opc = 5;
1754 goto gen_op8;
1755 case TOK_ADDC2: /* add with carry use */
1756 opc = 2;
1757 goto gen_op8;
1758 case TOK_SUBC2: /* sub with carry use */
1759 opc = 3;
1760 goto gen_op8;
1761 case '&':
1762 opc = 4;
1763 goto gen_op8;
1764 case '^':
1765 opc = 6;
1766 goto gen_op8;
1767 case '|':
1768 opc = 1;
1769 goto gen_op8;
1770 case '*':
1771 gv2(RC_INT, RC_INT);
1772 r = vtop[-1].r;
1773 fr = vtop[0].r;
1774 orex(ll, fr, r, 0xaf0f); /* imul fr, r */
1775 o(0xc0 + REG_VALUE(fr) + REG_VALUE(r) * 8);
1776 vtop--;
1777 break;
1778 case TOK_SHL:
1779 opc = 4;
1780 goto gen_shift;
1781 case TOK_SHR:
1782 opc = 5;
1783 goto gen_shift;
1784 case TOK_SAR:
1785 opc = 7;
1786 gen_shift:
1787 opc = 0xc0 | (opc << 3);
1788 if (cc) {
1789 /* constant case */
1790 vswap();
1791 r = gv(RC_INT);
1792 vswap();
1793 orex(ll, r, 0, 0xc1); /* shl/shr/sar $xxx, r */
1794 o(opc | REG_VALUE(r));
1795 g(vtop->c.i & (ll ? 63 : 31));
1796 } else {
1797 /* we generate the shift in ecx */
1798 gv2(RC_INT, RC_RCX);
1799 r = vtop[-1].r;
1800 orex(ll, r, 0, 0xd3); /* shl/shr/sar %cl, r */
1801 o(opc | REG_VALUE(r));
1803 vtop--;
1804 break;
1805 case TOK_UDIV:
1806 case TOK_UMOD:
1807 uu = 1;
1808 goto divmod;
1809 case '/':
1810 case '%':
1811 case TOK_PDIV:
1812 uu = 0;
1813 divmod:
1814 /* first operand must be in eax */
1815 /* XXX: need better constraint for second operand */
1816 gv2(RC_RAX, RC_RCX);
1817 r = vtop[-1].r;
1818 fr = vtop[0].r;
1819 vtop--;
1820 save_reg(TREG_RDX);
1821 orex(ll, 0, 0, uu ? 0xd231 : 0x99); /* xor %edx,%edx : cqto */
1822 orex(ll, fr, 0, 0xf7); /* div fr, %eax */
1823 o((uu ? 0xf0 : 0xf8) + REG_VALUE(fr));
1824 if (op == '%' || op == TOK_UMOD)
1825 r = TREG_RDX;
1826 else
1827 r = TREG_RAX;
1828 vtop->r = r;
1829 break;
1830 default:
1831 opc = 7;
1832 goto gen_op8;
1836 void gen_opl(int op)
1838 gen_opi(op);
1841 void vpush_const(int t, int v)
1843 CType ctype = { t | VT_CONSTANT, 0 };
1844 vpushsym(&ctype, external_global_sym(v, &ctype));
1845 vtop->r |= VT_LVAL;
1848 /* generate a floating point operation 'v = t1 op t2' instruction. The
1849 two operands are guaranteed to have the same floating point type */
1850 /* XXX: need to use ST1 too */
1851 void gen_opf(int op)
1853 int a, ft, fc, swapped, r;
1854 int bt = vtop->type.t & VT_BTYPE;
1855 int float_type = bt == VT_LDOUBLE ? RC_ST0 : RC_FLOAT;
1857 if (op == TOK_NEG) { /* unary minus */
1858 gv(float_type);
1859 if (float_type == RC_ST0) {
1860 o(0xe0d9); /* fchs */
1861 } else {
1862 /* -0.0, in libtcc1.c */
1863 vpush_const(bt, bt == VT_FLOAT ? TOK___mzerosf : TOK___mzerodf);
1864 gv(RC_FLOAT);
1865 if (bt == VT_DOUBLE)
1866 o(0x66);
1867 /* xorp[sd] %xmm1, %xmm0 */
1868 o(0xc0570f | (REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8) << 16);
1869 vtop--;
1871 return;
1874 /* convert constants to memory references */
1875 if ((vtop[-1].r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
1876 vswap();
1877 gv(float_type);
1878 vswap();
1880 if ((vtop[0].r & (VT_VALMASK | VT_LVAL)) == VT_CONST)
1881 gv(float_type);
1883 /* must put at least one value in the floating point register */
1884 if ((vtop[-1].r & VT_LVAL) &&
1885 (vtop[0].r & VT_LVAL)) {
1886 vswap();
1887 gv(float_type);
1888 vswap();
1890 swapped = 0;
1891 /* swap the stack if needed so that t1 is the register and t2 is
1892 the memory reference */
1893 if (vtop[-1].r & VT_LVAL) {
1894 vswap();
1895 swapped = 1;
1897 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1898 if (op >= TOK_ULT && op <= TOK_GT) {
1899 /* load on stack second operand */
1900 load(TREG_ST0, vtop);
1901 save_reg(TREG_RAX); /* eax is used by FP comparison code */
1902 if (op == TOK_GE || op == TOK_GT)
1903 swapped = !swapped;
1904 else if (op == TOK_EQ || op == TOK_NE)
1905 swapped = 0;
1906 if (swapped)
1907 o(0xc9d9); /* fxch %st(1) */
1908 if (op == TOK_EQ || op == TOK_NE)
1909 o(0xe9da); /* fucompp */
1910 else
1911 o(0xd9de); /* fcompp */
1912 o(0xe0df); /* fnstsw %ax */
1913 if (op == TOK_EQ) {
1914 o(0x45e480); /* and $0x45, %ah */
1915 o(0x40fC80); /* cmp $0x40, %ah */
1916 } else if (op == TOK_NE) {
1917 o(0x45e480); /* and $0x45, %ah */
1918 o(0x40f480); /* xor $0x40, %ah */
1919 op = TOK_NE;
1920 } else if (op == TOK_GE || op == TOK_LE) {
1921 o(0x05c4f6); /* test $0x05, %ah */
1922 op = TOK_EQ;
1923 } else {
1924 o(0x45c4f6); /* test $0x45, %ah */
1925 op = TOK_EQ;
1927 vtop--;
1928 vset_VT_CMP(op);
1929 } else {
1930 /* no memory reference possible for long double operations */
1931 load(TREG_ST0, vtop);
1932 swapped = !swapped;
1934 switch(op) {
1935 default:
1936 case '+':
1937 a = 0;
1938 break;
1939 case '-':
1940 a = 4;
1941 if (swapped)
1942 a++;
1943 break;
1944 case '*':
1945 a = 1;
1946 break;
1947 case '/':
1948 a = 6;
1949 if (swapped)
1950 a++;
1951 break;
1953 ft = vtop->type.t;
1954 fc = vtop->c.i;
1955 o(0xde); /* fxxxp %st, %st(1) */
1956 o(0xc1 + (a << 3));
1957 vtop--;
1959 } else {
1960 if (op >= TOK_ULT && op <= TOK_GT) {
1961 /* if saved lvalue, then we must reload it */
1962 r = vtop->r;
1963 fc = vtop->c.i;
1964 if ((r & VT_VALMASK) == VT_LLOCAL) {
1965 SValue v1;
1966 r = get_reg(RC_INT);
1967 v1.type.t = VT_PTR;
1968 v1.r = VT_LOCAL | VT_LVAL;
1969 v1.c.i = fc;
1970 load(r, &v1);
1971 fc = 0;
1972 vtop->r = r = r | VT_LVAL;
1975 if (op == TOK_EQ || op == TOK_NE) {
1976 swapped = 0;
1977 } else {
1978 if (op == TOK_LE || op == TOK_LT)
1979 swapped = !swapped;
1980 if (op == TOK_LE || op == TOK_GE) {
1981 op = 0x93; /* setae */
1982 } else {
1983 op = 0x97; /* seta */
1987 if (swapped) {
1988 gv(RC_FLOAT);
1989 vswap();
1991 assert(!(vtop[-1].r & VT_LVAL));
1993 if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
1994 o(0x66);
1995 if (op == TOK_EQ || op == TOK_NE)
1996 o(0x2e0f); /* ucomisd */
1997 else
1998 o(0x2f0f); /* comisd */
2000 if (vtop->r & VT_LVAL) {
2001 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
2002 } else {
2003 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
2006 vtop--;
2007 vset_VT_CMP(op | 0x100);
2008 vtop->cmp_r = op;
2009 } else {
2010 assert((vtop->type.t & VT_BTYPE) != VT_LDOUBLE);
2011 switch(op) {
2012 default:
2013 case '+':
2014 a = 0;
2015 break;
2016 case '-':
2017 a = 4;
2018 break;
2019 case '*':
2020 a = 1;
2021 break;
2022 case '/':
2023 a = 6;
2024 break;
2026 ft = vtop->type.t;
2027 fc = vtop->c.i;
2028 assert((ft & VT_BTYPE) != VT_LDOUBLE);
2030 r = vtop->r;
2031 /* if saved lvalue, then we must reload it */
2032 if ((vtop->r & VT_VALMASK) == VT_LLOCAL) {
2033 SValue v1;
2034 r = get_reg(RC_INT);
2035 v1.type.t = VT_PTR;
2036 v1.r = VT_LOCAL | VT_LVAL;
2037 v1.c.i = fc;
2038 load(r, &v1);
2039 fc = 0;
2040 vtop->r = r = r | VT_LVAL;
2043 assert(!(vtop[-1].r & VT_LVAL));
2044 if (swapped) {
2045 assert(vtop->r & VT_LVAL);
2046 gv(RC_FLOAT);
2047 vswap();
2050 if ((ft & VT_BTYPE) == VT_DOUBLE) {
2051 o(0xf2);
2052 } else {
2053 o(0xf3);
2055 o(0x0f);
2056 o(0x58 + a);
2058 if (vtop->r & VT_LVAL) {
2059 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
2060 } else {
2061 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
2064 vtop--;
2069 /* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
2070 and 'long long' cases. */
2071 void gen_cvt_itof(int t)
2073 if ((t & VT_BTYPE) == VT_LDOUBLE) {
2074 save_reg(TREG_ST0);
2075 gv(RC_INT);
2076 if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
2077 /* signed long long to float/double/long double (unsigned case
2078 is handled generically) */
2079 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2080 o(0x242cdf); /* fildll (%rsp) */
2081 o(0x08c48348); /* add $8, %rsp */
2082 } else if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2083 (VT_INT | VT_UNSIGNED)) {
2084 /* unsigned int to float/double/long double */
2085 o(0x6a); /* push $0 */
2086 g(0x00);
2087 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2088 o(0x242cdf); /* fildll (%rsp) */
2089 o(0x10c48348); /* add $16, %rsp */
2090 } else {
2091 /* int to float/double/long double */
2092 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2093 o(0x2404db); /* fildl (%rsp) */
2094 o(0x08c48348); /* add $8, %rsp */
2096 vtop->r = TREG_ST0;
2097 } else {
2098 int r = get_reg(RC_FLOAT);
2099 gv(RC_INT);
2100 o(0xf2 + ((t & VT_BTYPE) == VT_FLOAT?1:0));
2101 if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2102 (VT_INT | VT_UNSIGNED) ||
2103 (vtop->type.t & VT_BTYPE) == VT_LLONG) {
2104 o(0x48); /* REX */
2106 o(0x2a0f);
2107 o(0xc0 + (vtop->r & VT_VALMASK) + REG_VALUE(r)*8); /* cvtsi2sd */
2108 vtop->r = r;
2112 /* convert from one floating point type to another */
2113 void gen_cvt_ftof(int t)
2115 int ft, bt, tbt;
2117 ft = vtop->type.t;
2118 bt = ft & VT_BTYPE;
2119 tbt = t & VT_BTYPE;
2121 if (bt == VT_FLOAT) {
2122 gv(RC_FLOAT);
2123 if (tbt == VT_DOUBLE) {
2124 o(0x140f); /* unpcklps */
2125 o(0xc0 + REG_VALUE(vtop->r)*9);
2126 o(0x5a0f); /* cvtps2pd */
2127 o(0xc0 + REG_VALUE(vtop->r)*9);
2128 } else if (tbt == VT_LDOUBLE) {
2129 save_reg(RC_ST0);
2130 /* movss %xmm0,-0x10(%rsp) */
2131 o(0x110ff3);
2132 o(0x44 + REG_VALUE(vtop->r)*8);
2133 o(0xf024);
2134 o(0xf02444d9); /* flds -0x10(%rsp) */
2135 vtop->r = TREG_ST0;
2137 } else if (bt == VT_DOUBLE) {
2138 gv(RC_FLOAT);
2139 if (tbt == VT_FLOAT) {
2140 o(0x140f66); /* unpcklpd */
2141 o(0xc0 + REG_VALUE(vtop->r)*9);
2142 o(0x5a0f66); /* cvtpd2ps */
2143 o(0xc0 + REG_VALUE(vtop->r)*9);
2144 } else if (tbt == VT_LDOUBLE) {
2145 save_reg(RC_ST0);
2146 /* movsd %xmm0,-0x10(%rsp) */
2147 o(0x110ff2);
2148 o(0x44 + REG_VALUE(vtop->r)*8);
2149 o(0xf024);
2150 o(0xf02444dd); /* fldl -0x10(%rsp) */
2151 vtop->r = TREG_ST0;
2153 } else {
2154 int r;
2155 gv(RC_ST0);
2156 r = get_reg(RC_FLOAT);
2157 if (tbt == VT_DOUBLE) {
2158 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
2159 /* movsd -0x10(%rsp),%xmm0 */
2160 o(0x100ff2);
2161 o(0x44 + REG_VALUE(r)*8);
2162 o(0xf024);
2163 vtop->r = r;
2164 } else if (tbt == VT_FLOAT) {
2165 o(0xf0245cd9); /* fstps -0x10(%rsp) */
2166 /* movss -0x10(%rsp),%xmm0 */
2167 o(0x100ff3);
2168 o(0x44 + REG_VALUE(r)*8);
2169 o(0xf024);
2170 vtop->r = r;
2175 /* convert fp to int 't' type */
2176 void gen_cvt_ftoi(int t)
2178 int ft, bt, size, r;
2179 ft = vtop->type.t;
2180 bt = ft & VT_BTYPE;
2181 if (bt == VT_LDOUBLE) {
2182 gen_cvt_ftof(VT_DOUBLE);
2183 bt = VT_DOUBLE;
2186 gv(RC_FLOAT);
2187 if (t != VT_INT)
2188 size = 8;
2189 else
2190 size = 4;
2192 r = get_reg(RC_INT);
2193 if (bt == VT_FLOAT) {
2194 o(0xf3);
2195 } else if (bt == VT_DOUBLE) {
2196 o(0xf2);
2197 } else {
2198 assert(0);
2200 orex(size == 8, r, 0, 0x2c0f); /* cvttss2si or cvttsd2si */
2201 o(0xc0 + REG_VALUE(vtop->r) + REG_VALUE(r)*8);
2202 vtop->r = r;
2205 // Generate sign extension from 32 to 64 bits:
2206 ST_FUNC void gen_cvt_sxtw(void)
2208 int r = gv(RC_INT);
2209 /* x86_64 specific: movslq */
2210 o(0x6348);
2211 o(0xc0 + (REG_VALUE(r) << 3) + REG_VALUE(r));
2214 /* char/short to int conversion */
2215 ST_FUNC void gen_cvt_csti(int t)
2217 int r, sz, xl, ll;
2218 r = gv(RC_INT);
2219 sz = !(t & VT_UNSIGNED);
2220 xl = (t & VT_BTYPE) == VT_SHORT;
2221 ll = (vtop->type.t & VT_BTYPE) == VT_LLONG;
2222 orex(ll, r, 0, 0xc0b60f /* mov[sz] %a[xl], %eax */
2223 | (sz << 3 | xl) << 8
2224 | (REG_VALUE(r) << 3 | REG_VALUE(r)) << 16
2228 /* increment tcov counter */
2229 ST_FUNC void gen_increment_tcov (SValue *sv)
2231 o(0x058348); /* addq $1, xxx(%rip) */
2232 greloca(cur_text_section, sv->sym, ind, R_X86_64_PC32, -5);
2233 gen_le32(0);
2234 o(1);
2237 /* computed goto support */
2238 ST_FUNC void ggoto(void)
2240 gcall_or_jmp(1);
2241 vtop--;
2244 /* Save the stack pointer onto the stack and return the location of its address */
2245 ST_FUNC void gen_vla_sp_save(int addr) {
2246 /* mov %rsp,addr(%rbp)*/
2247 gen_modrm64(0x89, TREG_RSP, VT_LOCAL, NULL, addr);
2250 /* Restore the SP from a location on the stack */
2251 ST_FUNC void gen_vla_sp_restore(int addr) {
2252 gen_modrm64(0x8b, TREG_RSP, VT_LOCAL, NULL, addr);
2255 #ifdef TCC_TARGET_PE
2256 /* Save result of gen_vla_alloc onto the stack */
2257 ST_FUNC void gen_vla_result(int addr) {
2258 /* mov %rax,addr(%rbp)*/
2259 gen_modrm64(0x89, TREG_RAX, VT_LOCAL, NULL, addr);
2261 #endif
2263 /* Subtract from the stack pointer, and push the resulting value onto the stack */
2264 ST_FUNC void gen_vla_alloc(CType *type, int align) {
2265 int use_call = 0;
2267 #if defined(CONFIG_TCC_BCHECK)
2268 use_call = tcc_state->do_bounds_check;
2269 #endif
2270 #ifdef TCC_TARGET_PE /* alloca does more than just adjust %rsp on Windows */
2271 use_call = 1;
2272 #endif
2273 if (use_call)
2275 vpush_helper_func(TOK_alloca);
2276 vswap(); /* Move alloca ref past allocation size */
2277 gfunc_call(1);
2279 else {
2280 int r;
2281 r = gv(RC_INT); /* allocation size */
2282 /* sub r,%rsp */
2283 o(0x2b48);
2284 o(0xe0 | REG_VALUE(r));
2285 /* We align to 16 bytes rather than align */
2286 /* and ~15, %rsp */
2287 o(0xf0e48348);
2288 vpop();
2293 * Assmuing the top part of the stack looks like below,
2294 * src dest src
2296 ST_FUNC void gen_struct_copy(int size)
2298 int n = size / PTR_SIZE;
2299 #ifdef TCC_TARGET_PE
2300 o(0x5756); /* push rsi, rdi */
2301 #endif
2302 gv2(RC_RDI, RC_RSI);
2303 if (n <= 4) {
2304 while (n)
2305 o(0xa548), --n;
2306 } else {
2307 vpushi(n);
2308 gv(RC_RCX);
2309 o(0xa548f3);
2310 vpop();
2312 if (size & 0x04)
2313 o(0xa5);
2314 if (size & 0x02)
2315 o(0xa566);
2316 if (size & 0x01)
2317 o(0xa4);
2318 #ifdef TCC_TARGET_PE
2319 o(0x5e5f); /* pop rdi, rsi */
2320 #endif
2321 vpop();
2322 vpop();
2325 /* end of x86-64 code generator */
2326 /*************************************************************/
2327 #endif /* ! TARGET_DEFS_ONLY */
2328 /******************************************************/