1 #ifdef TARGET_DEFS_ONLY
3 // Number of registers available to allocator:
4 #define NB_REGS 19 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7, xxx, ra, sp
6 #define TREG_R(x) (x) // x = 0..7
7 #define TREG_F(x) (x + 8) // x = 0..7
9 // Register classes sorted from more general to more precise:
10 #define RC_INT (1 << 0)
11 #define RC_FLOAT (1 << 1)
12 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
13 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
15 #define RC_IRET (RC_R(0)) // int return register class
16 #define RC_FRET (RC_F(0)) // float return register class
18 #define REG_IRET (TREG_R(0)) // int return register number
19 #define REG_FRET (TREG_F(0)) // float return register number
23 #define LDOUBLE_SIZE 16
24 #define LDOUBLE_ALIGN 16
28 #define CHAR_IS_UNSIGNED
39 ST_DATA
const int reg_classes
[NB_REGS
] = {
61 static int ireg(int r
)
67 assert(r
>= 0 && r
< 8);
68 return r
+ 10; // tccrX --> aX == x(10+X)
71 static int is_ireg(int r
)
73 return r
< 8 || r
== TREG_RA
|| r
== TREG_SP
;
76 static int freg(int r
)
78 assert(r
>= 8 && r
< 16);
79 return r
- 8 + 10; // tccfX --> faX == f(10+X)
82 static int is_freg(int r
)
84 return r
>= 8 && r
< 16;
87 ST_FUNC
void o(unsigned int c
)
92 if (ind1
> cur_text_section
->data_allocated
)
93 section_realloc(cur_text_section
, ind1
);
94 write32le(cur_text_section
->data
+ ind
, c
);
98 static void EIu(uint32_t opcode
, uint32_t func3
,
99 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
101 o(opcode
| (func3
<< 12) | (rd
<< 7) | (rs1
<< 15) | (imm
<< 20));
104 static void EI(uint32_t opcode
, uint32_t func3
,
105 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
107 assert(! ((imm
+ (1 << 11)) >> 12));
108 EIu(opcode
, func3
, rd
, rs1
, imm
);
111 static void ES(uint32_t opcode
, uint32_t func3
,
112 uint32_t rs1
, uint32_t rs2
, uint32_t imm
)
114 assert(! ((imm
+ (1 << 11)) >> 12));
115 o(opcode
| (func3
<< 12) | ((imm
& 0x1f) << 7) | (rs1
<< 15)
116 | (rs2
<< 20) | ((imm
>> 5) << 25));
119 // Patch all branches in list pointed to by t to branch to a:
120 ST_FUNC
void gsym_addr(int t_
, int a_
)
125 unsigned char *ptr
= cur_text_section
->data
+ t
;
126 uint32_t next
= read32le(ptr
);
127 uint32_t r
= a
- t
, imm
;
128 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
129 tcc_error("out-of-range branch chain");
130 imm
= (((r
>> 12) & 0xff) << 12)
131 | (((r
>> 11) & 1) << 20)
132 | (((r
>> 1) & 0x3ff) << 21)
133 | (((r
>> 20) & 1) << 31);
134 write32le(ptr
, r
== 4 ? 0x33 : 0x6f | imm
); // nop || j imm
139 ST_FUNC
void load(int r
, SValue
*sv
)
142 int v
= fr
& VT_VALMASK
;
143 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
145 int bt
= sv
->type
.t
& VT_BTYPE
;
146 int align
, size
= type_size(&sv
->type
, &align
);
148 int func3
, opcode
= 0x03;
150 assert(bt
== VT_DOUBLE
|| bt
== VT_FLOAT
);
152 func3
= bt
== VT_DOUBLE
? 3 : 2;
157 func3
= size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3;
158 if (size
< 8 && !is_float(sv
->type
.t
) && (sv
->type
.t
& VT_UNSIGNED
))
164 tcc_error("unimp: load1(giant local ofs) (0x%llx)", (long long)sv
->c
.i
);
165 if (((unsigned)fc
+ (1 << 11)) >> 12) {
166 br
= is_ireg(r
) ? rr
: 5;
167 o(0x37 | (br
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui BR, upper(fc)
168 o(0x33 | (br
<< 7) | (br
<< 15) | (8 << 20)); // add BR, BR, s0
171 EI(opcode
, func3
, rr
, br
, fc
); // l[bhwd][u]/fl[wd] RR, fc(BR)
172 } else if (v
< VT_CONST
) {
173 /*if (((unsigned)fc + (1 << 11)) >> 12)
174 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
175 fc
= 0; // XXX store ofs in LVAL(reg)
176 EI(opcode
, func3
, rr
, ireg(v
), fc
); // l[bhwd][u] RR, 0(V)
177 } else if (v
== VT_CONST
&& (fr
& VT_SYM
)) {
179 int addend
= 0, tempr
;
180 if (1 || ((unsigned)fc
+ (1 << 11)) >> 12)
183 greloca(cur_text_section
, sv
->sym
, ind
,
184 R_RISCV_PCREL_HI20
, addend
);
186 label
.v
= tok_alloc(".L0 ", 4)->tok
;
187 label
.type
.t
= VT_VOID
| VT_STATIC
;
189 label
.c
= 0; /* force new local ELF symbol */
190 put_extern_sym(&label
, cur_text_section
, ind
, 0);
191 tempr
= is_ireg(r
) ? rr
: 5;
192 o(0x17 | (tempr
<< 7)); // auipc TR, 0 %pcrel_hi(sym)+addend
193 greloca(cur_text_section
, &label
, ind
,
194 R_RISCV_PCREL_LO12_I
, 0);
195 EI(opcode
, func3
, rr
, tempr
, fc
); // l[bhwd][u] RR, fc(TR)
196 } else if (v
== VT_LLOCAL
) {
197 int br
= 8, tempr
= is_ireg(r
) ? rr
: 5;
199 tcc_error("unimp: load2(giant local ofs) (0x%llx)", (long long)sv
->c
.i
);
200 if (((unsigned)fc
+ (1 << 11)) >> 12) {
202 o(0x37 | (br
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui BR, upper(fc)
203 o(0x33 | (br
<< 7) | (br
<< 15) | (8 << 20)); // add BR, BR, s0
206 EI(0x03, 3, tempr
, br
, fc
); // ld TEMPR, fc(BR)
207 EI(opcode
, func3
, rr
, tempr
, 0); // l[bhwd][u] RR, 0(TEMPR)
209 tcc_error("unimp: load(non-local lval)");
211 } else if (v
== VT_CONST
) {
212 int rb
= 0, do32bit
= 8, doload
= 0, zext
= 0;
213 assert((!is_float(sv
->type
.t
) && is_ireg(r
)) || bt
== VT_LDOUBLE
);
216 if (sv
->sym
->type
.t
& VT_STATIC
) { // XXX do this per linker relax
217 greloca(cur_text_section
, sv
->sym
, ind
,
218 R_RISCV_PCREL_HI20
, sv
->c
.i
);
222 if (((unsigned)fc
+ (1 << 11)) >> 12)
223 tcc_error("unimp: large addend for global address");
224 greloca(cur_text_section
, sv
->sym
, ind
,
225 R_RISCV_GOT_HI20
, 0);
229 label
.v
= tok_alloc(".L0 ", 4)->tok
;
230 label
.type
.t
= VT_VOID
| VT_STATIC
;
232 label
.c
= 0; /* force new local ELF symbol */
233 put_extern_sym(&label
, cur_text_section
, ind
, 0);
234 o(0x17 | (rr
<< 7)); // auipc RR, 0 %call(func)
235 greloca(cur_text_section
, &label
, ind
,
236 R_RISCV_PCREL_LO12_I
, 0);
240 if (is_float(sv
->type
.t
) && bt
!= VT_LDOUBLE
)
241 tcc_error("unimp: load(float)");
243 int64_t si
= sv
->c
.i
;
250 o(0x37 | (rr
<< 7) | (((pi
+ 0x800) & 0xfffff000))); // lui RR, up(up(fc))
251 EI(0x13, 0, rr
, rr
, (int)pi
<< 20 >> 20); // addi RR, RR, lo(up(fc))
252 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
253 EI(0x13, 0, rr
, rr
, (fc
+ (1 << 19)) >> 20); // addi RR, RR, up(lo(fc))
254 EI(0x13, 1, rr
, rr
, 12); // slli RR, RR, 12
256 EI(0x13, 0, rr
, rr
, fc
>> 8); // addi RR, RR, lo1(lo(fc))
257 EI(0x13, 1, rr
, rr
, 8); // slli RR, RR, 8
261 } else if (bt
== VT_LLONG
) {
262 /* A 32bit unsigned constant for a 64bit type.
263 lui always sign extends, so we need to do an explicit zext.*/
267 if (((unsigned)fc
+ (1 << 11)) >> 12)
268 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)), rb
= rr
; //lui RR, upper(fc)
270 EI(0x03, 3, rr
, rr
, 0); // ld RR, 0(RR)
272 EI(0x13 | do32bit
, 0, rr
, rr
, fc
<< 20 >> 20); // addi[w] R, x0|R, FC
274 EI(0x13 | do32bit
, 0, rr
, rb
, fc
<< 20 >> 20); // addi[w] R, x0|R, FC
276 EI(0x13, 1, rr
, rr
, 32); // slli RR, RR, 32
277 EI(0x13, 5, rr
, rr
, 32); // srli RR, RR, 32
279 } else if (v
== VT_LOCAL
) {
283 tcc_error("unimp: load(addr giant local ofs) (0xll%x)", (long long)sv
->c
.i
);
284 if (((unsigned)fc
+ (1 << 11)) >> 12) {
285 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui RR, upper(fc)
286 o(0x33 | (rr
<< 7) | (rr
<< 15) | (8 << 20)); // add RR, RR, s0
290 EI(0x13, 0, rr
, br
, fc
); // addi R, s0, FC
291 } else if (v
< VT_CONST
) {
293 //assert(!fc); XXX support offseted regs
294 if (is_freg(r
) && is_freg(v
))
295 o(0x53 | (rr
<< 7) | (freg(v
) << 15) | (freg(v
) << 20) | ((bt
== VT_DOUBLE
? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
296 else if (is_ireg(r
) && is_ireg(v
))
297 EI(0x13, 0, rr
, ireg(v
), 0); // addi RR, V, 0 == mv RR, V
299 int func7
= is_ireg(r
) ? 0x70 : 0x78;
302 assert(size
== 4 || size
== 8);
303 o(0x53 | (rr
<< 7) | ((is_freg(v
) ? freg(v
) : ireg(v
)) << 15)
304 | (func7
<< 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
306 } else if (v
== VT_CMP
) { // we rely on cmp_r to be the correct result
307 EI(0x13, 0, rr
, vtop
->cmp_r
, 0); // mv RR, CMP_R
308 } else if ((v
& ~1) == VT_JMP
) {
311 EI(0x13, 0, rr
, 0, t
); // addi RR, x0, t
314 EI(0x13, 0, rr
, 0, t
^ 1); // addi RR, x0, !t
316 tcc_error("unimp: load(non-const)");
319 ST_FUNC
void store(int r
, SValue
*sv
)
321 int fr
= sv
->r
& VT_VALMASK
;
322 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
325 int bt
= ft
& VT_BTYPE
;
326 int align
, size
= type_size(&sv
->type
, &align
);
327 assert(!is_float(bt
) || is_freg(r
) || bt
== VT_LDOUBLE
);
328 /* long doubles are in two integer registers, but the load/store
329 primitives only deal with one, so do as if it's one reg. */
330 if (bt
== VT_LDOUBLE
)
333 tcc_error("unimp: store(struct)");
335 tcc_error("unimp: large sized store");
336 assert(sv
->r
& VT_LVAL
);
337 if (fr
== VT_LOCAL
) {
340 tcc_error("unimp: store(giant local off) (0x%llx)", (long long)sv
->c
.i
);
341 if (((unsigned)fc
+ (1 << 11)) >> 12) {
343 o(0x37 | (br
<< 7) | ((0x800 + fc
) & 0xfffff000)); //lui BR, upper(fc)
344 o(0x33 | (br
<< 7) | (br
<< 15) | (8 << 20)); // add BR, BR, s0
348 ES(0x27, size
== 4 ? 2 : 3, br
, rr
, fc
); // fs[wd] RR, fc(base)
350 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
351 br
, rr
, fc
); // s[bhwd] RR, fc(base)
352 } else if (fr
< VT_CONST
) {
353 int ptrreg
= ireg(fr
);
354 /*if (((unsigned)fc + (1 << 11)) >> 12)
355 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
356 fc
= 0; // XXX support offsets regs
358 ES(0x27, size
== 4 ? 2 : 3, ptrreg
, rr
, fc
); // fs[wd] RR, fc(PTRREG)
360 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
361 ptrreg
, rr
, fc
); // s[bhwd] RR, fc(PTRREG)
362 } else if ((sv
->r
& ~VT_LVAL_TYPE
) == (VT_CONST
| VT_SYM
| VT_LVAL
)) {
364 int tempr
, addend
= 0;
365 if (1 || ((unsigned)fc
+ (1 << 11)) >> 12)
369 greloca(cur_text_section
, sv
->sym
, ind
,
370 R_RISCV_PCREL_HI20
, addend
);
372 label
.v
= tok_alloc(".L0 ", 4)->tok
;
373 label
.type
.t
= VT_VOID
| VT_STATIC
;
375 label
.c
= 0; /* force new local ELF symbol */
376 put_extern_sym(&label
, cur_text_section
, ind
, 0);
377 o(0x17 | (tempr
<< 7)); // auipc TEMPR, 0 %pcrel_hi(sym)+addend
378 greloca(cur_text_section
, &label
, ind
,
379 R_RISCV_PCREL_LO12_S
, 0);
381 ES(0x27, size
== 4 ? 2 : 3, tempr
, rr
, fc
); // fs[wd] RR, fc(TEMPR)
383 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
384 tempr
, rr
, fc
); // s[bhwd] RR, fc(TEMPR)
386 tcc_error("implement me: %s(!local)", __FUNCTION__
);
389 static void gcall_or_jmp(int docall
)
391 int tr
= docall
? 1 : 5; // ra or t0
392 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
393 ((vtop
->r
& VT_SYM
) && vtop
->c
.i
== (int)vtop
->c
.i
)) {
394 /* constant symbolic case -> simple relocation */
395 greloca(cur_text_section
, vtop
->sym
, ind
,
396 R_RISCV_CALL_PLT
, (int)vtop
->c
.i
);
397 o(0x17 | (tr
<< 7)); // auipc TR, 0 %call(func)
398 EI(0x67, 0, tr
, tr
, 0);// jalr TR, r(TR)
399 } else if (vtop
->r
< VT_CONST
) {
400 int r
= ireg(vtop
->r
);
401 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
406 EI(0x67, 0, tr
, r
, 0); // jalr TR, 0(R)
410 ST_FUNC
void gfunc_call(int nb_args
)
412 int i
, align
, size
, aireg
, afreg
;
413 int info
[nb_args
? nb_args
: 1];
414 int stack_adj
= 0, tempspace
= 0, ofs
, splitofs
= 0;
419 sa
= vtop
[-nb_args
].type
.ref
->next
;
420 for (i
= 0; i
< nb_args
; i
++) {
421 int *pareg
, nregs
, infreg
= 0, byref
= 0, tempofs
;
422 sv
= &vtop
[1 + i
- nb_args
];
423 sv
->type
.t
&= ~VT_ARRAY
; // XXX this should be done in tccgen.c
424 size
= type_size(&sv
->type
, &align
);
428 tempspace
= (tempspace
+ align
- 1) & -align
;
438 if ((sv
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
) {
441 infreg
= sa
&& is_float(sv
->type
.t
);
442 if (!infreg
&& !sa
&& align
== 2*XLEN
&& size
<= 2*XLEN
)
443 aireg
= (aireg
+ 1) & ~1;
444 pareg
= infreg
? &afreg
: &aireg
;
445 if ((*pareg
< 8) && !force_stack
) {
446 info
[i
] = *pareg
+ (infreg
? 8 : 0);
460 stack_adj
+= (size
+ align
- 1) & -align
;
465 info
[i
] |= 64 | (tempofs
<< 7);
469 stack_adj
= (stack_adj
+ 15) & -16;
470 tempspace
= (tempspace
+ 15) & -16;
471 if (stack_adj
+ tempspace
) {
472 EI(0x13, 0, 2, 2, -(stack_adj
+ tempspace
)); // addi sp, sp, -adj
473 for (i
= ofs
= 0; i
< nb_args
; i
++) {
476 size
= type_size(&vtop
->type
, &align
);
478 vset(&char_pointer_type
, TREG_SP
, 0);
479 vpushi(stack_adj
+ (info
[i
] >> 7));
481 vpushv(vtop
); // this replaces the old argument
484 vtop
->type
= vtop
[-1].type
;
493 /* Once we support offseted regs we can do this:
494 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
495 to construct the lvalue for the outgoing stack slot,
496 until then we have to jump through hoops. */
497 vset(&char_pointer_type
, TREG_SP
, 0);
498 ofs
= (ofs
+ align
- 1) & -align
;
502 vtop
->type
= vtop
[-1].type
;
505 vtop
->r
= vtop
->r2
= VT_CONST
; // this arg is done
509 } else if (info
[i
] & 16) {
516 for (i
= 0; i
< nb_args
; i
++) {
517 int r
= info
[nb_args
- 1 - i
];
522 origtype
= vtop
->type
;
523 size
= type_size(&vtop
->type
, &align
);
524 if (size
> 8 && (vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
)
525 vtop
->type
.t
= VT_LDOUBLE
; // force loading a pair of regs
526 gv(r
< 8 ? RC_R(r
) : RC_F(r
- 8));
527 vtop
->type
= origtype
;
529 assert((vtop
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
530 || (vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
);
531 assert(vtop
->r2
< VT_CONST
);
532 if (info
[nb_args
- 1 - i
] & 16) {
533 ES(0x23, 3, 2, ireg(vtop
->r2
), splitofs
); // sd t0, ofs(sp)
534 } else if (vtop
->r2
!= 1 + vtop
->r
) {
536 /* XXX we'd like to have 'gv' move directly into
537 the right class instead of us fixing it up. */
538 EI(0x13, 0, ireg(vtop
->r
) + 1, ireg(vtop
->r2
), 0); // mv Ra+1, RR2
539 vtop
->r2
= 1 + vtop
->r
;
548 if (stack_adj
+ tempspace
)
549 EI(0x13, 0, 2, 2, stack_adj
+ tempspace
); // addi sp, sp, adj
552 static int func_sub_sp_offset
, num_va_regs
;
554 ST_FUNC
void gfunc_prolog(CType
*func_type
)
556 int i
, addr
, align
, size
;
562 sym
= func_type
->ref
;
564 loc
= -16; // for ra and s0
565 func_sub_sp_offset
= ind
;
569 addr
= 0; // XXX not correct
570 /* if the function returns by reference, then add an
571 implicit pointer parameter */
572 size
= type_size(&func_vt
, &align
);
573 if (size
> 2 * XLEN
) {
576 ES(0x23, 3, 8, 10 + aireg
, loc
); // sd a0, loc(s0)
579 /* define parameters */
580 while ((sym
= sym
->next
) != NULL
) {
583 size
= type_size(type
, &align
);
584 if (size
> 2 * XLEN
) {
585 type
= &char_pointer_type
;
586 size
= align
= byref
= 8;
588 if (size
> 2 * XLEN
) {
592 addr
= (addr
+ align
- 1) & -align
;
596 int regcount
= 1, *pareg
= &aireg
;
597 if (is_float(type
->t
) && (type
->t
& VT_BTYPE
) != VT_LDOUBLE
)
599 if (regcount
+ *pareg
> 8)
603 loc
-= regcount
* 8; // XXX could reserve only 'size' bytes
605 for (i
= 0; i
< regcount
; i
++) {
607 assert(i
== 1 && regcount
== 2 && !(addr
& 7));
608 EI(0x03, 3, 5, 8, addr
); // ld t0, addr(s0)
610 ES(0x23, 3, 8, 5, loc
+ i
*8); // sd t0, loc(s0)
613 if (pareg
== &afreg
) {
614 assert(type
->t
== VT_FLOAT
|| type
->t
== VT_DOUBLE
);
615 ES(0x27, size
== 4 ? 2 : 3, 8, 10 + *pareg
, loc
+ i
*8); // fs[wd] FAi, loc(s0)
617 ES(0x23, 3, 8, 10 + *pareg
, loc
+ i
*8); // sd aX, loc(s0) // XXX
622 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
623 (byref
? VT_LLOCAL
: VT_LOCAL
) | lvalue_type(sym
->type
.t
),
627 if (func_type
->ref
->f
.func_type
== FUNC_ELLIPSIS
) {
628 for (; aireg
< 8; aireg
++) {
630 ES(0x23, 3, 8, 10 + aireg
, -8 + num_va_regs
* 8); // sd aX, loc(s0)
635 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
636 int *ret_align
, int *regsize
)
638 /* generic code can only deal with structs of pow(2) sizes
639 (it always deals with whole registers), so go through our own
641 int align
, size
= type_size(vt
, &align
);
656 return (size
+ 7) / 8;
659 ST_FUNC
void gfunc_return(CType
*func_type
)
661 int align
, size
= type_size(func_type
, &align
), nregs
;
662 CType type
= *func_type
;
663 if (size
> 2 * XLEN
) {
665 vset(&type
, VT_LOCAL
| VT_LVAL
, func_vc
);
672 nregs
= (size
+ 7) / 8;
674 vtop
->type
.t
= VT_LDOUBLE
;
676 if (is_float(func_type
->t
) && (vtop
->type
.t
& VT_BTYPE
) != VT_LDOUBLE
)
683 ST_FUNC
void gfunc_epilog(void)
685 int v
, saved_ind
, d
, large_ofs_ind
;
687 loc
= (loc
- num_va_regs
* 8);
688 d
= v
= (-loc
+ 15) & -16;
690 if (v
>= (1 << 11)) {
692 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
693 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
694 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20)); //add sp, sp, t0
696 EI(0x03, 3, 1, 2, d
- 8 - num_va_regs
* 8); // ld ra, v-8(sp)
697 EI(0x03, 3, 8, 2, d
- 16 - num_va_regs
* 8); // ld s0, v-16(sp)
698 EI(0x13, 0, 2, 2, d
); // addi sp, sp, v
699 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
700 if (v
>= (1 << 11)) {
702 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
703 o(0x37 | (5 << 7) | ((0x800 + (v
-16)) & 0xfffff000)); //lui t0, upper(v)
704 EI(0x13, 0, 5, 5, (v
-16) << 20 >> 20); // addi t0, t0, lo(v)
705 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20) | (0x20 << 25)); //sub sp, sp, t0
706 gjmp_addr(func_sub_sp_offset
+ 5*4);
710 ind
= func_sub_sp_offset
;
711 EI(0x13, 0, 2, 2, -d
); // addi sp, sp, -d
712 ES(0x23, 3, 2, 1, d
- 8 - num_va_regs
* 8); // sd ra, d-8(sp)
713 ES(0x23, 3, 2, 8, d
- 16 - num_va_regs
* 8); // sd s0, d-16(sp)
715 EI(0x13, 0, 8, 2, d
- num_va_regs
* 8); // addi s0, sp, d
717 gjmp_addr(large_ofs_ind
);
718 if ((ind
- func_sub_sp_offset
) != 5*4)
719 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
723 ST_FUNC
void gen_va_start(void)
725 tcc_error("implement me: %s", __FUNCTION__
);
728 ST_FUNC
void gen_va_arg(CType
*t
)
730 tcc_error("implement me: %s", __FUNCTION__
);
733 ST_FUNC
void gen_fill_nops(int bytes
)
736 tcc_error("alignment of code section not multiple of 4");
738 EI(0x13, 0, 0, 0, 0); // addi x0, x0, 0 == nop
743 // Generate forward branch to label:
744 ST_FUNC
int gjmp(int t
)
752 // Generate branch to known address:
753 ST_FUNC
void gjmp_addr(int a
)
755 uint32_t r
= a
- ind
, imm
;
756 if ((r
+ (1 << 21)) & ~((1U << 22) - 2)) {
757 o(0x17 | (5 << 7) | (((r
+ 0x800) & 0xfffff000))); // lui RR, up(r)
758 r
= (int)r
<< 20 >> 20;
759 EI(0x67, 0, 0, 5, r
); // jalr x0, r(t0)
761 imm
= (((r
>> 12) & 0xff) << 12)
762 | (((r
>> 11) & 1) << 20)
763 | (((r
>> 1) & 0x3ff) << 21)
764 | (((r
>> 20) & 1) << 31);
765 o(0x6f | imm
); // jal x0, imm == j imm
769 ST_FUNC
int gjmp_cond(int op
, int t
)
772 assert(op
== TOK_EQ
|| op
== TOK_NE
);
773 assert(vtop
->cmp_r
>= 10 && vtop
->cmp_r
< 18);
774 o(0x63 | (!inv
<< 12) | (vtop
->cmp_r
<< 15) | (8 << 7)); // bne/beq x0,r,+4
778 ST_FUNC
int gjmp_append(int n
, int t
)
781 /* insert jump list n into t */
784 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
792 static void gen_opil(int op
, int ll
)
796 int func3
= 0, func7
= 0;
797 /* XXX We could special-case some constant args. */
799 a
= ireg(vtop
[-1].r
);
809 tcc_error("implement me: %s(%s)", __FUNCTION__
, get_tok_str(op
, NULL
));
812 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20)); // add d, a, b
815 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); //sub d, a, b
818 o(0x33 | ll
| (d
<< 7) | (a
<< 15) | (b
<< 20) | (5 << 12) | (1 << 30)); //sra d, a, b
821 o(0x33 | ll
| (d
<< 7) | (a
<< 15) | (b
<< 20) | (5 << 12)); //srl d, a, b
824 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (1 << 12)); //sll d, a, b
827 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25)); //mul d, a, b
830 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
833 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (7 << 12)); // and d, a, b
836 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (4 << 12)); // xor d, a, b
839 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (6 << 12)); // or d, a, b
842 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (6 << 12)); //rem d, a, b
845 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (7 << 12)); //remu d, a, b
849 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (5 << 12)); //divu d, a, b
860 if (op
& 1) { // remove [U]GE,GT
864 if ((op
& 7) == 6) { // [U]LE
865 int t
= a
; a
= b
; b
= t
;
868 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (((op
> TOK_UGT
) ? 2 : 3) << 12)); // slt[u] d, a, b
870 EI(0x13, 4, d
, d
, 1); // xori d, d, 1
876 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); // sub d, a, b
878 o(0x33 | (3 << 12) | (d
<< 7) | (0 << 15) | (d
<< 20)); // sltu d, x0, d == snez d,d
880 EI(0x13, 3, d
, d
, 1); // sltiu d, d, 1 == seqz d,d
887 ST_FUNC
void gen_opi(int op
)
892 ST_FUNC
void gen_opl(int op
)
897 ST_FUNC
void gen_opf(int op
)
899 int rs1
, rs2
, rd
, dbl
, invert
;
900 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
901 CType type
= vtop
[0].type
;
905 case '*': func
= TOK___multf3
; break;
906 case '+': func
= TOK___addtf3
; break;
907 case '-': func
= TOK___subtf3
; break;
908 case '/': func
= TOK___divtf3
; break;
909 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
910 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
911 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
912 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
913 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
914 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
915 default: assert(0); break;
917 vpush_global_sym(&func_old_type
, func
);
922 vtop
->r2
= cond
< 0 ? TREG_R(1) : VT_CONST
;
932 gv2(RC_FLOAT
, RC_FLOAT
);
933 assert(vtop
->type
.t
== VT_DOUBLE
|| vtop
->type
.t
== VT_FLOAT
);
934 dbl
= vtop
->type
.t
== VT_DOUBLE
;
935 rs1
= freg(vtop
[-1].r
);
945 rd
= get_reg(RC_FLOAT
);
948 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (7 << 12) | (dbl
<< 25) | (op
<< 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)
962 rd
= get_reg(RC_INT
);
965 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (op
<< 12) | (dbl
<< 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
967 EI(0x13, 4, rd
, rd
, 1); // xori RD, 1
981 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
985 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
990 ST_FUNC
void gen_cvt_sxtw(void)
992 /* XXX on risc-v the registers are usually sign-extended already.
993 Let's try to not do anything here. */
996 ST_FUNC
void gen_cvt_itof(int t
)
998 int rr
= ireg(gv(RC_INT
)), dr
;
999 int u
= vtop
->type
.t
& VT_UNSIGNED
;
1000 int l
= (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
;
1001 if (t
== VT_LDOUBLE
) {
1003 (u
? TOK___floatunditf
: TOK___floatditf
) :
1004 (u
? TOK___floatunsitf
: TOK___floatsitf
);
1005 vpush_global_sym(&func_old_type
, func
);
1011 vtop
->r2
= TREG_R(1);
1014 dr
= get_reg(RC_FLOAT
);
1018 EIu(0x53, 7, dr
, rr
, ((0x68 | (t
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[sd].[wl][u]
1022 ST_FUNC
void gen_cvt_ftoi(int t
)
1024 int ft
= vtop
->type
.t
& VT_BTYPE
;
1025 int l
= (t
& VT_BTYPE
) == VT_LLONG
;
1026 int u
= t
& VT_UNSIGNED
;
1027 if (ft
== VT_LDOUBLE
) {
1029 (u
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1030 (u
? TOK___fixunstfsi
: TOK___fixtfsi
);
1031 vpush_global_sym(&func_old_type
, func
);
1038 int rr
= freg(gv(RC_FLOAT
)), dr
;
1040 dr
= get_reg(RC_INT
);
1044 EIu(0x53, 7, dr
, rr
, ((0x60 | (ft
== VT_DOUBLE
? 1 : 0)) << 5) | (u
? 1 : 0) | (l
? 2 : 0)); // fcvt.[wl][u].[sd]
1048 ST_FUNC
void gen_cvt_ftof(int dt
)
1050 int st
= vtop
->type
.t
& VT_BTYPE
, rs
, rd
;
1054 if (dt
== VT_LDOUBLE
|| st
== VT_LDOUBLE
) {
1055 int func
= (dt
== VT_LDOUBLE
) ?
1056 (st
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1057 (st
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1058 vpush_global_sym(&func_old_type
, func
);
1063 if (dt
== VT_LDOUBLE
)
1064 vtop
->r
= REG_IRET
, vtop
->r2
= REG_IRET
+1;
1068 assert (dt
== VT_FLOAT
|| dt
== VT_DOUBLE
);
1069 assert (st
== VT_FLOAT
|| st
== VT_DOUBLE
);
1071 rd
= get_reg(RC_FLOAT
);
1072 if (dt
== VT_DOUBLE
)
1073 EI(0x53, 7, freg(rd
), freg(rs
), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
1075 EI(0x53, 7, freg(rd
), freg(rs
), (0x20 << 5) | 1); // fcvt.s.d RD, RS
1080 ST_FUNC
void ggoto(void)
1086 ST_FUNC
void gen_vla_sp_save(int addr
)
1088 ES(0x23, 3, 8, 2, addr
); // sd sp, fc(s0)
1091 ST_FUNC
void gen_vla_sp_restore(int addr
)
1093 EI(0x03, 3, 2, 8, addr
); // ld sp, fc(s0)
1096 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
)
1098 int rr
= ireg(gv(RC_INT
));
1099 EI(0x13, 0, rr
, rr
, 15); // addi RR, RR, 15
1100 EI(0x13, 7, rr
, rr
, -16); // andi, RR, RR, -16
1101 o(0x33 | (2 << 7) | (2 << 15) | (rr
<< 20) | (0x20 << 25)); //sub sp, sp, rr