2 * A64 code generator for TCC
4 * Copyright (c) 2014-2015 Edmund Grimley Evans
6 * Copying and distribution of this file, with or without modification,
7 * are permitted in any medium without royalty provided the copyright
8 * notice and this notice are preserved. This file is offered as-is,
9 * without any warranty.
12 #ifdef TARGET_DEFS_ONLY
14 // Number of registers available to allocator:
15 #define NB_REGS 28 // x0-x18, x30, v0-v7
17 #define TREG_R(x) (x) // x = 0..18
19 #define TREG_F(x) (x + 20) // x = 0..7
21 // Register classes sorted from more general to more precise:
22 #define RC_INT (1 << 0)
23 #define RC_FLOAT (1 << 1)
24 #define RC_R(x) (1 << (2 + (x))) // x = 0..18
25 #define RC_R30 (1 << 21)
26 #define RC_F(x) (1 << (22 + (x))) // x = 0..7
28 #define RC_IRET (RC_R(0)) // int return register class
29 #define RC_FRET (RC_F(0)) // float return register class
31 #define REG_IRET (TREG_R(0)) // int return register number
32 #define REG_FRET (TREG_F(0)) // float return register number
36 #define LDOUBLE_SIZE 16
37 #define LDOUBLE_ALIGN 16
41 #define CHAR_IS_UNSIGNED
43 /******************************************************/
46 #define EM_TCC_TARGET EM_AARCH64
48 #define R_DATA_32 R_AARCH64_ABS32
49 #define R_DATA_PTR R_AARCH64_ABS64
50 #define R_JMP_SLOT R_AARCH64_JUMP_SLOT
51 #define R_GLOB_DAT R_AARCH64_GLOB_DAT
52 #define R_COPY R_AARCH64_COPY
54 #define ELF_START_ADDR 0x00400000
55 #define ELF_PAGE_SIZE 0x1000
57 /******************************************************/
58 #else /* ! TARGET_DEFS_ONLY */
59 /******************************************************/
63 ST_DATA
const int reg_classes
[NB_REGS
] = {
83 RC_R30
, // not in RC_INT as we make special use of x30
94 #define IS_FREG(x) ((x) >= TREG_F(0))
96 static uint32_t intr(int r
)
98 assert(TREG_R(0) <= r
&& r
<= TREG_R30
);
99 return r
< TREG_R30
? r
: 30;
102 static uint32_t fltr(int r
)
104 assert(TREG_F(0) <= r
&& r
<= TREG_F(7));
105 return r
- TREG_F(0);
108 // Add an instruction to text section:
109 ST_FUNC
void o(unsigned int c
)
112 if (ind1
> cur_text_section
->data_allocated
)
113 section_realloc(cur_text_section
, ind1
);
114 write32le(cur_text_section
->data
+ ind
, c
);
118 static int arm64_encode_bimm64(uint64_t x
)
128 if (x
>> 2 == (x
& (((uint64_t)1 << (64 - 2)) - 1)))
129 rep
= 2, x
&= ((uint64_t)1 << 2) - 1;
130 else if (x
>> 4 == (x
& (((uint64_t)1 << (64 - 4)) - 1)))
131 rep
= 4, x
&= ((uint64_t)1 << 4) - 1;
132 else if (x
>> 8 == (x
& (((uint64_t)1 << (64 - 8)) - 1)))
133 rep
= 8, x
&= ((uint64_t)1 << 8) - 1;
134 else if (x
>> 16 == (x
& (((uint64_t)1 << (64 - 16)) - 1)))
135 rep
= 16, x
&= ((uint64_t)1 << 16) - 1;
136 else if (x
>> 32 == (x
& (((uint64_t)1 << (64 - 32)) - 1)))
137 rep
= 32, x
&= ((uint64_t)1 << 32) - 1;
142 if (!(x
& (((uint64_t)1 << 32) - 1))) x
>>= 32, pos
+= 32;
143 if (!(x
& (((uint64_t)1 << 16) - 1))) x
>>= 16, pos
+= 16;
144 if (!(x
& (((uint64_t)1 << 8) - 1))) x
>>= 8, pos
+= 8;
145 if (!(x
& (((uint64_t)1 << 4) - 1))) x
>>= 4, pos
+= 4;
146 if (!(x
& (((uint64_t)1 << 2) - 1))) x
>>= 2, pos
+= 2;
147 if (!(x
& (((uint64_t)1 << 1) - 1))) x
>>= 1, pos
+= 1;
150 if (!(~x
& (((uint64_t)1 << 32) - 1))) x
>>= 32, len
+= 32;
151 if (!(~x
& (((uint64_t)1 << 16) - 1))) x
>>= 16, len
+= 16;
152 if (!(~x
& (((uint64_t)1 << 8) - 1))) x
>>= 8, len
+= 8;
153 if (!(~x
& (((uint64_t)1 << 4) - 1))) x
>>= 4, len
+= 4;
154 if (!(~x
& (((uint64_t)1 << 2) - 1))) x
>>= 2, len
+= 2;
155 if (!(~x
& (((uint64_t)1 << 1) - 1))) x
>>= 1, len
+= 1;
160 pos
= (pos
+ len
) & (rep
- 1);
163 return ((0x1000 & rep
<< 6) | (((rep
- 1) ^ 31) << 1 & 63) |
164 ((rep
- pos
) & (rep
- 1)) << 6 | (len
- 1));
167 static uint32_t arm64_movi(int r
, uint64_t x
)
172 return 0x52800000 | r
| x
<< 5; // movz w(r),#(x)
173 if (!(x
& ~(m
<< 16)))
174 return 0x52a00000 | r
| x
>> 11; // movz w(r),#(x >> 16),lsl #16
175 if (!(x
& ~(m
<< 32)))
176 return 0xd2c00000 | r
| x
>> 27; // movz x(r),#(x >> 32),lsl #32
177 if (!(x
& ~(m
<< 48)))
178 return 0xd2e00000 | r
| x
>> 43; // movz x(r),#(x >> 48),lsl #48
179 if ((x
& ~m
) == m
<< 16)
180 return (0x12800000 | r
|
181 (~x
<< 5 & 0x1fffe0)); // movn w(r),#(~x)
182 if ((x
& ~(m
<< 16)) == m
)
183 return (0x12a00000 | r
|
184 (~x
>> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
186 return (0x92800000 | r
|
187 (~x
<< 5 & 0x1fffe0)); // movn x(r),#(~x)
189 return (0x92a00000 | r
|
190 (~x
>> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
192 return (0x92c00000 | r
|
193 (~x
>> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
195 return (0x92e00000 | r
|
196 (~x
>> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
197 if (!(x
>> 32) && (e
= arm64_encode_bimm64(x
| x
<< 32)) >= 0)
198 return 0x320003e0 | r
| (uint32_t)e
<< 10; // movi w(r),#(x)
199 if ((e
= arm64_encode_bimm64(x
)) >= 0)
200 return 0xb20003e0 | r
| (uint32_t)e
<< 10; // movi x(r),#(x)
204 static void arm64_movimm(int r
, uint64_t x
)
207 if ((i
= arm64_movi(r
, x
)))
208 o(i
); // a single MOV
210 // MOVZ/MOVN and 1-3 MOVKs
212 uint32_t mov1
= 0xd2800000; // movz
214 for (i
= 0; i
< 64; i
+= 16) {
215 z
+= !(x
>> i
& 0xffff);
216 m
+= !(~x
>> i
& 0xffff);
220 mov1
= 0x92800000; // movn
222 for (i
= 0; i
< 64; i
+= 16)
223 if (x1
>> i
& 0xffff) {
224 o(mov1
| r
| (x1
>> i
& 0xffff) << 5 | i
<< 17);
225 // movz/movn x(r),#(*),lsl #(i)
228 for (i
+= 16; i
< 64; i
+= 16)
229 if (x1
>> i
& 0xffff)
230 o(0xf2800000 | r
| (x
>> i
& 0xffff) << 5 | i
<< 17);
231 // movk x(r),#(*),lsl #(i)
235 // Patch all branches in list pointed to by t to branch to a:
236 ST_FUNC
void gsym_addr(int t_
, int a_
)
241 unsigned char *ptr
= cur_text_section
->data
+ t
;
242 uint32_t next
= read32le(ptr
);
243 if (a
- t
+ 0x8000000 >= 0x10000000)
244 tcc_error("branch out of range");
245 write32le(ptr
, (a
- t
== 4 ? 0xd503201f : // nop
246 0x14000000 | ((a
- t
) >> 2 & 0x3ffffff))); // b
251 // Patch all branches in list pointed to by t to branch to current location:
252 ST_FUNC
void gsym(int t
)
257 static int arm64_type_size(int t
)
259 switch (t
& VT_BTYPE
) {
260 case VT_INT
: return 2;
261 case VT_BYTE
: return 0;
262 case VT_SHORT
: return 1;
263 case VT_PTR
: return 3;
264 case VT_ENUM
: return 2;
265 case VT_FUNC
: return 3;
266 case VT_FLOAT
: return 2;
267 case VT_DOUBLE
: return 3;
268 case VT_LDOUBLE
: return 4;
269 case VT_BOOL
: return 0;
270 case VT_LLONG
: return 3;
276 static void arm64_spoff(int reg
, uint64_t off
)
278 uint32_t sub
= off
>> 63;
282 o(0x910003e0 | sub
<< 30 | reg
| off
<< 10);
283 // (add|sub) x(reg),sp,#(off)
285 arm64_movimm(30, off
); // use x30 for offset
286 o(0x8b3e63e0 | sub
<< 30 | reg
); // (add|sub) x(reg),sp,x30
290 static void arm64_ldrx(int sg
, int sz_
, int dst
, int bas
, uint64_t off
)
295 if (!(off
& ~((uint32_t)0xfff << sz
)))
296 o(0x39400000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
297 (uint32_t)!!sg
<< 23 | sz
<< 30); // ldr(*) x(dst),[x(bas),#(off)]
298 else if (off
< 256 || -off
<= 256)
299 o(0x38400000 | dst
| bas
<< 5 | (off
& 511) << 12 |
300 (uint32_t)!!sg
<< 23 | sz
<< 30); // ldur(*) x(dst),[x(bas),#(off)]
302 arm64_movimm(30, off
); // use x30 for offset
303 o(0x38206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
304 (uint32_t)(!!sg
+ 1) << 22 | sz
<< 30); // ldr(*) x(dst),[x(bas),x30]
308 static void arm64_ldrv(int sz_
, int dst
, int bas
, uint64_t off
)
311 if (!(off
& ~((uint32_t)0xfff << sz
)))
312 o(0x3d400000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
313 (sz
& 4) << 21 | (sz
& 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
314 else if (off
< 256 || -off
<= 256)
315 o(0x3c400000 | dst
| bas
<< 5 | (off
& 511) << 12 |
316 (sz
& 4) << 21 | (sz
& 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
318 arm64_movimm(30, off
); // use x30 for offset
319 o(0x3c606800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
320 sz
<< 30 | (sz
& 4) << 21); // ldr (s|d|q)(dst),[x(bas),x30]
324 static void arm64_ldrs(int reg_
, int size
)
327 // Use x30 for intermediate value in some cases.
329 default: assert(0); break;
331 arm64_ldrx(0, 0, reg
, reg
, 0);
334 arm64_ldrx(0, 1, reg
, reg
, 0);
337 arm64_ldrx(0, 1, 30, reg
, 0);
338 arm64_ldrx(0, 0, reg
, reg
, 2);
339 o(0x2a0043c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #16
342 arm64_ldrx(0, 2, reg
, reg
, 0);
345 arm64_ldrx(0, 2, 30, reg
, 0);
346 arm64_ldrx(0, 0, reg
, reg
, 4);
347 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
350 arm64_ldrx(0, 2, 30, reg
, 0);
351 arm64_ldrx(0, 1, reg
, reg
, 4);
352 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
355 arm64_ldrx(0, 2, 30, reg
, 0);
356 arm64_ldrx(0, 2, reg
, reg
, 3);
357 o(0x53087c00 | reg
| reg
<< 5); // lsr w(reg), w(reg), #8
358 o(0xaa0083c0 | reg
| reg
<< 16); // orr x(reg),x30,x(reg),lsl #32
361 arm64_ldrx(0, 3, reg
, reg
, 0);
364 arm64_ldrx(0, 0, reg
+ 1, reg
, 8);
365 arm64_ldrx(0, 3, reg
, reg
, 0);
368 arm64_ldrx(0, 1, reg
+ 1, reg
, 8);
369 arm64_ldrx(0, 3, reg
, reg
, 0);
372 arm64_ldrx(0, 2, reg
+ 1, reg
, 7);
373 o(0x53087c00 | (reg
+1) | (reg
+1) << 5); // lsr w(reg+1), w(reg+1), #8
374 arm64_ldrx(0, 3, reg
, reg
, 0);
377 arm64_ldrx(0, 2, reg
+ 1, reg
, 8);
378 arm64_ldrx(0, 3, reg
, reg
, 0);
381 arm64_ldrx(0, 3, reg
+ 1, reg
, 5);
382 o(0xd358fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #24
383 arm64_ldrx(0, 3, reg
, reg
, 0);
386 arm64_ldrx(0, 3, reg
+ 1, reg
, 6);
387 o(0xd350fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #16
388 arm64_ldrx(0, 3, reg
, reg
, 0);
391 arm64_ldrx(0, 3, reg
+ 1, reg
, 7);
392 o(0xd348fc00 | (reg
+1) | (reg
+1) << 5); // lsr x(reg+1), x(reg+1), #8
393 arm64_ldrx(0, 3, reg
, reg
, 0);
396 o(0xa9400000 | reg
| (reg
+1) << 10 | reg
<< 5);
397 // ldp x(reg),x(reg+1),[x(reg)]
402 static void arm64_strx(int sz_
, int dst
, int bas
, uint64_t off
)
405 if (!(off
& ~((uint32_t)0xfff << sz
)))
406 o(0x39000000 | dst
| bas
<< 5 | off
<< (10 - sz
) | sz
<< 30);
407 // str(*) x(dst),[x(bas],#(off)]
408 else if (off
< 256 || -off
<= 256)
409 o(0x38000000 | dst
| bas
<< 5 | (off
& 511) << 12 | sz
<< 30);
410 // stur(*) x(dst),[x(bas],#(off)]
412 arm64_movimm(30, off
); // use x30 for offset
413 o(0x38206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 | sz
<< 30);
414 // str(*) x(dst),[x(bas),x30]
418 static void arm64_strv(int sz_
, int dst
, int bas
, uint64_t off
)
421 if (!(off
& ~((uint32_t)0xfff << sz
)))
422 o(0x3d000000 | dst
| bas
<< 5 | off
<< (10 - sz
) |
423 (sz
& 4) << 21 | (sz
& 3) << 30); // str (s|d|q)(dst),[x(bas),#(off)]
424 else if (off
< 256 || -off
<= 256)
425 o(0x3c000000 | dst
| bas
<< 5 | (off
& 511) << 12 |
426 (sz
& 4) << 21 | (sz
& 3) << 30); // stur (s|d|q)(dst),[x(bas),#(off)]
428 arm64_movimm(30, off
); // use x30 for offset
429 o(0x3c206800 | dst
| bas
<< 5 | (uint32_t)30 << 16 |
430 sz
<< 30 | (sz
& 4) << 21); // str (s|d|q)(dst),[x(bas),x30]
434 static void arm64_sym(int r
, Sym
*sym
, unsigned long addend
)
436 // Currently TCC's linker does not generate COPY relocations for
437 // STT_OBJECTs when tcc is invoked with "-run". This typically
438 // results in "R_AARCH64_ADR_PREL_PG_HI21 relocation failed" when
439 // a program refers to stdin. A workaround is to avoid that
440 // relocation and use only relocations with unlimited range.
443 if (avoid_adrp
|| (sym
->type
.t
& VT_WEAK
)) {
444 // (GCC uses a R_AARCH64_ABS64 in this case.)
445 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G0_NC
, addend
);
446 o(0xd2800000 | r
); // mov x(rt),#0,lsl #0
447 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G1_NC
, addend
);
448 o(0xf2a00000 | r
); // movk x(rt),#0,lsl #16
449 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G2_NC
, addend
);
450 o(0xf2c00000 | r
); // movk x(rt),#0,lsl #32
451 greloca(cur_text_section
, sym
, ind
, R_AARCH64_MOVW_UABS_G3
, addend
);
452 o(0xf2e00000 | r
); // movk x(rt),#0,lsl #48
455 greloca(cur_text_section
, sym
, ind
, R_AARCH64_ADR_PREL_PG_HI21
, addend
);
457 greloca(cur_text_section
, sym
, ind
, R_AARCH64_ADD_ABS_LO12_NC
, addend
);
458 o(0x91000000 | r
| r
<< 5);
462 ST_FUNC
void load(int r
, SValue
*sv
)
464 int svtt
= sv
->type
.t
;
465 int svr
= sv
->r
& ~VT_LVAL_TYPE
;
466 int svrv
= svr
& VT_VALMASK
;
467 uint64_t svcul
= (uint32_t)sv
->c
.i
;
468 svcul
= svcul
>> 31 & 1 ? svcul
- ((uint64_t)1 << 32) : svcul
;
470 if (svr
== (VT_LOCAL
| VT_LVAL
)) {
472 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 29, svcul
);
474 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
479 if ((svr
& ~VT_VALMASK
) == VT_LVAL
&& svrv
< VT_CONST
) {
481 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), intr(svrv
), 0);
483 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
484 intr(r
), intr(svrv
), 0);
488 if (svr
== (VT_CONST
| VT_LVAL
| VT_SYM
)) {
489 arm64_sym(30, sv
->sym
, svcul
); // use x30 for address
491 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 30, 0);
493 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
498 if (svr
== (VT_CONST
| VT_SYM
)) {
499 arm64_sym(intr(r
), sv
->sym
, svcul
);
503 if (svr
== VT_CONST
) {
504 if ((svtt
& VT_BTYPE
) != VT_VOID
)
505 arm64_movimm(intr(r
), arm64_type_size(svtt
) == 3 ?
506 sv
->c
.i
: (uint32_t)svcul
);
510 if (svr
< VT_CONST
) {
511 if (IS_FREG(r
) && IS_FREG(svr
))
512 if (svtt
== VT_LDOUBLE
)
513 o(0x4ea01c00 | fltr(r
) | fltr(svr
) << 5);
514 // mov v(r).16b,v(svr).16b
516 o(0x1e604000 | fltr(r
) | fltr(svr
) << 5); // fmov d(r),d(svr)
517 else if (!IS_FREG(r
) && !IS_FREG(svr
))
518 o(0xaa0003e0 | intr(r
) | intr(svr
) << 16); // mov x(r),x(svr)
524 if (svr
== VT_LOCAL
) {
526 o(0xd10003a0 | intr(r
) | -svcul
<< 10); // sub x(r),x29,#...
528 arm64_movimm(30, -svcul
); // use x30 for offset
529 o(0xcb0003a0 | intr(r
) | (uint32_t)30 << 16); // sub x(r),x29,x30
534 if (svr
== VT_JMP
|| svr
== VT_JMPI
) {
535 int t
= (svr
== VT_JMPI
);
536 arm64_movimm(intr(r
), t
);
537 o(0x14000002); // b .+8
539 arm64_movimm(intr(r
), t
^ 1);
543 if (svr
== (VT_LLOCAL
| VT_LVAL
)) {
544 arm64_ldrx(0, 3, 30, 29, svcul
); // use x30 for offset
546 arm64_ldrv(arm64_type_size(svtt
), fltr(r
), 30, 0);
548 arm64_ldrx(!(svtt
& VT_UNSIGNED
), arm64_type_size(svtt
),
553 printf("load(%x, (%x, %x, %llx))\n", r
, svtt
, sv
->r
, (long long)svcul
);
557 ST_FUNC
void store(int r
, SValue
*sv
)
559 int svtt
= sv
->type
.t
;
560 int svr
= sv
->r
& ~VT_LVAL_TYPE
;
561 int svrv
= svr
& VT_VALMASK
;
562 uint64_t svcul
= (uint32_t)sv
->c
.i
;
563 svcul
= svcul
>> 31 & 1 ? svcul
- ((uint64_t)1 << 32) : svcul
;
565 if (svr
== (VT_LOCAL
| VT_LVAL
)) {
567 arm64_strv(arm64_type_size(svtt
), fltr(r
), 29, svcul
);
569 arm64_strx(arm64_type_size(svtt
), intr(r
), 29, svcul
);
573 if ((svr
& ~VT_VALMASK
) == VT_LVAL
&& svrv
< VT_CONST
) {
575 arm64_strv(arm64_type_size(svtt
), fltr(r
), intr(svrv
), 0);
577 arm64_strx(arm64_type_size(svtt
), intr(r
), intr(svrv
), 0);
581 if (svr
== (VT_CONST
| VT_LVAL
| VT_SYM
)) {
582 arm64_sym(30, sv
->sym
, svcul
); // use x30 for address
584 arm64_strv(arm64_type_size(svtt
), fltr(r
), 30, 0);
586 arm64_strx(arm64_type_size(svtt
), intr(r
), 30, 0);
590 printf("store(%x, (%x, %x, %llx))\n", r
, svtt
, sv
->r
, (long long)svcul
);
594 static void arm64_gen_bl_or_b(int b
)
596 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
) {
597 assert(!b
&& (vtop
->r
& VT_SYM
));
598 greloc(cur_text_section
, vtop
->sym
, ind
, R_AARCH64_CALL26
);
599 o(0x94000000); // bl .
602 o(0xd61f0000 | (uint32_t)!b
<< 21 | intr(gv(RC_R30
)) << 5); // br/blr
605 static int arm64_hfa_aux(CType
*type
, int *fsize
, int num
)
607 if (is_float(type
->t
)) {
608 int a
, n
= type_size(type
, &a
);
609 if (num
>= 4 || (*fsize
&& *fsize
!= n
))
614 else if ((type
->t
& VT_BTYPE
) == VT_STRUCT
) {
615 int is_struct
= 0; // rather than union
617 for (field
= type
->ref
->next
; field
; field
= field
->next
)
624 for (field
= type
->ref
->next
; field
; field
= field
->next
) {
625 if (field
->c
!= (num
- num0
) * *fsize
)
627 num
= arm64_hfa_aux(&field
->type
, fsize
, num
);
631 if (type
->ref
->c
!= (num
- num0
) * *fsize
)
637 for (field
= type
->ref
->next
; field
; field
= field
->next
) {
638 int num1
= arm64_hfa_aux(&field
->type
, fsize
, num0
);
641 num
= num1
< num
? num
: num1
;
643 if (type
->ref
->c
!= (num
- num0
) * *fsize
)
648 else if (type
->t
& VT_ARRAY
) {
652 num1
= arm64_hfa_aux(&type
->ref
->type
, fsize
, num
);
653 if (num1
== -1 || (num1
!= num
&& type
->ref
->c
> 4))
655 num1
= num
+ type
->ref
->c
* (num1
- num
);
663 static int arm64_hfa(CType
*type
, int *fsize
)
665 if ((type
->t
& VT_BTYPE
) == VT_STRUCT
|| (type
->t
& VT_ARRAY
)) {
667 int n
= arm64_hfa_aux(type
, &sz
, 0);
668 if (0 < n
&& n
<= 4) {
677 static unsigned long arm64_pcs_aux(int n
, CType
**type
, unsigned long *a
)
679 int nx
= 0; // next integer register
680 int nv
= 0; // next vector register
681 unsigned long ns
= 32; // next stack offset
684 for (i
= 0; i
< n
; i
++) {
685 int hfa
= arm64_hfa(type
[i
], 0);
688 if ((type
[i
]->t
& VT_ARRAY
) ||
689 (type
[i
]->t
& VT_BTYPE
) == VT_FUNC
)
692 size
= type_size(type
[i
], &align
);
697 else if (size
> 16) {
698 // B.3: replace with pointer
700 a
[i
] = nx
++ << 1 | 1;
708 else if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
)
710 size
= (size
+ 7) & ~7;
713 if (is_float(type
[i
]->t
) && nv
< 8) {
714 a
[i
] = 16 + (nv
++ << 1);
719 if (hfa
&& nv
+ hfa
<= 8) {
720 a
[i
] = 16 + (nv
<< 1);
728 size
= (size
+ 7) & ~7;
732 if (hfa
|| (type
[i
]->t
& VT_BTYPE
) == VT_LDOUBLE
) {
734 ns
= (ns
+ align
- 1) & -align
;
738 if ((type
[i
]->t
& VT_BTYPE
) == VT_FLOAT
)
742 if (hfa
|| is_float(type
[i
]->t
)) {
749 if ((type
[i
]->t
& VT_BTYPE
) != VT_STRUCT
&& size
<= 8 && nx
< 8) {
759 if ((type
[i
]->t
& VT_BTYPE
) != VT_STRUCT
&& size
== 16 && nx
< 7) {
766 if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
&& size
<= (8 - nx
) * 8) {
768 nx
+= (size
+ 7) >> 3;
777 ns
= (ns
+ align
- 1) & -align
;
780 if ((type
[i
]->t
& VT_BTYPE
) == VT_STRUCT
) {
798 static unsigned long arm64_pcs(int n
, CType
**type
, unsigned long *a
)
803 if ((type
[0]->t
& VT_BTYPE
) == VT_VOID
)
806 arm64_pcs_aux(1, type
, a
);
807 assert(a
[0] == 0 || a
[0] == 1 || a
[0] == 16);
811 stack
= arm64_pcs_aux(n
, type
+ 1, a
+ 1);
815 for (i
= 0; i
<= n
; i
++) {
817 printf("arm64_pcs return: ");
819 printf("arm64_pcs arg %d: ", i
);
820 if (a
[i
] == (unsigned long)-1)
822 else if (a
[i
] == 1 && !i
)
823 printf("X8 pointer\n");
825 printf("X%lu%s\n", a
[i
] / 2, a
[i
] & 1 ? " pointer" : "");
827 printf("V%lu\n", a
[i
] / 2 - 8);
829 printf("stack %lu%s\n",
830 (a
[i
] - 32) & ~1, a
[i
] & 1 ? " pointer" : "");
837 ST_FUNC
void gfunc_call(int nb_args
)
841 unsigned long *a
, *a1
;
845 return_type
= &vtop
[-nb_args
].type
.ref
->type
;
846 if ((return_type
->t
& VT_BTYPE
) == VT_STRUCT
)
849 t
= tcc_malloc((nb_args
+ 1) * sizeof(*t
));
850 a
= tcc_malloc((nb_args
+ 1) * sizeof(*a
));
851 a1
= tcc_malloc((nb_args
+ 1) * sizeof(*a1
));
854 for (i
= 0; i
< nb_args
; i
++)
855 t
[nb_args
- i
] = &vtop
[-i
].type
;
857 stack
= arm64_pcs(nb_args
, t
, a
);
859 // Allocate space for structs replaced by pointer:
860 for (i
= nb_args
; i
; i
--)
862 SValue
*arg
= &vtop
[i
- nb_args
];
863 int align
, size
= type_size(&arg
->type
, &align
);
864 assert((arg
->type
.t
& VT_BTYPE
) == VT_STRUCT
);
865 stack
= (stack
+ align
- 1) & -align
;
870 stack
= (stack
+ 15) >> 4 << 4;
872 assert(stack
< 0x1000);
874 o(0xd10003ff | stack
<< 10); // sub sp,sp,#(n)
876 // First pass: set all values on stack
877 for (i
= nb_args
; i
; i
--) {
878 vpushv(vtop
- nb_args
+ i
);
881 // struct replaced by pointer
882 int r
= get_reg(RC_INT
);
883 arm64_spoff(intr(r
), a1
[i
]);
884 vset(&vtop
->type
, r
| VT_LVAL
, 0);
890 arm64_spoff(intr(r
), a1
[i
]);
891 arm64_strx(3, intr(r
), 31, (a
[i
] - 32) >> 1 << 1);
894 else if (a
[i
] >= 32) {
896 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
897 int r
= get_reg(RC_INT
);
898 arm64_spoff(intr(r
), a
[i
] - 32);
899 vset(&vtop
->type
, r
| VT_LVAL
, 0);
903 else if (is_float(vtop
->type
.t
)) {
905 arm64_strv(arm64_type_size(vtop
[0].type
.t
),
906 fltr(vtop
[0].r
), 31, a
[i
] - 32);
910 arm64_strx(arm64_type_size(vtop
[0].type
.t
),
911 intr(vtop
[0].r
), 31, a
[i
] - 32);
918 // Second pass: assign values to registers
919 for (i
= nb_args
; i
; i
--, vtop
--) {
920 if (a
[i
] < 16 && !(a
[i
] & 1)) {
921 // value in general-purpose registers
922 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
923 int align
, size
= type_size(&vtop
->type
, &align
);
924 vtop
->type
.t
= VT_PTR
;
927 arm64_ldrs(a
[i
] / 2, size
);
933 // struct replaced by pointer in register
934 arm64_spoff(a
[i
] / 2, a1
[i
]);
935 else if (a
[i
] < 32) {
936 // value in floating-point registers
937 if ((vtop
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
938 uint32_t j
, sz
, n
= arm64_hfa(&vtop
->type
, &sz
);
939 vtop
->type
.t
= VT_PTR
;
942 for (j
= 0; j
< n
; j
++)
944 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
946 j
<< 10); // ldr ([sdq])(*),[x30,#(j * sz)]
949 gv(RC_F(a
[i
] / 2 - 8));
953 if ((return_type
->t
& VT_BTYPE
) == VT_STRUCT
) {
955 // indirect return: set x8 and discard the stack value
960 // return in registers: keep the address for after the call
965 arm64_gen_bl_or_b(0);
968 o(0x910003ff | stack
<< 10); // add sp,sp,#(n)
971 int rt
= return_type
->t
;
972 int bt
= rt
& VT_BTYPE
;
973 if (bt
== VT_BYTE
|| bt
== VT_SHORT
)
974 // Promote small integers:
975 o(0x13001c00 | (bt
== VT_SHORT
) << 13 |
976 (uint32_t)!!(rt
& VT_UNSIGNED
) << 30); // [su]xt[bh] w0,w0
977 else if (bt
== VT_STRUCT
&& !(a
[0] & 1)) {
978 // A struct was returned in registers, so write it out:
982 int align
, size
= type_size(return_type
, &align
);
985 o(0xa9000500); // stp x0,x1,[x8]
987 arm64_strx(size
> 4 ? 3 : size
> 2 ? 2 : size
> 1, 0, 8, 0);
990 else if (a
[0] == 16) {
991 uint32_t j
, sz
, n
= arm64_hfa(return_type
, &sz
);
992 for (j
= 0; j
< n
; j
++)
994 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
996 j
<< 10); // str ([sdq])(*),[x8,#(j * sz)]
1006 static unsigned long arm64_func_va_list_stack
;
1007 static int arm64_func_va_list_gr_offs
;
1008 static int arm64_func_va_list_vr_offs
;
1009 static int arm64_func_sub_sp_offset
;
1011 ST_FUNC
void gfunc_prolog(CType
*func_type
)
1019 // Why doesn't the caller (gen_function) set func_vt?
1020 func_vt
= func_type
->ref
->type
;
1021 func_vc
= 144; // offset of where x8 is stored
1023 for (sym
= func_type
->ref
; sym
; sym
= sym
->next
)
1025 t
= tcc_malloc(n
* sizeof(*t
));
1026 a
= tcc_malloc(n
* sizeof(*a
));
1028 for (sym
= func_type
->ref
; sym
; sym
= sym
->next
)
1029 t
[i
++] = &sym
->type
;
1031 arm64_func_va_list_stack
= arm64_pcs(n
- 1, t
, a
);
1033 o(0xa9b27bfd); // stp x29,x30,[sp,#-224]!
1034 o(0xad0087e0); // stp q0,q1,[sp,#16]
1035 o(0xad018fe2); // stp q2,q3,[sp,#48]
1036 o(0xad0297e4); // stp q4,q5,[sp,#80]
1037 o(0xad039fe6); // stp q6,q7,[sp,#112]
1038 o(0xa90923e8); // stp x8,x8,[sp,#144]
1039 o(0xa90a07e0); // stp x0,x1,[sp,#160]
1040 o(0xa90b0fe2); // stp x2,x3,[sp,#176]
1041 o(0xa90c17e4); // stp x4,x5,[sp,#192]
1042 o(0xa90d1fe6); // stp x6,x7,[sp,#208]
1044 arm64_func_va_list_gr_offs
= -64;
1045 arm64_func_va_list_vr_offs
= -128;
1047 for (i
= 1, sym
= func_type
->ref
->next
; sym
; i
++, sym
= sym
->next
) {
1048 int off
= (a
[i
] < 16 ? 160 + a
[i
] / 2 * 8 :
1049 a
[i
] < 32 ? 16 + (a
[i
] - 16) / 2 * 16 :
1050 224 + ((a
[i
] - 32) >> 1 << 1));
1051 sym_push(sym
->v
& ~SYM_FIELD
, &sym
->type
,
1052 (a
[i
] & 1 ? VT_LLOCAL
: VT_LOCAL
) | lvalue_type(sym
->type
.t
),
1056 int align
, size
= type_size(&sym
->type
, &align
);
1057 arm64_func_va_list_gr_offs
= (a
[i
] / 2 - 7 +
1058 (!(a
[i
] & 1) && size
> 8)) * 8;
1060 else if (a
[i
] < 32) {
1061 uint32_t hfa
= arm64_hfa(&sym
->type
, 0);
1062 arm64_func_va_list_vr_offs
= (a
[i
] / 2 - 16 +
1063 (hfa
? hfa
: 1)) * 16;
1066 // HFAs of float and double need to be written differently:
1067 if (16 <= a
[i
] && a
[i
] < 32 && (sym
->type
.t
& VT_BTYPE
) == VT_STRUCT
) {
1068 uint32_t j
, sz
, k
= arm64_hfa(&sym
->type
, &sz
);
1070 for (j
= 0; j
< k
; j
++) {
1071 o(0x3d0003e0 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
1072 ((a
[i
] - 16) / 2 + j
) | (off
/ sz
+ j
) << 10);
1073 // str ([sdq])(*),[sp,#(j * sz)]
1081 o(0x910003fd); // mov x29,sp
1082 arm64_func_sub_sp_offset
= ind
;
1083 // In gfunc_epilog these will be replaced with code to decrement SP:
1084 o(0xd503201f); // nop
1085 o(0xd503201f); // nop
1089 ST_FUNC
void gen_va_start(void)
1092 --vtop
; // we don't need the "arg"
1094 r
= intr(gv(RC_INT
));
1096 if (arm64_func_va_list_stack
) {
1097 //xx could use add (immediate) here
1098 arm64_movimm(30, arm64_func_va_list_stack
+ 224);
1099 o(0x8b1e03be); // add x30,x29,x30
1102 o(0x910383be); // add x30,x29,#224
1103 o(0xf900001e | r
<< 5); // str x30,[x(r)]
1105 if (arm64_func_va_list_gr_offs
) {
1106 if (arm64_func_va_list_stack
)
1107 o(0x910383be); // add x30,x29,#224
1108 o(0xf900041e | r
<< 5); // str x30,[x(r),#8]
1111 if (arm64_func_va_list_vr_offs
) {
1112 o(0x910243be); // add x30,x29,#144
1113 o(0xf900081e | r
<< 5); // str x30,[x(r),#16]
1116 arm64_movimm(30, arm64_func_va_list_gr_offs
);
1117 o(0xb900181e | r
<< 5); // str w30,[x(r),#24]
1119 arm64_movimm(30, arm64_func_va_list_vr_offs
);
1120 o(0xb9001c1e | r
<< 5); // str w30,[x(r),#28]
1125 ST_FUNC
void gen_va_arg(CType
*t
)
1127 int align
, size
= type_size(t
, &align
);
1128 int fsize
, hfa
= arm64_hfa(t
, &fsize
);
1131 if (is_float(t
->t
)) {
1137 r0
= intr(gv(RC_INT
));
1138 r1
= get_reg(RC_INT
);
1139 vtop
[0].r
= r1
| lvalue_type(t
->t
);
1143 uint32_t n
= size
> 16 ? 8 : (size
+ 7) & -8;
1144 o(0xb940181e | r0
<< 5); // ldr w30,[x(r0),#24] // __gr_offs
1146 assert(0); // this path untested but needed for __uint128_t
1147 o(0x11003fde); // add w30,w30,#15
1148 o(0x121c6fde); // and w30,w30,#-16
1150 o(0x310003c0 | r1
| n
<< 10); // adds w(r1),w30,#(n)
1151 o(0x540000ad); // b.le .+20
1152 o(0xf9400000 | r1
| r0
<< 5); // ldr x(r1),[x(r0)] // __stack
1153 o(0x9100001e | r1
<< 5 | n
<< 10); // add x30,x(r1),#(n)
1154 o(0xf900001e | r0
<< 5); // str x30,[x(r0)] // __stack
1155 o(0x14000004); // b .+16
1156 o(0xb9001800 | r1
| r0
<< 5); // str w(r1),[x(r0),#24] // __gr_offs
1157 o(0xf9400400 | r1
| r0
<< 5); // ldr x(r1),[x(r0),#8] // __gr_top
1158 o(0x8b3ec000 | r1
| r1
<< 5); // add x(r1),x(r1),w30,sxtw
1160 o(0xf9400000 | r1
| r1
<< 5); // ldr x(r1),[x(r1)]
1163 uint32_t rsz
= hfa
<< 4;
1164 uint32_t ssz
= (size
+ 7) & -(uint32_t)8;
1166 o(0xb9401c1e | r0
<< 5); // ldr w30,[x(r0),#28] // __vr_offs
1167 o(0x310003c0 | r1
| rsz
<< 10); // adds w(r1),w30,#(rsz)
1168 b1
= ind
; o(0x5400000d); // b.le lab1
1169 o(0xf9400000 | r1
| r0
<< 5); // ldr x(r1),[x(r0)] // __stack
1171 o(0x91003c00 | r1
| r1
<< 5); // add x(r1),x(r1),#15
1172 o(0x927cec00 | r1
| r1
<< 5); // and x(r1),x(r1),#-16
1174 o(0x9100001e | r1
<< 5 | ssz
<< 10); // add x30,x(r1),#(ssz)
1175 o(0xf900001e | r0
<< 5); // str x30,[x(r0)] // __stack
1176 b2
= ind
; o(0x14000000); // b lab2
1178 write32le(cur_text_section
->data
+ b1
, 0x5400000d | (ind
- b1
) << 3);
1179 o(0xb9001c00 | r1
| r0
<< 5); // str w(r1),[x(r0),#28] // __vr_offs
1180 o(0xf9400800 | r1
| r0
<< 5); // ldr x(r1),[x(r0),#16] // __vr_top
1181 if (hfa
== 1 || fsize
== 16)
1182 o(0x8b3ec000 | r1
| r1
<< 5); // add x(r1),x(r1),w30,sxtw
1184 // We need to change the layout of this HFA.
1185 // Get some space on the stack using global variable "loc":
1186 loc
= (loc
- size
) & -(uint32_t)align
;
1187 o(0x8b3ec000 | 30 | r1
<< 5); // add x30,x(r1),w30,sxtw
1188 arm64_movimm(r1
, loc
);
1189 o(0x8b0003a0 | r1
| r1
<< 16); // add x(r1),x29,x(r1)
1190 o(0x4c402bdc | (uint32_t)fsize
<< 7 |
1191 (uint32_t)(hfa
== 2) << 15 |
1192 (uint32_t)(hfa
== 3) << 14); // ld1 {v28.(4s|2d),...},[x30]
1193 o(0x0d00801c | r1
<< 5 | (fsize
== 8) << 10 |
1194 (uint32_t)(hfa
!= 2) << 13 |
1195 (uint32_t)(hfa
!= 3) << 21); // st(hfa) {v28.(s|d),...}[0],[x(r1)]
1198 write32le(cur_text_section
->data
+ b2
, 0x14000000 | (ind
- b2
) >> 2);
1202 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
1203 int *align
, int *regsize
)
1208 ST_FUNC
void greturn(void)
1210 CType
*t
= &func_vt
;
1213 arm64_pcs(0, &t
, &a
);
1218 if ((func_vt
.t
& VT_BTYPE
) == VT_STRUCT
) {
1219 int align
, size
= type_size(&func_vt
, &align
);
1222 arm64_ldrs(0, size
);
1228 CType type
= func_vt
;
1230 vset(&type
, VT_LOCAL
| VT_LVAL
, func_vc
);
1237 if ((func_vt
.t
& VT_BTYPE
) == VT_STRUCT
) {
1238 uint32_t j
, sz
, n
= arm64_hfa(&vtop
->type
, &sz
);
1241 for (j
= 0; j
< n
; j
++)
1243 (sz
& 16) << 19 | -(sz
& 8) << 27 | (sz
& 4) << 29 |
1244 j
| j
<< 10); // ldr ([sdq])(*),[x0,#(j * sz)]
1254 ST_FUNC
void gfunc_epilog(void)
1257 // Insert instructions to subtract size of stack frame from SP.
1258 unsigned char *ptr
= cur_text_section
->data
+ arm64_func_sub_sp_offset
;
1259 uint64_t diff
= (-loc
+ 15) & ~15;
1260 if (!(diff
>> 24)) {
1261 if (diff
& 0xfff) // sub sp,sp,#(diff & 0xfff)
1262 write32le(ptr
, 0xd10003ff | (diff
& 0xfff) << 10);
1263 if (diff
>> 12) // sub sp,sp,#(diff >> 12),lsl #12
1264 write32le(ptr
+ 4, 0xd14003ff | (diff
>> 12) << 10);
1267 // In this case we may subtract more than necessary,
1268 // but always less than 17/16 of what we were aiming for.
1271 while (diff
>> 20) {
1272 diff
= (diff
+ 0xffff) >> 16;
1275 while (diff
>> 16) {
1276 diff
= (diff
+ 1) >> 1;
1279 write32le(ptr
, 0xd2800010 | diff
<< 5 | i
<< 21);
1280 // mov x16,#(diff),lsl #(16 * i)
1281 write32le(ptr
+ 4, 0xcb3063ff | j
<< 10);
1282 // sub sp,sp,x16,lsl #(j)
1285 o(0x910003bf); // mov sp,x29
1286 o(0xa8ce7bfd); // ldp x29,x30,[sp],#224
1288 o(0xd65f03c0); // ret
1291 // Generate forward branch to label:
1292 ST_FUNC
int gjmp(int t
)
1299 // Generate branch to known address:
1300 ST_FUNC
void gjmp_addr(int a
)
1302 assert(a
- ind
+ 0x8000000 < 0x10000000);
1303 o(0x14000000 | ((a
- ind
) >> 2 & 0x3ffffff));
1306 ST_FUNC
int gtst(int inv
, int t
)
1308 int bt
= vtop
->type
.t
& VT_BTYPE
;
1309 if (bt
== VT_LDOUBLE
) {
1310 uint32_t a
, b
, f
= fltr(gv(RC_FLOAT
));
1311 a
= get_reg(RC_INT
);
1314 b
= get_reg(RC_INT
);
1317 o(0x4e083c00 | a
| f
<< 5); // mov x(a),v(f).d[0]
1318 o(0x4e183c00 | b
| f
<< 5); // mov x(b),v(f).d[1]
1319 o(0xaa000400 | a
| a
<< 5 | b
<< 16); // orr x(a),x(a),x(b),lsl #1
1320 o(0xb4000040 | a
| !!inv
<< 24); // cbz/cbnz x(a),.+8
1323 else if (bt
== VT_FLOAT
|| bt
== VT_DOUBLE
) {
1324 uint32_t a
= fltr(gv(RC_FLOAT
));
1325 o(0x1e202008 | a
<< 5 | (bt
!= VT_FLOAT
) << 22); // fcmp
1326 o(0x54000040 | !!inv
); // b.eq/b.ne .+8
1329 uint32_t ll
= (bt
== VT_PTR
|| bt
== VT_LLONG
);
1330 uint32_t a
= intr(gv(RC_INT
));
1331 o(0x34000040 | a
| !!inv
<< 24 | ll
<< 31); // cbz/cbnz wA,.+8
1337 static int arm64_iconst(uint64_t *val
, SValue
*sv
)
1339 if ((sv
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) != VT_CONST
)
1343 *val
= ((t
& VT_BTYPE
) == VT_LLONG
? sv
->c
.i
:
1345 (t
& VT_UNSIGNED
? 0 : -(sv
->c
.i
& 0x80000000)));
1350 static int arm64_gen_opic(int op
, uint32_t l
, int rev
, uint64_t val
,
1351 uint32_t x
, uint32_t a
)
1353 if (op
== '-' && !rev
) {
1357 val
= l
? val
: (uint32_t)val
;
1362 uint32_t s
= l
? val
>> 63 : val
>> 31;
1363 val
= s
? -val
: val
;
1364 val
= l
? val
: (uint32_t)val
;
1365 if (!(val
& ~(uint64_t)0xfff))
1366 o(0x11000000 | l
<< 31 | s
<< 30 | x
| a
<< 5 | val
<< 10);
1367 else if (!(val
& ~(uint64_t)0xfff000))
1368 o(0x11400000 | l
<< 31 | s
<< 30 | x
| a
<< 5 | val
>> 12 << 10);
1370 arm64_movimm(30, val
); // use x30
1371 o(0x0b1e0000 | l
<< 31 | s
<< 30 | x
| a
<< 5);
1378 o(0x4b0003e0 | l
<< 31 | x
| a
<< 16); // neg
1379 else if (val
== (l
? (uint64_t)-1 : (uint32_t)-1))
1380 o(0x2a2003e0 | l
<< 31 | x
| a
<< 16); // mvn
1382 arm64_movimm(30, val
); // use x30
1383 o(0x4b0003c0 | l
<< 31 | x
| a
<< 16); // sub
1388 if (val
== -1 || (val
== 0xffffffff && !l
)) {
1389 o(0x2a2003e0 | l
<< 31 | x
| a
<< 16); // mvn
1395 int e
= arm64_encode_bimm64(l
? val
: val
| val
<< 32);
1398 o((op
== '&' ? 0x12000000 :
1399 op
== '|' ? 0x32000000 : 0x52000000) |
1400 l
<< 31 | x
| a
<< 5 | (uint32_t)e
<< 10);
1407 uint32_t n
= 32 << l
;
1408 val
= val
& (n
- 1);
1413 else if (op
== TOK_SHL
)
1414 o(0x53000000 | l
<< 31 | l
<< 22 | x
| a
<< 5 |
1415 (n
- val
) << 16 | (n
- 1 - val
) << 10); // lsl
1417 o(0x13000000 | (op
== TOK_SHR
) << 30 | l
<< 31 | l
<< 22 |
1418 x
| a
<< 5 | val
<< 16 | (n
- 1) << 10); // lsr/asr
1426 static void arm64_gen_opil(int op
, uint32_t l
)
1430 // Special treatment for operations with a constant operand:
1435 if (arm64_iconst(0, &vtop
[0])) {
1439 if (arm64_iconst(&val
, &vtop
[-1])) {
1441 a
= intr(vtop
[0].r
);
1443 x
= get_reg(RC_INT
);
1445 if (arm64_gen_opic(op
, l
, rev
, val
, intr(x
), a
)) {
1456 gv2(RC_INT
, RC_INT
);
1457 assert(vtop
[-1].r
< VT_CONST
&& vtop
[0].r
< VT_CONST
);
1458 a
= intr(vtop
[-1].r
);
1459 b
= intr(vtop
[0].r
);
1461 x
= get_reg(RC_INT
);
1468 // Use x30 for quotient:
1469 o(0x1ac00c00 | l
<< 31 | 30 | a
<< 5 | b
<< 16); // sdiv
1470 o(0x1b008000 | l
<< 31 | x
| (uint32_t)30 << 5 |
1471 b
<< 16 | a
<< 10); // msub
1474 o(0x0a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // and
1477 o(0x1b007c00 | l
<< 31 | x
| a
<< 5 | b
<< 16); // mul
1480 o(0x0b000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // add
1483 o(0x4b000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // sub
1486 o(0x1ac00c00 | l
<< 31 | x
| a
<< 5 | b
<< 16); // sdiv
1489 o(0x4a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // eor
1492 o(0x2a000000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // orr
1495 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1496 o(0x1a9f17e0 | x
); // cset wA,eq
1499 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1500 o(0x1a9fb7e0 | x
); // cset wA,ge
1503 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1504 o(0x1a9fd7e0 | x
); // cset wA,gt
1507 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1508 o(0x1a9fc7e0 | x
); // cset wA,le
1511 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1512 o(0x1a9fa7e0 | x
); // cset wA,lt
1515 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1516 o(0x1a9f07e0 | x
); // cset wA,ne
1519 o(0x1ac02800 | l
<< 31 | x
| a
<< 5 | b
<< 16); // asr
1522 o(0x1ac02000 | l
<< 31 | x
| a
<< 5 | b
<< 16); // lsl
1525 o(0x1ac02400 | l
<< 31 | x
| a
<< 5 | b
<< 16); // lsr
1529 o(0x1ac00800 | l
<< 31 | x
| a
<< 5 | b
<< 16); // udiv
1532 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1533 o(0x1a9f37e0 | x
); // cset wA,cs
1536 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1537 o(0x1a9f97e0 | x
); // cset wA,hi
1540 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1541 o(0x1a9f27e0 | x
); // cset wA,cc
1544 o(0x6b00001f | l
<< 31 | a
<< 5 | b
<< 16); // cmp
1545 o(0x1a9f87e0 | x
); // cset wA,ls
1548 // Use x30 for quotient:
1549 o(0x1ac00800 | l
<< 31 | 30 | a
<< 5 | b
<< 16); // udiv
1550 o(0x1b008000 | l
<< 31 | x
| (uint32_t)30 << 5 |
1551 b
<< 16 | a
<< 10); // msub
1558 ST_FUNC
void gen_opi(int op
)
1560 arm64_gen_opil(op
, 0);
1563 ST_FUNC
void gen_opl(int op
)
1565 arm64_gen_opil(op
, 1);
1568 ST_FUNC
void gen_opf(int op
)
1570 uint32_t x
, a
, b
, dbl
;
1572 if (vtop
[0].type
.t
== VT_LDOUBLE
) {
1573 CType type
= vtop
[0].type
;
1577 case '*': func
= TOK___multf3
; break;
1578 case '+': func
= TOK___addtf3
; break;
1579 case '-': func
= TOK___subtf3
; break;
1580 case '/': func
= TOK___divtf3
; break;
1581 case TOK_EQ
: func
= TOK___eqtf2
; cond
= 1; break;
1582 case TOK_NE
: func
= TOK___netf2
; cond
= 0; break;
1583 case TOK_LT
: func
= TOK___lttf2
; cond
= 10; break;
1584 case TOK_GE
: func
= TOK___getf2
; cond
= 11; break;
1585 case TOK_LE
: func
= TOK___letf2
; cond
= 12; break;
1586 case TOK_GT
: func
= TOK___gttf2
; cond
= 13; break;
1587 default: assert(0); break;
1589 vpush_global_sym(&func_old_type
, func
);
1593 vtop
->r
= cond
< 0 ? REG_FRET
: REG_IRET
;
1597 o(0x7100001f); // cmp w0,#0
1598 o(0x1a9f07e0 | (uint32_t)cond
<< 12); // cset w0,(cond)
1603 dbl
= vtop
[0].type
.t
!= VT_FLOAT
;
1604 gv2(RC_FLOAT
, RC_FLOAT
);
1605 assert(vtop
[-1].r
< VT_CONST
&& vtop
[0].r
< VT_CONST
);
1606 a
= fltr(vtop
[-1].r
);
1607 b
= fltr(vtop
[0].r
);
1610 case TOK_EQ
: case TOK_NE
:
1611 case TOK_LT
: case TOK_GE
: case TOK_LE
: case TOK_GT
:
1612 x
= get_reg(RC_INT
);
1618 x
= get_reg(RC_FLOAT
);
1627 o(0x1e200800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fmul
1630 o(0x1e202800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fadd
1633 o(0x1e203800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fsub
1636 o(0x1e201800 | dbl
<< 22 | x
| a
<< 5 | b
<< 16); // fdiv
1639 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1640 o(0x1a9f17e0 | x
); // cset w(x),eq
1643 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1644 o(0x1a9fb7e0 | x
); // cset w(x),ge
1647 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1648 o(0x1a9fd7e0 | x
); // cset w(x),gt
1651 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1652 o(0x1a9f87e0 | x
); // cset w(x),ls
1655 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1656 o(0x1a9f57e0 | x
); // cset w(x),mi
1659 o(0x1e202000 | dbl
<< 22 | a
<< 5 | b
<< 16); // fcmp
1660 o(0x1a9f07e0 | x
); // cset w(x),ne
1667 // Generate sign extension from 32 to 64 bits:
1668 ST_FUNC
void gen_cvt_sxtw(void)
1670 uint32_t r
= intr(gv(RC_INT
));
1671 o(0x93407c00 | r
| r
<< 5); // sxtw x(r),w(r)
1674 ST_FUNC
void gen_cvt_itof(int t
)
1676 if (t
== VT_LDOUBLE
) {
1677 int f
= vtop
->type
.t
;
1678 int func
= (f
& VT_BTYPE
) == VT_LLONG
?
1679 (f
& VT_UNSIGNED
? TOK___floatunditf
: TOK___floatditf
) :
1680 (f
& VT_UNSIGNED
? TOK___floatunsitf
: TOK___floatsitf
);
1681 vpush_global_sym(&func_old_type
, func
);
1690 int d
, n
= intr(gv(RC_INT
));
1691 int s
= !(vtop
->type
.t
& VT_UNSIGNED
);
1692 uint32_t l
= ((vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
);
1694 d
= get_reg(RC_FLOAT
);
1697 o(0x1e220000 | (uint32_t)!s
<< 16 |
1698 (uint32_t)(t
!= VT_FLOAT
) << 22 | fltr(d
) |
1699 l
<< 31 | n
<< 5); // [us]cvtf [sd](d),[wx](n)
1703 ST_FUNC
void gen_cvt_ftoi(int t
)
1705 if ((vtop
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
) {
1706 int func
= (t
& VT_BTYPE
) == VT_LLONG
?
1707 (t
& VT_UNSIGNED
? TOK___fixunstfdi
: TOK___fixtfdi
) :
1708 (t
& VT_UNSIGNED
? TOK___fixunstfsi
: TOK___fixtfsi
);
1709 vpush_global_sym(&func_old_type
, func
);
1718 int d
, n
= fltr(gv(RC_FLOAT
));
1719 uint32_t l
= ((vtop
->type
.t
& VT_BTYPE
) != VT_FLOAT
);
1721 d
= get_reg(RC_INT
);
1725 (uint32_t)!!(t
& VT_UNSIGNED
) << 16 |
1726 (uint32_t)((t
& VT_BTYPE
) == VT_LLONG
) << 31 | intr(d
) |
1727 l
<< 22 | n
<< 5); // fcvtz[su] [wx](d),[sd](n)
1731 ST_FUNC
void gen_cvt_ftof(int t
)
1733 int f
= vtop
[0].type
.t
;
1734 assert(t
== VT_FLOAT
|| t
== VT_DOUBLE
|| t
== VT_LDOUBLE
);
1735 assert(f
== VT_FLOAT
|| f
== VT_DOUBLE
|| f
== VT_LDOUBLE
);
1739 if (t
== VT_LDOUBLE
|| f
== VT_LDOUBLE
) {
1740 int func
= (t
== VT_LDOUBLE
) ?
1741 (f
== VT_FLOAT
? TOK___extendsftf2
: TOK___extenddftf2
) :
1742 (t
== VT_FLOAT
? TOK___trunctfsf2
: TOK___trunctfdf2
);
1743 vpush_global_sym(&func_old_type
, func
);
1753 assert(vtop
[0].r
< VT_CONST
);
1754 a
= fltr(vtop
[0].r
);
1756 x
= get_reg(RC_FLOAT
);
1762 o(0x1e22c000 | x
| a
<< 5); // fcvt d(x),s(a)
1764 o(0x1e624000 | x
| a
<< 5); // fcvt s(x),d(a)
1768 ST_FUNC
void ggoto(void)
1770 arm64_gen_bl_or_b(1);
1774 ST_FUNC
void gen_clear_cache(void)
1776 uint32_t beg
, end
, dsz
, isz
, p
, lab1
, b1
;
1777 gv2(RC_INT
, RC_INT
);
1779 vtop
->r
= get_reg(RC_INT
);
1781 vtop
->r
= get_reg(RC_INT
);
1783 vtop
->r
= get_reg(RC_INT
);
1784 beg
= intr(vtop
[-4].r
); // x0
1785 end
= intr(vtop
[-3].r
); // x1
1786 dsz
= intr(vtop
[-2].r
); // x2
1787 isz
= intr(vtop
[-1].r
); // x3
1788 p
= intr(vtop
[0].r
); // x4
1791 o(0xd53b0020 | isz
); // mrs x(isz),ctr_el0
1792 o(0x52800080 | p
); // mov w(p),#4
1793 o(0x53104c00 | dsz
| isz
<< 5); // ubfx w(dsz),w(isz),#16,#4
1794 o(0x1ac02000 | dsz
| p
<< 5 | dsz
<< 16); // lsl w(dsz),w(p),w(dsz)
1795 o(0x12000c00 | isz
| isz
<< 5); // and w(isz),w(isz),#15
1796 o(0x1ac02000 | isz
| p
<< 5 | isz
<< 16); // lsl w(isz),w(p),w(isz)
1797 o(0x51000400 | p
| dsz
<< 5); // sub w(p),w(dsz),#1
1798 o(0x8a240004 | p
| beg
<< 5 | p
<< 16); // bic x(p),x(beg),x(p)
1799 b1
= ind
; o(0x14000000); // b
1801 o(0xd50b7b20 | p
); // dc cvau,x(p)
1802 o(0x8b000000 | p
| p
<< 5 | dsz
<< 16); // add x(p),x(p),x(dsz)
1803 write32le(cur_text_section
->data
+ b1
, 0x14000000 | (ind
- b1
) >> 2);
1804 o(0xeb00001f | p
<< 5 | end
<< 16); // cmp x(p),x(end)
1805 o(0x54ffffa3 | ((lab1
- ind
) << 3 & 0xffffe0)); // b.cc lab1
1806 o(0xd5033b9f); // dsb ish
1807 o(0x51000400 | p
| isz
<< 5); // sub w(p),w(isz),#1
1808 o(0x8a240004 | p
| beg
<< 5 | p
<< 16); // bic x(p),x(beg),x(p)
1809 b1
= ind
; o(0x14000000); // b
1811 o(0xd50b7520 | p
); // ic ivau,x(p)
1812 o(0x8b000000 | p
| p
<< 5 | isz
<< 16); // add x(p),x(p),x(isz)
1813 write32le(cur_text_section
->data
+ b1
, 0x14000000 | (ind
- b1
) >> 2);
1814 o(0xeb00001f | p
<< 5 | end
<< 16); // cmp x(p),x(end)
1815 o(0x54ffffa3 | ((lab1
- ind
) << 3 & 0xffffe0)); // b.cc lab1
1816 o(0xd5033b9f); // dsb ish
1817 o(0xd5033fdf); // isb
1820 ST_FUNC
void gen_vla_sp_save(int addr
) {
1821 uint32_t r
= intr(get_reg(RC_INT
));
1822 o(0x910003e0 | r
); // mov x(r),sp
1823 arm64_strx(3, r
, 29, addr
);
1826 ST_FUNC
void gen_vla_sp_restore(int addr
) {
1827 // Use x30 because this function can be called when there
1828 // is a live return value in x0 but there is nothing on
1829 // the value stack to prevent get_reg from returning x0.
1831 arm64_ldrx(0, 3, r
, 29, addr
);
1832 o(0x9100001f | r
<< 5); // mov sp,x(r)
1835 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
) {
1836 uint32_t r
= intr(gv(RC_INT
));
1837 o(0x91003c00 | r
| r
<< 5); // add x(r),x(r),#15
1838 o(0x927cec00 | r
| r
<< 5); // bic x(r),x(r),#15
1839 o(0xcb2063ff | r
<< 16); // sub sp,sp,x(r)
1843 /* end of A64 code generator */
1844 /*************************************************************/
1846 /*************************************************************/