1 #ifdef TARGET_DEFS_ONLY
3 // Number of registers available to allocator:
4 #define NB_REGS 16 // x10-x17 aka a0-a7, f10-f17 aka fa0-fa7
6 #define TREG_R(x) (x) // x = 0..7
7 #define TREG_F(x) (x + 8) // x = 0..7
9 // Register classes sorted from more general to more precise:
10 #define RC_INT (1 << 0)
11 #define RC_FLOAT (1 << 1)
12 #define RC_R(x) (1 << (2 + (x))) // x = 0..7
13 #define RC_F(x) (1 << (10 + (x))) // x = 0..7
15 #define RC_IRET (RC_R(0)) // int return register class
16 #define RC_FRET (RC_F(0)) // float return register class
18 #define REG_IRET (TREG_R(0)) // int return register number
19 #define REG_FRET (TREG_F(0)) // float return register number
23 #define LDOUBLE_SIZE 16
24 #define LDOUBLE_ALIGN 16
28 #define CHAR_IS_UNSIGNED
39 ST_DATA
const int reg_classes
[NB_REGS
] = {
58 static int ireg(int r
)
64 assert(r
>= 0 && r
< 8);
65 return r
+ 10; // tccrX --> aX == x(10+X)
68 static int is_ireg(int r
)
70 return r
< 8 || r
== TREG_RA
|| r
== TREG_SP
;
73 static int freg(int r
)
75 assert(r
>= 8 && r
< 16);
76 return r
- 8 + 10; // tccfX --> faX == f(10+X)
79 static int is_freg(int r
)
81 return r
>= 8 && r
< 16;
84 ST_FUNC
void o(unsigned int c
)
89 if (ind1
> cur_text_section
->data_allocated
)
90 section_realloc(cur_text_section
, ind1
);
91 write32le(cur_text_section
->data
+ ind
, c
);
95 static void EI(uint32_t opcode
, uint32_t func3
,
96 uint32_t rd
, uint32_t rs1
, uint32_t imm
)
98 assert(! ((imm
+ (1 << 11)) >> 12));
99 o(opcode
| (func3
<< 12) | (rd
<< 7) | (rs1
<< 15) | (imm
<< 20));
102 static void ES(uint32_t opcode
, uint32_t func3
,
103 uint32_t rs1
, uint32_t rs2
, uint32_t imm
)
105 assert(! ((imm
+ (1 << 11)) >> 12));
106 o(opcode
| (func3
<< 12) | ((imm
& 0x1f) << 7) | (rs1
<< 15)
107 | (rs2
<< 20) | ((imm
>> 5) << 25));
110 // Patch all branches in list pointed to by t to branch to a:
111 ST_FUNC
void gsym_addr(int t_
, int a_
)
116 unsigned char *ptr
= cur_text_section
->data
+ t
;
117 uint32_t next
= read32le(ptr
);
118 uint32_t r
= a
- t
, imm
;
119 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
120 tcc_error("out-of-range branch chain");
121 imm
= (((r
>> 12) & 0xff) << 12)
122 | (((r
>> 11) & 1) << 20)
123 | (((r
>> 1) & 0x3ff) << 21)
124 | (((r
>> 20) & 1) << 31);
125 write32le(ptr
, r
== 4 ? 0x33 : 0x6f | imm
); // nop || j imm
130 ST_FUNC
void load(int r
, SValue
*sv
)
133 int v
= fr
& VT_VALMASK
;
134 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
136 int bt
= sv
->type
.t
& VT_BTYPE
;
137 int align
, size
= type_size(&sv
->type
, &align
);
139 int func3
, opcode
= 0x03;
141 assert(bt
== VT_DOUBLE
|| bt
== VT_FLOAT
);
143 func3
= bt
== VT_DOUBLE
? 3 : 2;
148 func3
= size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3;
149 if (size
< 8 && !is_float(sv
->type
.t
) && (sv
->type
.t
& VT_UNSIGNED
))
153 if (((unsigned)fc
+ (1 << 11)) >> 12)
154 tcc_error("unimp: load(large local ofs) (0x%x)", fc
);
155 EI(opcode
, func3
, rr
, 8, fc
); // l[bhwd][u]/fl[wd] RR, fc(s0)
156 } else if (v
< VT_CONST
) {
157 /*if (((unsigned)fc + (1 << 11)) >> 12)
158 tcc_error("unimp: load(large addend) (0x%x)", fc);*/
159 fc
= 0; // XXX store ofs in LVAL(reg)
160 EI(opcode
, func3
, rr
, ireg(v
), fc
); // l[bhwd][u] RR, 0(V)
161 } else if (v
== VT_CONST
&& (fr
& VT_SYM
)) {
163 int addend
= 0, tempr
;
164 if (1 || ((unsigned)fc
+ (1 << 11)) >> 12)
167 greloca(cur_text_section
, sv
->sym
, ind
,
168 R_RISCV_PCREL_HI20
, addend
);
170 label
.v
= tok_alloc(".L0 ", 4)->tok
;
171 label
.type
.t
= VT_VOID
| VT_STATIC
;
173 label
.c
= 0; /* force new local ELF symbol */
174 put_extern_sym(&label
, cur_text_section
, ind
, 0);
175 tempr
= is_ireg(r
) ? rr
: ireg(get_reg(RC_INT
));
176 o(0x17 | (tempr
<< 7)); // auipc TR, 0 %pcrel_hi(sym)+addend
177 greloca(cur_text_section
, &label
, ind
,
178 R_RISCV_PCREL_LO12_I
, 0);
179 EI(opcode
, func3
, rr
, tempr
, fc
); // l[bhwd][u] RR, fc(TR)
180 } else if (v
== VT_LLOCAL
) {
182 if (((unsigned)fc
+ (1 << 11)) >> 12)
183 tcc_error("unimp: load(large local ofs) (0x%x)", fc
);
185 tempr
= ireg(get_reg(RC_INT
));
186 EI(0x03, 3, tempr
, 8, fc
); // ld TEMPR, fc(s0)
187 EI(opcode
, func3
, rr
, tempr
, 0); // l[bhwd][u] RR, 0(TEMPR)
189 tcc_error("unimp: load(non-local lval)");
191 } else if (v
== VT_CONST
) {
193 assert(!is_float(sv
->type
.t
) && is_ireg(r
));
195 tcc_error("unimp: load(very large const)");
198 greloca(cur_text_section
, sv
->sym
, ind
,
199 R_RISCV_PCREL_HI20
, fc
);
201 label
.v
= tok_alloc(".L0 ", 4)->tok
;
202 label
.type
.t
= VT_VOID
| VT_STATIC
;
204 label
.c
= 0; /* force new local ELF symbol */
205 put_extern_sym(&label
, cur_text_section
, ind
, 0);
206 o(0x17 | (rr
<< 7)); // auipc RR, 0 %call(func)
207 greloca(cur_text_section
, &label
, ind
,
208 R_RISCV_PCREL_LO12_I
, 0);
212 if (is_float(sv
->type
.t
))
213 tcc_error("unimp: load(float)");
214 if (((unsigned)fc
+ (1 << 11)) >> 12)
215 o(0x37 | (rr
<< 7) | ((0x800 + fc
) & 0xfffff000)), rb
= rr
; //lui RR, upper(fc)
216 EI(0x13, 0, rr
, rb
, fc
<< 20 >> 20); // addi R, x0|R, FC
217 } else if (v
== VT_LOCAL
) {
219 if (((unsigned)fc
+ (1 << 11)) >> 12)
220 tcc_error("unimp: load(addr large local ofs) (0x%x)", fc
);
221 EI(0x13, 0, rr
, 8, fc
); // addi R, s0, FC
222 } else if (v
< VT_CONST
) {
224 //assert(!fc); XXX support offseted regs
225 if (is_freg(r
) && is_freg(v
))
226 o(0x53 | (rr
<< 7) | (freg(v
) << 15) | (freg(v
) << 20) | ((bt
== VT_DOUBLE
? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
227 else if (is_ireg(r
) && is_ireg(v
))
228 EI(0x13, 0, rr
, ireg(v
), 0); // addi RR, V, 0 == mv RR, V
230 int func7
= is_ireg(r
) ? 0x70 : 0x78;
233 assert(size
== 4 || size
== 8);
234 o(0x53 | (rr
<< 7) | ((is_freg(v
) ? freg(v
) : ireg(v
)) << 15)
235 | (func7
<< 25)); // fmv.{w.x, x.w, d.x, x.d} RR, VR
237 } else if (v
== VT_CMP
) { // we rely on cmp_r to be the correct result
238 EI(0x13, 0, rr
, vtop
->cmp_r
, 0); // mv RR, CMP_R
239 } else if ((v
& ~1) == VT_JMP
) {
242 EI(0x13, 0, rr
, 0, t
); // addi RR, x0, t
245 EI(0x13, 0, rr
, 0, t
^ 1); // addi RR, x0, !t
247 tcc_error("unimp: load(non-const)");
250 ST_FUNC
void store(int r
, SValue
*sv
)
252 int fr
= sv
->r
& VT_VALMASK
;
253 int rr
= is_ireg(r
) ? ireg(r
) : freg(r
);
256 int bt
= ft
& VT_BTYPE
;
257 int align
, size
= type_size(&sv
->type
, &align
);
258 assert(!is_float(bt
) || is_freg(r
));
260 tcc_error("unimp: store(struct)");
262 tcc_error("unimp: large sized store");
263 assert(sv
->r
& VT_LVAL
);
264 if (fr
== VT_LOCAL
) {
265 if (((unsigned)fc
+ (1 << 11)) >> 12)
266 tcc_error("unimp: store(large local off) (0x%x)", fc
);
268 ES(0x27, size
== 4 ? 2 : 3, 8, rr
, fc
); // fs[wd] RR, fc(s0)
270 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
271 8, rr
, fc
); // s[bhwd] RR, fc(s0)
272 } else if (fr
< VT_CONST
) {
273 int ptrreg
= ireg(fr
);
274 /*if (((unsigned)fc + (1 << 11)) >> 12)
275 tcc_error("unimp: store(large addend) (0x%x)", fc);*/
276 fc
= 0; // XXX support offsets regs
278 ES(0x27, size
== 4 ? 2 : 3, ptrreg
, rr
, fc
); // fs[wd] RR, fc(PTRREG)
280 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
281 ptrreg
, rr
, fc
); // s[bhwd] RR, fc(PTRREG)
282 } else if (sv
->r
== (VT_CONST
| VT_SYM
| VT_LVAL
)) {
284 int tempr
, addend
= 0;
285 if (1 || ((unsigned)fc
+ (1 << 11)) >> 12)
288 tempr
= ireg(get_reg(RC_INT
));
289 greloca(cur_text_section
, sv
->sym
, ind
,
290 R_RISCV_PCREL_HI20
, addend
);
292 label
.v
= tok_alloc(".L0 ", 4)->tok
;
293 label
.type
.t
= VT_VOID
| VT_STATIC
;
295 label
.c
= 0; /* force new local ELF symbol */
296 put_extern_sym(&label
, cur_text_section
, ind
, 0);
297 o(0x17 | (tempr
<< 7)); // auipc TEMPR, 0 %pcrel_hi(sym)+addend
298 greloca(cur_text_section
, &label
, ind
,
299 R_RISCV_PCREL_LO12_S
, 0);
301 ES(0x27, size
== 4 ? 2 : 3, tempr
, rr
, fc
); // fs[wd] RR, fc(TEMPR)
303 ES(0x23, size
== 1 ? 0 : size
== 2 ? 1 : size
== 4 ? 2 : 3,
304 tempr
, rr
, fc
); // s[bhwd] RR, fc(TEMPR)
306 tcc_error("implement me: %s(!local)", __FUNCTION__
);
309 static void gcall(void)
311 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
312 ((vtop
->r
& VT_SYM
) && vtop
->c
.i
== (int)vtop
->c
.i
)) {
313 /* constant symbolic case -> simple relocation */
314 greloca(cur_text_section
, vtop
->sym
, ind
,
315 R_RISCV_CALL_PLT
, (int)vtop
->c
.i
);
316 o(0x17 | (1 << 7)); // auipc ra, 0 %call(func)
317 o(0x80e7); // jalr ra, 0 %call(func)
318 } else if ((vtop
->r
& VT_VALMASK
) < VT_CONST
) {
319 int r
= ireg(vtop
->r
& VT_VALMASK
);
320 EI(0x67, 0, 1, r
, 0); // jalr ra, 0(R)
325 EI(0x67, 0, 1, r
, 0); // jalr ra, 0(R)
329 ST_FUNC
void gfunc_call(int nb_args
)
331 int i
, align
, size
, aireg
, afreg
;
332 int info
[nb_args
? nb_args
: 1];
333 int stack_adj
= 0, ofs
;
337 sa
= vtop
[-nb_args
].type
.ref
->next
;
338 for (i
= 0; i
< nb_args
; i
++) {
340 sv
= &vtop
[1 + i
- nb_args
];
341 sv
->type
.t
&= ~VT_ARRAY
; // XXX this should be done in tccgen.c
342 size
= type_size(&sv
->type
, &align
);
343 if (size
> 8 || ((sv
->type
.t
& VT_BTYPE
) == VT_STRUCT
))
344 tcc_error("unimp: call arg %d wrong type", nb_args
- i
);
345 pareg
= sa
&& is_float(sv
->type
.t
) ? &afreg
: &aireg
;
347 info
[i
] = *pareg
+ (sa
&& is_float(sv
->type
.t
) ? 8 : 0);
351 stack_adj
+= (size
+ align
- 1) & -align
;
356 stack_adj
= (stack_adj
+ 15) & -16;
358 EI(0x13, 0, 2, 2, -stack_adj
); // addi sp, sp, -adj
359 for (i
= ofs
= 0; i
< nb_args
; i
++) {
360 if (1 && info
[i
] >= 16) {
362 size
= type_size(&vtop
->type
, &align
);
363 /* Once we support offseted regs we can do this:
364 vset(&vtop->type, TREG_SP | VT_LVAL, ofs);
365 to construct the lvalue for the outgoing stack slot,
366 until then we have to jump through hoops. */
367 vset(&char_pointer_type
, TREG_SP
, 0);
371 vtop
->type
= vtop
[-1].type
;
375 ofs
+= (size
+ align
- 1) & -align
;
376 ofs
= (ofs
+ 7) & -8;
380 for (i
= 0; i
< nb_args
; i
++) {
381 int r
= info
[nb_args
- 1 - i
];
384 gv(r
< 8 ? RC_R(r
) : RC_F(r
- 8));
392 EI(0x13, 0, 2, 2, stack_adj
); // addi sp, sp, adj
395 static int func_sub_sp_offset
;
397 ST_FUNC
void gfunc_prolog(CType
*func_type
)
399 int i
, addr
, align
, size
;
405 sym
= func_type
->ref
;
407 loc
= -16; // for ra and s0
408 func_sub_sp_offset
= ind
;
410 if (sym
->f
.func_type
== FUNC_ELLIPSIS
) {
411 tcc_error("unimp: vararg prologue");
415 addr
= 0; // XXX not correct
416 /* if the function returns a structure, then add an
417 implicit pointer parameter */
418 size
= type_size(&func_vt
, &align
);
419 if (size
> 2 * XLEN
) {
420 tcc_error("unimp: struct return");
423 /* define parameters */
424 while ((sym
= sym
->next
) != NULL
) {
426 size
= type_size(type
, &align
);
427 if (size
> 2 * XLEN
) {
429 addr
= (addr
+ align
- 1) & -align
;
436 if (regcount
+ (is_float(type
->t
) ? afreg
: aireg
) >= 8)
440 for (i
= 0; i
< regcount
; i
++) {
441 if (is_float(type
->t
)) {
442 tcc_error("unimp: float args");
444 ES(0x23, 3, 8, 10 + aireg
, loc
+ i
*8); // sd aX, loc(s0) // XXX
449 sym_push(sym
->v
& ~SYM_FIELD
, type
,
450 VT_LOCAL
| lvalue_type(type
->t
), param_addr
);
454 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
,
455 int *ret_align
, int *regsize
)
457 /* generic code can only deal with structs of pow(2) sizes
458 (it always deals with whole registers), so go through our own
463 ST_FUNC
void gfunc_return(CType
*func_type
)
465 int align
, size
= type_size(func_type
, &align
);
466 if ((func_type
->t
& VT_BTYPE
) == VT_STRUCT
467 || size
> 2 * XLEN
) {
468 tcc_error("unimp: struct or large return");
470 if (is_float(func_type
->t
))
477 ST_FUNC
void gfunc_epilog(void)
481 v
= (-loc
+ 15) & -16;
483 EI(0x03, 3, 1, 2, v
- 8); // ld ra, v-8(sp)
484 EI(0x03, 3, 8, 2, v
- 16); // ld s0, v-16(sp)
485 EI(0x13, 0, 2, 2, v
); // addi sp, sp, v
486 EI(0x67, 0, 0, 1, 0); // jalr x0, 0(x1), aka ret
488 ind
= func_sub_sp_offset
;
489 EI(0x13, 0, 2, 2, -v
); // addi sp, sp, -v
490 ES(0x23, 3, 2, 1, v
- 8); // sd ra, v-8(sp)
491 ES(0x23, 3, 2, 8, v
- 16); // sd s0, v-16(sp)
492 EI(0x13, 0, 8, 2, v
); // addi s0, sp, v
496 ST_FUNC
void gen_va_start(void)
498 tcc_error("implement me: %s", __FUNCTION__
);
501 ST_FUNC
void gen_va_arg(CType
*t
)
503 tcc_error("implement me: %s", __FUNCTION__
);
506 ST_FUNC
void gen_fill_nops(int bytes
)
508 tcc_error("implement me: %s", __FUNCTION__
);
510 tcc_error("alignment of code section not multiple of 4");
513 // Generate forward branch to label:
514 ST_FUNC
int gjmp(int t
)
522 // Generate branch to known address:
523 ST_FUNC
void gjmp_addr(int a
)
525 uint32_t r
= a
- ind
, imm
;
526 if ((r
+ (1 << 21)) & ~((1U << 22) - 2))
527 tcc_error("out-of-range jump");
528 imm
= (((r
>> 12) & 0xff) << 12)
529 | (((r
>> 11) & 1) << 20)
530 | (((r
>> 1) & 0x3ff) << 21)
531 | (((r
>> 20) & 1) << 31);
532 o(0x6f | imm
); // jal x0, imm == j imm
535 ST_FUNC
int gjmp_cond(int op
, int t
)
538 assert(op
== TOK_EQ
|| op
== TOK_NE
);
539 assert(vtop
->cmp_r
>= 10 && vtop
->cmp_r
< 18);
540 o(0x63 | (!inv
<< 12) | (vtop
->cmp_r
<< 15) | (8 << 7)); // bne/beq x0,r,+4
544 ST_FUNC
int gjmp_append(int n
, int t
)
547 /* insert jump list n into t */
550 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
558 static void gen_opil(int op
, int ll
)
562 int func3
= 0, func7
= 0;
563 /* XXX We could special-case some constant args. */
565 a
= ireg(vtop
[-1].r
);
580 tcc_error("implement me: %s(%s)", __FUNCTION__
, get_tok_str(op
, NULL
));
583 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20)); // add d, a, b
586 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); //sub d, a, b
589 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (1 << 12)); //sll d, a, b
592 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25)); //mul d, a, b
595 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x01 << 25) | (4 << 12)); //div d, a, b
598 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (7 << 12)); // and d, a, b
601 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (4 << 12)); // xor d, a, b
604 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (6 << 12)); // or d, a, b
615 if (op
& 1) { // remove [U]GE,GT
619 if ((op
& 7) == 6) { // [U]LE
620 int t
= a
; a
= b
; b
= t
;
623 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (((op
> TOK_UGT
) ? 2 : 3) << 12)); // slt[u] d, a, b
625 EI(0x13, 4, d
, d
, 1); // xori d, d, 1
631 o(0x33 | (d
<< 7) | (a
<< 15) | (b
<< 20) | (0x20 << 25)); // sub d, a, b
633 o(0x33 | (3 << 12) | (d
<< 7) | (0 << 15) | (d
<< 20)); // sltu d, x0, d == snez d,d
635 EI(0x13, 3, d
, d
, 1); // sltiu d, d, 1 == seqz d,d
642 ST_FUNC
void gen_opi(int op
)
647 ST_FUNC
void gen_opl(int op
)
652 ST_FUNC
void gen_opf(int op
)
654 int rs1
, rs2
, rd
, dbl
, invert
;
655 gv2(RC_FLOAT
, RC_FLOAT
);
656 assert(vtop
->type
.t
== VT_DOUBLE
|| vtop
->type
.t
== VT_FLOAT
);
657 dbl
= vtop
->type
.t
== VT_DOUBLE
;
658 rs1
= freg(vtop
[-1].r
);
668 rd
= get_reg(RC_FLOAT
);
671 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (7 << 12) | (dbl
<< 25) | (op
<< 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)
685 rd
= get_reg(RC_INT
);
688 o(0x53 | (rd
<< 7) | (rs1
<< 15) | (rs2
<< 20) | (op
<< 12) | (dbl
<< 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
690 EI(0x13, 4, rd
, rd
, 1); // xori RD, 1
704 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
708 rd
= rs1
, rs1
= rs2
, rs2
= rd
;
713 ST_FUNC
void gen_cvt_sxtw(void)
715 /* XXX on risc-v the registers are usually sign-extended already.
716 Let's try to not do anything here. */
719 ST_FUNC
void gen_cvt_itof(int t
)
721 tcc_error("implement me: %s", __FUNCTION__
);
724 ST_FUNC
void gen_cvt_ftoi(int t
)
726 tcc_error("implement me: %s", __FUNCTION__
);
729 ST_FUNC
void gen_cvt_ftof(int dt
)
731 int st
= vtop
->type
.t
& VT_BTYPE
, rs
, rd
;
733 assert (dt
== VT_FLOAT
|| dt
== VT_DOUBLE
);
734 assert (st
== VT_FLOAT
|| st
== VT_DOUBLE
);
738 rd
= get_reg(RC_FLOAT
);
740 EI(0x53, 7, freg(rd
), freg(rs
), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
742 EI(0x53, 7, freg(rd
), freg(rs
), (0x20 << 5) | 1); // fcvt.s.d RD, RS
746 ST_FUNC
void ggoto(void)
748 tcc_error("implement me: %s", __FUNCTION__
);
751 ST_FUNC
void gen_vla_sp_save(int addr
)
753 tcc_error("implement me: %s", __FUNCTION__
);
756 ST_FUNC
void gen_vla_sp_restore(int addr
)
758 tcc_error("implement me: %s", __FUNCTION__
);
761 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
)
763 tcc_error("implement me: %s", __FUNCTION__
);