sdelfloader/loader/source/processor.h

   1 // this file was taken from libogc, see http://www.devkitpro.org/
   2
   3 #ifndef __PROCESSOR_H__
   4 #define __PROCESSOR_H__
   5
   6 #include <gctypes.h>
   7
   8 #define __stringify(rn)                                 #rn
   9 #define ATTRIBUTE_ALIGN(v)                              __attribute__((aligned(v)))
  10
  11 #define _sync() asm volatile("sync")
  12 #define _nop() asm volatile("nop")
  13 #define ppcsync() asm volatile("sc")
  14 #define ppchalt() ({                                    \
  15         asm volatile("sync");                           \
  16         while(1) {                                                      \
  17                 asm volatile("nop");                    \
  18                 asm volatile("li 3,0");                 \
  19                 asm volatile("nop");                    \
  20         }                                                                       \
  21 })
  22
  23 #define mfdcr(_rn) ({register u32 _rval; \
  24                 asm volatile("mfdcr %0," __stringify(_rn) \
  25              : "=r" (_rval)); _rval;})
  26 #define mtdcr(rn, val)  asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
  27
  28 #define mfmsr()   ({register u32 _rval; \
  29                 asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})
  30 #define mtmsr(val)  asm volatile("mtmsr %0" : : "r" (val))
  31
  32 #define mfdec()   ({register u32 _rval; \
  33                 asm volatile("mfdec %0" : "=r" (_rval)); _rval;})
  34 #define mtdec(_val)  asm volatile("mtdec %0" : : "r" (_val))
  35
  36 #define mfspr(_rn) \
  37 ({      register u32 _rval = 0; \
  38         asm volatile("mfspr %0," __stringify(_rn) \
  39         : "=r" (_rval));\
  40         _rval; \
  41 })
  42
  43 #define mtspr(_rn, _val) asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
  44
  45 #define mfwpar()                mfspr(WPAR)
  46 #define mtwpar(_val)    mtspr(WPAR,_val)
  47
  48 #define mfmmcr0()               mfspr(MMCR0)
  49 #define mtmmcr0(_val)   mtspr(MMCR0,_val)
  50 #define mfmmcr1()               mfspr(MMCR1)
  51 #define mtmmcr1(_val)   mtspr(MMCR1,_val)
  52
  53 #define mfpmc1()                mfspr(PMC1)
  54 #define mtpmc1(_val)    mtspr(PMC1,_val)
  55 #define mfpmc2()                mfspr(PMC2)
  56 #define mtpmc2(_val)    mtspr(PMC2,_val)
  57 #define mfpmc3()                mfspr(PMC3)
  58 #define mtpmc3(_val)    mtspr(PMC3,_val)
  59 #define mfpmc4()                mfspr(PMC4)
  60 #define mtpmc4(_val)    mtspr(PMC4,_val)
  61
  62 #define mfhid0()                mfspr(HID0)
  63 #define mthid0(_val)    mtspr(HID0,_val)
  64 #define mfhid1()                mfspr(HID1)
  65 #define mthid1(_val)    mtspr(HID1,_val)
  66 #define mfhid2()                mfspr(HID2)
  67 #define mthid2(_val)    mtspr(HID2,_val)
  68 #define mfhid4()                mfspr(HID4)
  69 #define mthid4(_val)    mtspr(HID4,_val)
  70
  71 #define cntlzw(_val) ({register u32 _rval; \
  72                                           asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})
  73
  74 #define _CPU_MSR_GET( _msr_value ) \
  75   do { \
  76     _msr_value = 0; \
  77     asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
  78   } while (0)
  79
  80 #define _CPU_MSR_SET( _msr_value ) \
  81 { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
  82
  83 #define _CPU_ISR_Enable() \
  84         { register u32 _val = 0; \
  85           asm volatile ("mfmsr %0; ori %0,%0,0x8000; mtmsr %0" : \
  86                                         "=&r" (_val) : "0" (_val));\
  87         }
  88
  89 #define _CPU_ISR_Disable( _isr_cookie ) \
  90   { register u32 _disable_mask = MSR_EE; \
  91     _isr_cookie = 0; \
  92     asm volatile ( \
  93         "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
  94         "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
  95         "0" ((_isr_cookie)), "1" ((_disable_mask)) \
  96         ); \
  97   }
  98
  99 #define _CPU_ISR_Restore( _isr_cookie )  \
 100   { \
 101      asm volatile ( "mtmsr %0" : \
 102                    "=r" ((_isr_cookie)) : \
 103                    "0" ((_isr_cookie))); \
 104   }
 105
 106 #define _CPU_ISR_Flash( _isr_cookie ) \
 107   { register u32 _disable_mask = MSR_EE; \
 108     asm volatile ( \
 109       "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
 110       "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
 111       "0" ((_isr_cookie)), "1" ((_disable_mask)) \
 112     ); \
 113   }
 114
 115 #endif