1 Test netlist for Eldo & Spice mode
3 !---------------------------------------------------------------
4 !-- Project : (X)emacs eldo & spice mode
5 !-- Circuit name : test_netlist.cir
6 !---------------------------------------------------------------
7 !-- Designer(s) : E. ROUAT <emmanuel.rouat@.wanadoo.fr>
8 ! : G. VAN DER PLAS <geert_vanderplas@email.com>
10 !-- Purpose : Test for eldo and spice mode
15 !---------------------------------------------------------------
16 mn2 1 2 3 4 pmos l=10u w=1u
17 mn1 1 2 3 4 nmos w='10u*wscale' l=1u $x=10u $l=1u $ test this doc $y=1u ?
19 + param: test=10f $ test for eldo
20 *+ couple=5 $ couple only for layla/mondriaan
22 ! Note the difference between 'comments' and 'doc strings' :
24 * This is a 'commented out' line
25 ! and this is a 'doc' string
26 $ and this is also a 'doc' string
27 * and a combination !of $both $ tested
28 * and a combination !of both tested
29 * and a 'combination' $of both tested
31 ! You can comment out portions of text using #c/#e:
34 .model MY_NMOS NMOS LEVEL=3
35 + VTO=1V UO=550 VMAX=2.0e5
36 + CGDO=0.4p CGBO=2.0e-10
38 .model MY_PMOS NMOS LEVEL=3
39 + VTO=-1V UO=230 VMAX=1.9e5
40 + CGDO=0.4p CGBO=2.0e-10
43 ! By using 'C-c C-c' you can 'toggle' between commented out portions
44 ! of test - select the region that follows, type 'C-c C-c' (or use
45 ! the '(Un)comment-region menu)' and see what happens:
56 !--------------------------------------------------------------------
58 !--------------------------------------------------------------------
60 ! 'models.lib' should highlight when the moude pointer passes over it.
61 ! This means you can load this file using the middle moude button (if
65 .lib key=typical models.lib
68 ! Lets define some MOSFET models - these should appear in
69 ! the 'Models' entry in the menu.
71 .model MY_NMOS NMOS LEVEL=3
72 + VTO=1V UO=550 VMAX=2.0e5
73 + CGDO=0.4p CGBO=2.0e-10
75 .model MY_PMOS NMOS LEVEL=3
76 + VTO=-1V UO=230 VMAX=1.9e5
77 + CGDO=0.4p CGBO=2.0e-10
79 ! The following has a wrong syntax - note the fontification
81 .model 1WRONG_SYNTAX NMOS
85 !--------------------------------------------------------------------
87 !--------------------------------------------------------------------
89 ! Lets define a subckt - a parametrised inverter
91 .SUBCKT FOO IN OUT VDD VSS param: W=5u L=0.5U
92 MP OUT IN VDD VDD MY_PMOS W={3*W} L={L}
93 MN OUT IN VSS! VSS! MY_NMOS W={W} L={L}
97 ! In the following instanciations, FOO should be highlighted
100 X2 1 2 3 4 FOO param: W=10u L=1u
101 X3 1 2 3 4 FOO ! comment
103 ! Even in multi-line instanciations:
105 + FOO param: W=10u L=1u
107 + 3 4 FOO param: W=10u L=1u
110 ! This one doesn't work - probably never will, in spice-mode it works
113 + FOO param: W=10u L=1u
116 ! FOO#1 is a valid name, but 1AOO1 isn't:
123 MN1 N1N28 N1N105 VSS VSS n W=1.056u L=0.185u
124 + AD=0.209P AS=0.122P PD=0.755U PS=0.280U
125 + NRD=0.297 NRS=0.160
126 MM1I47N3 N1I471N25 N1N28 N1N37 VSS n W=0.440U L=0.180U
127 + AD=0.062P AS=0.209P PD=0.280U PS=0.755U
128 + NRD=0.315 NRS=0.370
129 MM1I47N1 N1I471N6 N1N31 N1I471N25 VSS n W=0.440U L=0.180U
130 + AD=0.062P AS=0.062P PD=0.280U PS=0.280U
131 + NRD=0.315 NRS=0.315
132 MM1I47N2 VSS RB N1I471N6 VSS n W=0.440U L=0.180U
133 + AD=0.405P AS=0.062P PD=2.280U PS=0.280U
134 + NRD=0.918 NRS=0.315
135 MM1I120N VSS N1N37 N1N31 VSS n W=1.090U L=0.187U
136 + AD=0.377P AS=0.421P PD=0.960U PS=1.850U
137 + NRD=0.820 NRS=0.274
138 MM1I139N3 N1I1391N26 N1N31 VSS VSS n W=1.199U L=0.187U
139 + AD=0.194P AS=0.377P PD=0.375U PS=0.960U
140 + NRD=0.142 NRS=0.764
141 MM1I139N1 N1I1391N44 RB N1I1391N26 VSS n W=1.120U L=0.180U
142 + AD=0.157P AS=0.194P PD=0.280U PS=0.375U
143 + NRD=0.125 NRS=0.142
145 !--------------------------------------------------------------------
147 !--------------------------------------------------------------------
151 .options STAT=1 SIMUDIV=10 !Status reports
152 .options noascii nomod engnot
153 .options nowarn=240 nowarn=902 nowarn=123
154 .options eps=1e-7 itol=1e-6 gmin=1e-16 analog
155 .options nobound_phase paramfly inclib
159 ! Now some inputs and supplies
164 VIN IN 0 Pulse(0 5 1us 0.1ns 0.1ns 10ns 20ns)
166 ! Simulation cards - fontified in 'eldo-analysis-face' or 'spice-analysis-face'
171 ! What will we look at? All 'output' cards are fontified
172 ! in font-lock-preprocessor-face:
174 .plot tran V(IN) V(OUT)
175 .plot tra V(OUT) ! Note wrong syntax
178 .extract tran AVERAGE(I(VDD))
184 !--------------------------------------------------------------------
186 !--------------------------------------------------------------------
188 ** Thu Apr 11 2002 Geert Van der Plas <geert_vanderplas@email.com>
190 ** - added spice mode remarks
192 * Thu Apr 5 2001 E. ROUAT (DAIS) <emmanuel.rouat@st.com>