src/runtime/sparc-arch.c

   1 /*
   2  * This software is part of the SBCL system. See the README file for
   3  * more information.
   4  *
   5  * This software is derived from the CMU CL system, which was
   6  * written at Carnegie Mellon University and released into the
   7  * public domain. The software is in the public domain and is
   8  * provided with absolutely no warranty. See the COPYING and CREDITS
   9  * files for more information.
  10  */
  11 #include <stdio.h>
  12
  13 #include "sbcl.h"
  14 #include "runtime.h"
  15 #include "arch.h"
  16 #include "globals.h"
  17 #include "validate.h"
  18 #include "os.h"
  19 #include "lispregs.h"
  20 #include "signal.h"
  21 #include "alloc.h"
  22 #include "interrupt.h"
  23 #include "interr.h"
  24 #include "breakpoint.h"
  25 #include "monitor.h"
  26
  27 #ifdef LISP_FEATURE_LINUX
  28 extern int linux_sparc_siginfo_bug;
  29 #endif
  30
  31 void arch_init(void)
  32 {
  33     return;
  34 }
  35
  36 os_vm_address_t arch_get_bad_addr(int sig, siginfo_t *code, os_context_t *context)
  37 {
  38     unsigned int badinst;
  39     unsigned int *pc;
  40     int rs1;
  41
  42     pc = (unsigned int *)(*os_context_pc_addr(context));
  43
  44     /* On the sparc, we have to decode the instruction. */
  45
  46     /* Make sure it's not the pc thats bogus, and that it was lisp code */
  47     /* that caused the fault. */
  48     if ((unsigned long) pc & 3) {
  49       /* Unaligned */
  50       return NULL;
  51     }
  52     if ((pc < READ_ONLY_SPACE_START ||
  53          pc >= READ_ONLY_SPACE_START+READ_ONLY_SPACE_SIZE) &&
  54         (pc < current_dynamic_space ||
  55          pc >= current_dynamic_space + dynamic_space_size)) {
  56       return NULL;
  57     }
  58
  59     badinst = *pc;
  60
  61     if ((badinst >> 30) != 3)
  62         /* All load/store instructions have op = 11 (binary) */
  63         return 0;
  64
  65     rs1 = (badinst>>14)&0x1f;
  66
  67     if (badinst & (1<<13)) {
  68         /* r[rs1] + simm(13) */
  69         int simm13 = badinst & 0x1fff;
  70
  71         if (simm13 & (1<<12))
  72             simm13 |= -1<<13;
  73
  74         return (os_vm_address_t)
  75             (*os_context_register_addr(context, rs1)+simm13);
  76     }
  77     else {
  78         /* r[rs1] + r[rs2] */
  79         int rs2 = badinst & 0x1f;
  80
  81         return (os_vm_address_t)
  82             (*os_context_register_addr(context, rs1) +
  83              *os_context_register_addr(context, rs2));
  84     }
  85 }
  86
  87 void arch_skip_instruction(os_context_t *context)
  88 {
  89     *os_context_pc_addr(context) = *os_context_npc_addr(context);
  90     /* Note that we're doing integer arithmetic here, not pointer. So
  91      * the value that the return value of os_context_npc_addr() points
  92      * to will be incremented by 4, not 16.
  93      */
  94     *os_context_npc_addr(context) += 4;
  95 }
  96
  97 unsigned char *arch_internal_error_arguments(os_context_t *context)
  98 {
  99     return (unsigned char *)(*os_context_pc_addr(context) + 4);
 100 }
 101
 102 boolean arch_pseudo_atomic_atomic(os_context_t *context)
 103 {
 104     /* FIXME: this foreign_function_call_active test is dubious at
 105      * best. If a foreign call is made in a pseudo atomic section
 106      * (?) or more likely a pseudo atomic section is in a foreign
 107      * call then an interrupt is executed immediately. Maybe it
 108      * has to do with C code not maintaining pseudo atomic
 109      * properly. MG - 2005-08-10
 110      *
 111      * The foreign_function_call_active used to live at each call-site
 112      * to arch_pseudo_atomic_atomic, but this seems clearer.
 113      * --NS 2007-05-15 */
 114     return (!foreign_function_call_active)
 115         && ((*os_context_register_addr(context,reg_ALLOC)) & 4);
 116 }
 117
 118 void arch_set_pseudo_atomic_interrupted(os_context_t *context)
 119 {
 120     *os_context_register_addr(context,reg_ALLOC) |=  1;
 121 }
 122
 123 void arch_clear_pseudo_atomic_interrupted(os_context_t *context)
 124 {
 125     *os_context_register_addr(context,reg_ALLOC) &= ~1;
 126 }
 127
 128 unsigned int arch_install_breakpoint(void *pc)
 129 {
 130     unsigned int *ptr = (unsigned int *)pc;
 131     unsigned int result = *ptr;
 132     *ptr = trap_Breakpoint;
 133
 134     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 135
 136     return result;
 137 }
 138
 139 void arch_remove_breakpoint(void *pc, unsigned int orig_inst)
 140 {
 141     *(unsigned int *)pc = orig_inst;
 142     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 143 }
 144
 145 /*
 146  * Perform the instruction that we overwrote with a breakpoint.  As we
 147  * don't have a single-step facility, this means we have to:
 148  * - put the instruction back
 149  * - put a second breakpoint at the following instruction,
 150  *   set after_breakpoint and continue execution.
 151  *
 152  * When the second breakpoint is hit (very shortly thereafter, we hope)
 153  * sigtrap_handler gets called again, but follows the AfterBreakpoint
 154  * arm, which
 155  * - puts a bpt back in the first breakpoint place (running across a
 156  *   breakpoint shouldn't cause it to be uninstalled)
 157  * - replaces the second bpt with the instruction it was meant to be
 158  * - carries on
 159  *
 160  * Clear?
 161  */
 162 static unsigned int *skipped_break_addr, displaced_after_inst;
 163 static sigset_t orig_sigmask;
 164
 165 void arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst)
 166 {
 167     unsigned int *pc = (unsigned int *)(*os_context_pc_addr(context));
 168     unsigned int *npc = (unsigned int *)(*os_context_npc_addr(context));
 169
 170   /*  orig_sigmask = context->sigmask;
 171       sigemptyset(&context->sigmask); */
 172   /* FIXME!!! */
 173   /* FILLBLOCKSET(&context->uc_sigmask);*/
 174
 175     *pc = orig_inst;
 176     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 177     skipped_break_addr = pc;
 178     displaced_after_inst = *npc;
 179     *npc = trap_AfterBreakpoint;
 180     os_flush_icache((os_vm_address_t) npc, sizeof(unsigned int));
 181
 182 }
 183
 184 static int pseudo_atomic_trap_p(os_context_t *context)
 185 {
 186     unsigned int* pc;
 187     unsigned int badinst;
 188     int result;
 189
 190
 191     pc = (unsigned int*) *os_context_pc_addr(context);
 192     badinst = *pc;
 193     result = 0;
 194
 195     /* Check to see if the current instruction is a pseudo-atomic-trap */
 196     if (((badinst >> 30) == 2) && (((badinst >> 19) & 0x3f) == 0x3a)
 197         && (((badinst >> 13) & 1) == 1) && ((badinst & 0x7f) == PSEUDO_ATOMIC_TRAP))
 198         {
 199             unsigned int previnst;
 200             previnst = pc[-1];
 201             /*
 202              * Check to see if the previous instruction was an andcc alloc-tn,
 203              * 3, zero-tn instruction.
 204              */
 205             if (((previnst >> 30) == 2) && (((previnst >> 19) & 0x3f) == 0x11)
 206                 && (((previnst >> 14) & 0x1f) == reg_ALLOC)
 207                 && (((previnst >> 25) & 0x1f) == reg_ZERO)
 208                 && (((previnst >> 13) & 1) == 1)
 209                 && ((previnst & 0x1fff) == 3))
 210                 {
 211                     result = 1;
 212                 }
 213             else
 214                 {
 215                     fprintf(stderr, "Oops!  Got a PSEUDO-ATOMIC-TRAP without a preceeding andcc!\n");
 216                 }
 217         }
 218     return result;
 219 }
 220
 221 void
 222 arch_handle_breakpoint(os_context_t *context)
 223 {
 224     handle_breakpoint(context);
 225 }
 226
 227 void
 228 arch_handle_fun_end_breakpoint(os_context_t *context)
 229 {
 230     *os_context_pc_addr(context) = (int) handle_fun_end_breakpoint(context);
 231     *os_context_npc_addr(context) = *os_context_pc_addr(context) + 4;
 232 }
 233
 234 void
 235 arch_handle_after_breakpoint(os_context_t *context)
 236 {
 237     *skipped_break_addr = trap_Breakpoint;
 238     os_flush_icache(skipped_break_addr, sizeof(unsigned int));
 239     skipped_break_addr = NULL;
 240     *(unsigned long *) os_context_pc_addr(context) = displaced_after_inst;
 241     /* context->sigmask = orig_sigmask; */
 242     os_flush_icache((os_vm_address_t) os_context_pc_addr(context), sizeof(unsigned int));
 243 }
 244
 245 void
 246 arch_handle_single_step_trap(os_context_t *context, int trap)
 247 {
 248     unsigned int code = *((u32 *)(*os_context_pc_addr(context)));
 249     int register_offset = code >> 5 & 0x1f;
 250     handle_single_step_trap(context, trap, register_offset);
 251     arch_skip_instruction(context);
 252 }
 253
 254 static void sigill_handler(int signal, siginfo_t *siginfo, void *void_context)
 255 {
 256     os_context_t *context = arch_os_get_context(&void_context);
 257 #ifdef LISP_FEATURE_LINUX
 258     /* FIXME: Check that this is necessary -- CSR, 2002-07-15 */
 259     os_restore_fp_control(context);
 260 #endif
 261
 262     if ((siginfo->si_code) == ILL_ILLOPC
 263 #ifdef LISP_FEATURE_LINUX
 264         || (linux_sparc_siginfo_bug && (siginfo->si_code == 2))
 265 #endif
 266         ) {
 267         int trap;
 268         unsigned int inst;
 269         unsigned int* pc = (unsigned int*) siginfo->si_addr;
 270
 271         inst = *pc;
 272         trap = inst & 0x1f;
 273         handle_trap(context,trap);
 274     }
 275     else if ((siginfo->si_code) == ILL_ILLTRP
 276 #ifdef LISP_FEATURE_LINUX
 277              || (linux_sparc_siginfo_bug && (siginfo->si_code) == 192)
 278 #endif
 279              ) {
 280         if (pseudo_atomic_trap_p(context)) {
 281             /* A trap instruction from a pseudo-atomic.  We just need
 282                to fixup up alloc-tn to remove the interrupted flag,
 283                skip over the trap instruction, and then handle the
 284                pending interrupt(s). */
 285             arch_clear_pseudo_atomic_interrupted(context);
 286             arch_skip_instruction(context);
 287             interrupt_handle_pending(context);
 288         }
 289         else {
 290             interrupt_internal_error(context, 0);
 291         }
 292     }
 293     else {
 294         interrupt_handle_now(signal, siginfo, context);
 295     }
 296 }
 297
 298 static void sigemt_handler(int signal, siginfo_t *siginfo, void *void_context)
 299 {
 300     unsigned int badinst;
 301     boolean subtract, immed;
 302     int rd, rs1, op1, rs2, op2, result;
 303     os_context_t *context = arch_os_get_context(&void_context);
 304 #ifdef LISP_FEATURE_LINUX
 305     os_restore_fp_control(context);
 306 #endif
 307
 308     badinst = *(unsigned int *)os_context_pc_addr(context);
 309     if ((badinst >> 30) != 2 || ((badinst >> 20) & 0x1f) != 0x11) {
 310         /* It wasn't a tagged add.  Pass the signal into lisp. */
 311         interrupt_handle_now(signal, siginfo, context);
 312         return;
 313     }
 314
 315     fprintf(stderr, "SIGEMT trap handler with tagged op instruction!\n");
 316
 317     /* Extract the parts of the inst. */
 318     subtract = badinst & (1<<19);
 319     rs1 = (badinst>>14) & 0x1f;
 320     op1 = *os_context_register_addr(context, rs1);
 321
 322     /* If the first arg is $ALLOC then it is really a signal-pending note */
 323     /* for the pseudo-atomic noise. */
 324     if (rs1 == reg_ALLOC) {
 325         /* Perform the op anyway. */
 326         op2 = badinst & 0x1fff;
 327         if (op2 & (1<<12))
 328             op2 |= -1<<13;
 329         if (subtract)
 330             result = op1 - op2;
 331         else
 332             result = op1 + op2;
 333         /* KLUDGE: this & ~7 is a little bit magical but basically
 334            clears pseudo_atomic bits if any */
 335         *os_context_register_addr(context, reg_ALLOC) = result & ~7;
 336         arch_skip_instruction(context);
 337         interrupt_handle_pending(context);
 338         return;
 339     }
 340
 341     if ((op1 & 3) != 0) {
 342         /* The first arg wan't a fixnum. */
 343         interrupt_internal_error(context, 0);
 344         return;
 345     }
 346
 347     if (immed = badinst & (1<<13)) {
 348         op2 = badinst & 0x1fff;
 349         if (op2 & (1<<12))
 350             op2 |= -1<<13;
 351     }
 352     else {
 353         rs2 = badinst & 0x1f;
 354         op2 = *os_context_register_addr(context, rs2);
 355     }
 356
 357     if ((op2 & 3) != 0) {
 358         /* The second arg wan't a fixnum. */
 359         interrupt_internal_error(context, 0);
 360         return;
 361     }
 362
 363     rd = (badinst>>25) & 0x1f;
 364     if (rd != 0) {
 365         /* Don't bother computing the result unless we are going to use it. */
 366         if (subtract)
 367             result = (op1>>2) - (op2>>2);
 368         else
 369             result = (op1>>2) + (op2>>2);
 370
 371         dynamic_space_free_pointer =
 372             (lispobj *) *os_context_register_addr(context, reg_ALLOC);
 373
 374         *os_context_register_addr(context, rd) = alloc_number(result);
 375
 376         *os_context_register_addr(context, reg_ALLOC) =
 377             (unsigned long) dynamic_space_free_pointer;
 378     }
 379
 380     arch_skip_instruction(context);
 381 }
 382
 383 void arch_install_interrupt_handlers()
 384 {
 385     undoably_install_low_level_interrupt_handler(SIGILL , sigill_handler);
 386     undoably_install_low_level_interrupt_handler(SIGEMT, sigemt_handler);
 387 }
 388
 389 \f
 390 #ifdef LISP_FEATURE_LINKAGE_TABLE
 391
 392 /* This a naive port from CMUCL/sparc, which was mostly stolen from the
 393  * CMUCL/x86 version, with adjustments for sparc
 394  *
 395  * Linkage entry size is 16, because we need at least 3 instruction to
 396  * implement a jump:
 397  *
 398  *      sethi %hi(addr), %g4
 399  *      jmpl  [%g4 + %lo(addr)], %g5
 400  *      nop
 401  *
 402  * The Sparc V9 ABI seems to use 8 words for its jump tables.  Maybe
 403  * we should do the same?
 404  */
 405
 406 /*
 407  * Define the registers to use in the linkage jump table. Can be the
 408  * same. Some care must be exercised when choosing these. It has to be
 409  * a register that is not otherwise being used. reg_L0 is a good
 410  * choice. call_into_c trashes reg_L0 without preserving it, so we can
 411  * trash it in the linkage jump table.
 412  */
 413 #define LINKAGE_TEMP_REG        reg_L0
 414 #define LINKAGE_ADDR_REG        reg_L0
 415
 416 /*
 417  * Insert the necessary jump instructions at the given address.
 418  */
 419 void
 420 arch_write_linkage_table_jmp(void* reloc_addr, void *target_addr)
 421 {
 422   /*
 423    * Make JMP to function entry.
 424    *
 425    * The instruction sequence is:
 426    *
 427    *        sethi %hi(addr), temp_reg
 428    *        jmp   %temp_reg + %lo(addr), %addr_reg
 429    *        nop
 430    *        nop
 431    *
 432    */
 433   int* inst_ptr;
 434   unsigned long hi;                   /* Top 22 bits of address */
 435   unsigned long lo;                   /* Low 10 bits of address */
 436   unsigned int inst;
 437
 438   inst_ptr = (int*) reloc_addr;
 439
 440   /*
 441    * Split the target address into hi and lo parts for the sethi
 442    * instruction.  hi is the top 22 bits.  lo is the low 10 bits.
 443    */
 444   hi = (unsigned long) target_addr;
 445   lo = hi & 0x3ff;
 446   hi >>= 10;
 447
 448   /*
 449    * sethi %hi(addr), temp_reg
 450    */
 451
 452   inst = (0 << 30) | (LINKAGE_TEMP_REG << 25) | (4 << 22) | hi;
 453   *inst_ptr++ = inst;
 454
 455   /*
 456    * jmpl [temp_reg + %lo(addr)], addr_reg
 457    */
 458
 459   inst = (2U << 30) | (LINKAGE_ADDR_REG << 25) | (0x38 << 19)
 460     | (LINKAGE_TEMP_REG << 14) | (1 << 13) | lo;
 461   *inst_ptr++ = inst;
 462
 463   /* nop (really sethi 0, %g0) */
 464
 465   inst = (0 << 30) | (0 << 25) | (4 << 22) | 0;
 466
 467   *inst_ptr++ = inst;
 468   *inst_ptr++ = inst;
 469
 470   os_flush_icache((os_vm_address_t) reloc_addr, (char*) inst_ptr - (char*) reloc_addr);
 471 }
 472
 473 void
 474 arch_write_linkage_table_ref(void * reloc_addr, void *target_addr)
 475 {
 476     *(unsigned long *)reloc_addr = (unsigned long)target_addr;
 477 }
 478
 479 #endif