src/runtime/ppc-arch.c

   1 /*
   2  * This software is part of the SBCL system. See the README file for
   3  * more information.
   4  *
   5  * This software is derived from the CMU CL system, which was
   6  * written at Carnegie Mellon University and released into the
   7  * public domain. The software is in the public domain and is
   8  * provided with absolutely no warranty. See the COPYING and CREDITS
   9  * files for more information.
  10  */
  11
  12 #include <stdio.h>
  13
  14 #include "sbcl.h"
  15 #include "arch.h"
  16 #include "globals.h"
  17 #include "validate.h"
  18 #include "os.h"
  19 #include "interrupt.h"
  20 #include "lispregs.h"
  21 #include "signal.h"
  22 #include "interrupt.h"
  23 #include "interr.h"
  24 #include "breakpoint.h"
  25 #include "alloc.h"
  26
  27 #if defined(LISP_FEATURE_GENCGC)
  28 #include "gencgc-alloc-region.h"
  29 #endif
  30
  31 #ifdef LISP_FEATURE_SB_THREAD
  32 #include "pseudo-atomic.h"
  33 #endif
  34
  35   /* The header files may not define PT_DAR/PT_DSISR.  This definition
  36      is correct for all versions of ppc linux >= 2.0.30
  37
  38      As of DR2.1u4, MkLinux doesn't pass these registers to signal
  39      handlers correctly; a patch is necessary in order to (partially)
  40      correct this.
  41
  42      Even with the patch, the DSISR may not have its 'write' bit set
  43      correctly (it tends not to be set if the fault was caused by
  44      something other than a protection violation.)
  45
  46      Caveat callers.  */
  47
  48 #if defined (LISP_FEATURE_DARWIN) || defined(LISP_FEATURE_LINUX)
  49 #ifndef PT_DAR
  50 #define PT_DAR          41
  51 #endif
  52
  53 #ifndef PT_DSISR
  54 #define PT_DSISR        42
  55 #endif
  56 #endif
  57
  58 /* Magic encoding for the instruction used for traps. */
  59 #define TRAP_INSTRUCTION(trap) ((3<<26) | (6 << 21) | (trap))
  60
  61 void arch_init() {
  62 }
  63
  64 os_vm_address_t
  65 arch_get_bad_addr(int sig, siginfo_t *code, os_context_t *context)
  66 {
  67     os_vm_address_t addr;
  68
  69 #if defined(LISP_FEATURE_NETBSD) || defined(LISP_FEATURE_OPENBSD)
  70     addr = (os_vm_address_t) (code->si_addr);
  71 #else
  72     addr = (os_vm_address_t) (*os_context_register_addr(context,PT_DAR));
  73 #endif
  74     return addr;
  75 }
  76
  77
  78 void
  79 arch_skip_instruction(os_context_t *context)
  80 {
  81     char** pcptr;
  82     pcptr = (char**) os_context_pc_addr(context);
  83     *pcptr += 4;
  84 }
  85
  86 unsigned char *
  87 arch_internal_error_arguments(os_context_t *context)
  88 {
  89     return (unsigned char *)(*os_context_pc_addr(context)+4);
  90 }
  91
  92
  93 boolean
  94 arch_pseudo_atomic_atomic(os_context_t *context)
  95 {
  96 #ifdef LISP_FEATURE_SB_THREAD
  97     struct thread *thread = arch_os_get_current_thread();
  98
  99     if (foreign_function_call_active_p(thread)) {
 100         return get_pseudo_atomic_atomic(thread);
 101     } else return
 102 #else
 103     /* FIXME: this foreign_function_call_active test is dubious at
 104      * best. If a foreign call is made in a pseudo atomic section
 105      * (?) or more likely a pseudo atomic section is in a foreign
 106      * call then an interrupt is executed immediately. Maybe it
 107      * has to do with C code not maintaining pseudo atomic
 108      * properly. MG - 2005-08-10
 109      *
 110      * The foreign_function_call_active used to live at each call-site
 111      * to arch_pseudo_atomic_atomic, but this seems clearer.
 112      * --NS 2007-05-15 */
 113     return (!foreign_function_call_active_p(arch_os_get_current_thread())) &&
 114 #endif
 115         ((*os_context_register_addr(context,reg_ALLOC)) & flag_PseudoAtomic);
 116 }
 117
 118 void
 119 arch_set_pseudo_atomic_interrupted(os_context_t *context)
 120 {
 121 #ifdef LISP_FEATURE_SB_THREAD
 122     struct thread *thread = arch_os_get_current_thread();
 123
 124     if (foreign_function_call_active_p(thread)) {
 125         set_pseudo_atomic_interrupted(thread);
 126     } else
 127 #endif
 128         *os_context_register_addr(context,reg_ALLOC)
 129             |= flag_PseudoAtomicInterrupted;
 130 }
 131
 132 void
 133 arch_clear_pseudo_atomic_interrupted(os_context_t *context)
 134 {
 135 #ifdef LISP_FEATURE_SB_THREAD
 136     struct thread *thread = arch_os_get_current_thread();
 137
 138     if (foreign_function_call_active_p(thread)) {
 139         clear_pseudo_atomic_interrupted(thread);
 140     } else
 141 #endif
 142         *os_context_register_addr(context,reg_ALLOC)
 143             &= ~flag_PseudoAtomicInterrupted;
 144 }
 145
 146 unsigned int
 147 arch_install_breakpoint(void *pc)
 148 {
 149     unsigned int *ptr = (unsigned int *)pc;
 150     unsigned int result = *ptr;
 151     *ptr = TRAP_INSTRUCTION(trap_Breakpoint);
 152     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 153     return result;
 154 }
 155
 156 void
 157 arch_remove_breakpoint(void *pc, unsigned int orig_inst)
 158 {
 159     *(unsigned int *)pc = orig_inst;
 160     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 161 }
 162
 163 /*
 164  * Perform the instruction that we overwrote with a breakpoint.  As we
 165  * don't have a single-step facility, this means we have to:
 166  * - put the instruction back
 167  * - put a second breakpoint at the following instruction,
 168  *   set after_breakpoint and continue execution.
 169  *
 170  * When the second breakpoint is hit (very shortly thereafter, we hope)
 171  * sigtrap_handler gets called again, but follows the AfterBreakpoint
 172  * arm, which
 173  * - puts a bpt back in the first breakpoint place (running across a
 174  *   breakpoint shouldn't cause it to be uninstalled)
 175  * - replaces the second bpt with the instruction it was meant to be
 176  * - carries on
 177  *
 178  * Clear?
 179  */
 180 static unsigned int *skipped_break_addr, displaced_after_inst;
 181 static sigset_t orig_sigmask;
 182
 183 static boolean
 184 should_branch(os_context_t *context, unsigned int orig_inst)
 185 {
 186     /* orig_inst is a conditional branch instruction.  We need to
 187      * know if the branch will be taken if executed in context. */
 188     int ctr = *os_context_ctr_addr(context);
 189     int cr = *os_context_cr_addr(context);
 190     int bo_field = (orig_inst >> 21) & 0x1f;
 191     int bi_field = (orig_inst >> 16) & 0x1f;
 192     int ctr_ok;
 193
 194     if (!(bo_field & 4)) ctr--; /* Decrement CTR if necessary. */
 195
 196     ctr_ok = (bo_field & 4) || ((ctr == 0) == ((bo_field & 2) == 2));
 197     return ctr_ok && ((bo_field & 0x10) ||
 198                       !(((cr >> (31-bi_field)) ^ (bo_field >> 3)) & 1));
 199 }
 200
 201 void
 202 arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst)
 203 {
 204     /* not sure how we ensure that we get the breakpoint reinstalled
 205      * after doing this -dan */
 206     unsigned int *pc = (unsigned int *)(*os_context_pc_addr(context));
 207     unsigned int *next_pc;
 208     int op = orig_inst >> 26;
 209     int sub_op = (orig_inst & 0x7fe) >> 1;  /* XL-form sub-opcode */
 210
 211     orig_sigmask = *os_context_sigmask_addr(context);
 212     sigaddset_blockable(os_context_sigmask_addr(context));
 213
 214     *pc = orig_inst;
 215     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 216     skipped_break_addr = pc;
 217
 218     /* Figure out where we will end up after running the displaced
 219      * instruction by defaulting to the next instruction in the stream
 220      * and then checking for branch instructions.  FIXME: This will
 221      * probably screw up if it attempts to step a trap instruction. */
 222     next_pc = pc + 1;
 223
 224     if (op == 18) {
 225         /* Branch  I-form */
 226         unsigned int displacement = orig_inst & 0x03fffffc;
 227         /* Sign extend */
 228         if (displacement & 0x02000000) {
 229             displacement |= 0xc0000000;
 230         }
 231         if (orig_inst & 2) { /* Absolute Address */
 232             next_pc = (unsigned int *)displacement;
 233         } else {
 234             next_pc = (unsigned int *)(((unsigned int)pc) + displacement);
 235         }
 236     } else if ((op == 16)
 237                && should_branch(context, orig_inst)) {
 238         /* Branch Conditional  B-form */
 239         unsigned int displacement = orig_inst & 0x0000fffc;
 240         /* Sign extend */
 241         if (displacement & 0x00008000) {
 242             displacement |= 0xffff0000;
 243         }
 244         if (orig_inst & 2) { /* Absolute Address */
 245             next_pc = (unsigned int *)displacement;
 246         } else {
 247             next_pc = (unsigned int *)(((unsigned int)pc) + displacement);
 248         }
 249     } else if ((op == 19) && (sub_op == 16)
 250                && should_branch(context, orig_inst)) {
 251         /* Branch Conditional to Link Register  XL-form */
 252         next_pc = (unsigned int *)
 253             ((*os_context_lr_addr(context)) & ~3);
 254     } else if ((op == 19) && (sub_op == 528)
 255                && should_branch(context, orig_inst)) {
 256         /* Branch Conditional to Count Register  XL-form */
 257         next_pc = (unsigned int *)
 258             ((*os_context_ctr_addr(context)) & ~3);
 259     }
 260
 261     /* Set the "after" breakpoint. */
 262     displaced_after_inst = *next_pc;
 263     *next_pc = TRAP_INSTRUCTION(trap_AfterBreakpoint);
 264     os_flush_icache((os_vm_address_t)next_pc, sizeof(unsigned int));
 265 }
 266
 267 #ifdef LISP_FEATURE_GENCGC
 268 /*
 269  * Return non-zero if the current instruction is an allocation trap
 270  */
 271 static int
 272 allocation_trap_p(os_context_t * context)
 273 {
 274     unsigned int *pc;
 275     unsigned inst;
 276     unsigned opcode;
 277     unsigned src;
 278     unsigned __attribute__((unused)) dst;
 279
 280     /*
 281      * First, the instruction has to be a TWLGE temp, NL3, which has the
 282      * format.
 283      * | 6| 5| 5 | 5 | 10|1|  width
 284      * |31|5 |dst|src|  4|0|  field
 285      */
 286     pc = (unsigned int *) (*os_context_pc_addr(context));
 287     inst = *pc;
 288
 289 #if 0
 290     fprintf(stderr, "allocation_trap_p at %p:  inst = 0x%08x\n", pc, inst);
 291 #endif
 292
 293     opcode = inst >> 26;
 294     src = (inst >> 11) & 0x1f;
 295     dst = (inst >> 16) & 0x1f;
 296     if ((opcode == 31) && (src == reg_NL3) && (5 == ((inst >> 21) & 0x1f))
 297         && (4 == ((inst >> 1) & 0x3ff))) {
 298         /*
 299          * We got the instruction.  Now, look back to make sure it was
 300          * proceeded by what we expected.  The previous instruction
 301          * should be an ADD or ADDI instruction.
 302          */
 303         unsigned int add_inst;
 304
 305         add_inst = pc[-1];
 306 #if 0
 307         fprintf(stderr, "   add inst at %p:  inst = 0x%08x\n",
 308                 pc - 1, add_inst);
 309 #endif
 310         opcode = add_inst >> 26;
 311         if ((opcode == 31) && (266 == ((add_inst >> 1) & 0x1ff))) {
 312             return 1;
 313         } else if ((opcode == 14)) {
 314             return 1;
 315         } else {
 316             fprintf(stderr,
 317                     "Whoa! Got allocation trap but could not find ADD or ADDI instruction: 0x%08x in the proper place\n",
 318                     add_inst);
 319         }
 320     }
 321     return 0;
 322 }
 323
 324 extern struct alloc_region boxed_region;
 325
 326 void
 327 handle_allocation_trap(os_context_t * context)
 328 {
 329     unsigned int *pc;
 330     unsigned int inst;
 331     unsigned int target;
 332     unsigned int __attribute__((unused)) target_ptr, end_addr;
 333     unsigned int opcode;
 334     int size;
 335     boolean were_in_lisp;
 336     char *memory;
 337
 338     target = 0;
 339     size = 0;
 340
 341 #if 0
 342     fprintf(stderr, "In handle_allocation_trap\n");
 343 #endif
 344
 345     /* I don't think it's possible for us NOT to be in lisp when we get
 346      * here.  Remove this later? */
 347     were_in_lisp = !foreign_function_call_active_p(arch_os_get_current_thread());
 348
 349     if (were_in_lisp) {
 350         fake_foreign_function_call(context);
 351     } else {
 352         fprintf(stderr, "**** Whoa! allocation trap and we weren't in lisp!\n");
 353     }
 354
 355     /*
 356      * Look at current instruction: TWNE temp, NL3. We're here because
 357      * temp > NL3 and temp is the end of the allocation, and NL3 is
 358      * current-region-end-addr.
 359      *
 360      * We need to adjust temp and alloc-tn.
 361      */
 362
 363     pc = (unsigned int *) (*os_context_pc_addr(context));
 364     inst = pc[0];
 365     end_addr = (inst >> 11) & 0x1f;
 366     target = (inst >> 16) & 0x1f;
 367
 368     target_ptr = *os_context_register_addr(context, target);
 369
 370 #if 0
 371     fprintf(stderr, "handle_allocation_trap at %p:\n", pc);
 372     fprintf(stderr, "boxed_region.free_pointer: %p\n", boxed_region.free_pointer);
 373     fprintf(stderr, "boxed_region.end_addr: %p\n", boxed_region.end_addr);
 374     fprintf(stderr, "target reg: %d, end_addr reg: %d\n", target, end_addr);
 375     fprintf(stderr, "target: %x\n", *os_context_register_addr(context, target));
 376     fprintf(stderr, "end_addr: %x\n", *os_context_register_addr(context, end_addr));
 377 #endif
 378
 379 #if 0
 380     fprintf(stderr, "handle_allocation_trap at %p:\n", pc);
 381     fprintf(stderr, "  trap inst = 0x%08x\n", inst);
 382     fprintf(stderr, "  target reg = %s\n", lisp_register_names[target]);
 383 #endif
 384
 385     /*
 386      * Go back and look at the add/addi instruction.  The second src arg
 387      * is the size of the allocation.  Get it and call alloc to allocate
 388      * new space.
 389      */
 390     inst = pc[-1];
 391     opcode = inst >> 26;
 392 #if 0
 393     fprintf(stderr, "  add inst  = 0x%08x, opcode = %d\n", inst, opcode);
 394 #endif
 395     if (opcode == 14) {
 396         /*
 397          * ADDI temp-tn, alloc-tn, size
 398          *
 399          * Extract the size
 400          */
 401         size = (inst & 0xffff);
 402     } else if (opcode == 31) {
 403         /*
 404          * ADD temp-tn, alloc-tn, size-tn
 405          *
 406          * Extract the size
 407          */
 408         int reg;
 409
 410         reg = (inst >> 11) & 0x1f;
 411 #if 0
 412         fprintf(stderr, "  add, reg = %s\n", lisp_register_names[reg]);
 413 #endif
 414         size = *os_context_register_addr(context, reg);
 415
 416     }
 417
 418 #if 0
 419     fprintf(stderr, "Alloc %d to %s\n", size, lisp_register_names[target]);
 420 #endif
 421
 422 #if INLINE_ALLOC_DEBUG
 423     if ((((unsigned long)boxed_region.end_addr + size) / PAGE_SIZE) ==
 424         (((unsigned long)boxed_region.end_addr) / PAGE_SIZE)) {
 425       fprintf(stderr,"*** possibly bogus trap allocation of %d bytes at %p\n",
 426               size, target_ptr);
 427       fprintf(stderr, "    dynamic_space_free_pointer: %p, boxed_region.end_addr %p\n",
 428               dynamic_space_free_pointer, boxed_region.end_addr);
 429     }
 430 #endif
 431
 432 #if 0
 433     fprintf(stderr, "Ready to alloc\n");
 434     fprintf(stderr, "free_pointer = 0x%08x\n",
 435             dynamic_space_free_pointer);
 436 #endif
 437
 438     /*
 439      * alloc-tn was incremented by size.  Need to decrement it by size
 440      * to restore its original value. This is not true on GENCGC
 441      * anymore. d_s_f_p and reg_alloc get out of sync, but the p_a
 442      * bits stay intact and we set it to the proper value when it
 443      * needs to be. Keep this comment here for the moment in case
 444      * somebody tries to figure out what happened here.
 445      */
 446     /*    dynamic_space_free_pointer =
 447         (lispobj *) ((long) dynamic_space_free_pointer - size);
 448     */
 449 #if 0
 450     fprintf(stderr, "free_pointer = 0x%08x new\n",
 451             dynamic_space_free_pointer);
 452 #endif
 453
 454     {
 455         extern lispobj* alloc(sword_t);
 456         struct interrupt_data *data =
 457             arch_os_get_current_thread()->interrupt_data;
 458         data->allocation_trap_context = context;
 459         memory = (char *) alloc(size);
 460         data->allocation_trap_context = 0;
 461     }
 462
 463 #if 0
 464     fprintf(stderr, "alloc returned %p\n", memory);
 465     fprintf(stderr, "free_pointer = 0x%08x\n",
 466             dynamic_space_free_pointer);
 467 #endif
 468
 469     /*
 470      * The allocation macro wants the result to point to the end of the
 471      * object!
 472      */
 473     memory += size;
 474
 475 #if 0
 476     fprintf(stderr, "object end at %p\n", memory);
 477 #endif
 478
 479     *os_context_register_addr(context, target) = (unsigned long) memory;
 480 #ifndef LISP_FEATURE_SB_THREAD
 481     /* This is handled by the fake_foreign_function_call machinery on
 482      * threaded targets. */
 483     *os_context_register_addr(context, reg_ALLOC) =
 484       (unsigned long) dynamic_space_free_pointer
 485       | (*os_context_register_addr(context, reg_ALLOC)
 486          & LOWTAG_MASK);
 487 #endif
 488
 489     if (were_in_lisp) {
 490         undo_fake_foreign_function_call(context);
 491     }
 492
 493     /* Skip the allocation trap and the write of the updated free
 494      * pointer back to the allocation region.  This is two
 495      * instructions when threading is enabled and four instructions
 496      * otherwise. */
 497 #ifdef LISP_FEATURE_SB_THREAD
 498     (*os_context_pc_addr(context)) = (unsigned int)(pc + 2);
 499 #else
 500     (*os_context_pc_addr(context)) = (unsigned int)(pc + 4);
 501 #endif
 502
 503 }
 504 #endif
 505
 506 void
 507 arch_handle_breakpoint(os_context_t *context)
 508 {
 509     handle_breakpoint(context);
 510 }
 511
 512 void
 513 arch_handle_fun_end_breakpoint(os_context_t *context)
 514 {
 515     *os_context_pc_addr(context)
 516         =(int)handle_fun_end_breakpoint(context);
 517 }
 518
 519 void
 520 arch_handle_after_breakpoint(os_context_t *context)
 521 {
 522     *skipped_break_addr = TRAP_INSTRUCTION(trap_Breakpoint);
 523     os_flush_icache((os_vm_address_t) skipped_break_addr,
 524                     sizeof(unsigned int));
 525     skipped_break_addr = NULL;
 526     *(unsigned int *)*os_context_pc_addr(context)
 527         = displaced_after_inst;
 528     *os_context_sigmask_addr(context)= orig_sigmask;
 529     os_flush_icache((os_vm_address_t) *os_context_pc_addr(context),
 530                     sizeof(unsigned int));
 531 }
 532
 533 void
 534 arch_handle_single_step_trap(os_context_t *context, int trap)
 535 {
 536     unsigned int code = *((u32 *)(*os_context_pc_addr(context)));
 537     int register_offset = code >> 5 & 0x1f;
 538     handle_single_step_trap(context, trap, register_offset);
 539     arch_skip_instruction(context);
 540 }
 541
 542 static void
 543 sigtrap_handler(int signal, siginfo_t *siginfo, os_context_t *context)
 544 {
 545     unsigned int code;
 546
 547     code=*((u32 *)(*os_context_pc_addr(context)));
 548     if (code == ((3 << 26) | (0x18 << 21) | (reg_NL3 << 16))||
 549         /* trap instruction from do_pending_interrupt */
 550         code == 0x7fe00008) {
 551         arch_clear_pseudo_atomic_interrupted(context);
 552         arch_skip_instruction(context);
 553         /* interrupt or GC was requested in PA; now we're done with the
 554            PA section we may as well get around to it */
 555         interrupt_handle_pending(context);
 556         return;
 557     }
 558
 559 #ifdef LISP_FEATURE_GENCGC
 560     /* Is this an allocation trap? */
 561     if (allocation_trap_p(context)) {
 562         handle_allocation_trap(context);
 563         return;
 564     }
 565 #endif
 566
 567     if ((code >> 16) == ((3 << 10) | (6 << 5))) {
 568         /* twllei reg_ZERO,N will always trap if reg_ZERO = 0 */
 569         int trap = code & 0x1f;
 570         handle_trap(context,trap);
 571         return;
 572     }
 573     /* twi :ne ... or twi ... nargs */
 574     if (((code >> 26) == 3) && (((code >> 21) & 31) == 24
 575                                 || ((code >> 16) & 31) == reg_NARGS
 576         )) {
 577         interrupt_internal_error(context, 0);
 578         return;
 579     }
 580
 581     interrupt_handle_now(signal, (siginfo_t *)code, context);
 582 }
 583
 584
 585 void arch_install_interrupt_handlers()
 586 {
 587     undoably_install_low_level_interrupt_handler(SIGILL, sigtrap_handler);
 588     undoably_install_low_level_interrupt_handler(SIGTRAP, sigtrap_handler);
 589 }
 590
 591 void
 592 ppc_flush_icache(os_vm_address_t address, os_vm_size_t length)
 593 {
 594   os_vm_address_t end = (os_vm_address_t) ((int)(address+length+(32-1)) &~(32-1));
 595   extern void ppc_flush_cache_line(os_vm_address_t);
 596
 597   while (address < end) {
 598     ppc_flush_cache_line(address);
 599     address += 32;
 600   }
 601 }
 602
 603 #ifdef LISP_FEATURE_LINKAGE_TABLE
 604
 605 /* Linkage tables for PowerPC
 606  *
 607  * Linkage entry size is 16, because we need at least 4 instructions to
 608  * implement a jump.
 609  */
 610
 611 /*
 612  * Define the registers to use in the linkage jump table. Can be the
 613  * same. Some care must be exercised when choosing these. It has to be
 614  * a register that is not otherwise being used. reg_NFP is a good
 615  * choice. call_into_c trashes reg_NFP without preserving it, so we can
 616  * trash it in the linkage jump table.
 617  */
 618 #define LINKAGE_TEMP_REG        reg_NFP
 619 #define LINKAGE_ADDR_REG        reg_NFP
 620
 621 /*
 622  * Insert the necessary jump instructions at the given address.
 623  */
 624 void
 625 arch_write_linkage_table_jmp(char *reloc_addr, void *target_addr)
 626 {
 627   /*
 628    * Make JMP to function entry.
 629    *
 630    * The instruction sequence is:
 631    *
 632    *        addis 13, 0, (hi part of addr)
 633    *        ori   13, 13, (low part of addr)
 634    *        mtctr 13
 635    *        bctr
 636    *
 637    */
 638   int* inst_ptr;
 639   unsigned long hi;                   /* Top 16 bits of address */
 640   unsigned long lo;                   /* Low 16 bits of address */
 641   unsigned int inst;
 642
 643   inst_ptr = (int*) reloc_addr;
 644
 645   /*
 646    * Split the target address into hi and lo parts for the sethi
 647    * instruction.  hi is the top 22 bits.  lo is the low 10 bits.
 648    */
 649   hi = (unsigned long) target_addr;
 650   lo = hi & 0xffff;
 651   hi >>= 16;
 652
 653   /*
 654    * addis 13, 0, (hi part)
 655    */
 656
 657   inst = (15 << 26) | (LINKAGE_TEMP_REG << 21) | (0 << 16) | hi;
 658   *inst_ptr++ = inst;
 659
 660   /*
 661    * ori 13, 13, (lo part)
 662    */
 663
 664   inst = (24 << 26) | (LINKAGE_TEMP_REG << 21) | (LINKAGE_TEMP_REG << 16) | lo;
 665   *inst_ptr++ = inst;
 666
 667   /*
 668    * mtctr 13
 669    */
 670
 671   inst = (31 << 26) | (LINKAGE_TEMP_REG << 21) | (9 << 16) | (467 << 1);
 672   *inst_ptr++ = inst;
 673
 674   /*
 675    * bctr
 676    */
 677
 678   inst = (19 << 26) | (20 << 21) | (528 << 1);
 679   *inst_ptr++ = inst;
 680
 681   os_flush_icache((os_vm_address_t) reloc_addr, (char*) inst_ptr - reloc_addr);
 682 }
 683
 684 void
 685 arch_write_linkage_table_ref(void * reloc_addr, void *target_addr)
 686 {
 687     *(unsigned long *)reloc_addr = (unsigned long)target_addr;
 688 }
 689
 690 #endif