src/runtime/sparc-arch.c

   1 /*
   2  * This software is part of the SBCL system. See the README file for
   3  * more information.
   4  *
   5  * This software is derived from the CMU CL system, which was
   6  * written at Carnegie Mellon University and released into the
   7  * public domain. The software is in the public domain and is
   8  * provided with absolutely no warranty. See the COPYING and CREDITS
   9  * files for more information.
  10  */
  11 #include <stdio.h>
  12
  13 #include "sbcl.h"
  14 #include "runtime.h"
  15 #include "arch.h"
  16 #include "globals.h"
  17 #include "validate.h"
  18 #include "os.h"
  19 #include "lispregs.h"
  20 #include "signal.h"
  21 #include "alloc.h"
  22 #include "interrupt.h"
  23 #include "interr.h"
  24 #include "breakpoint.h"
  25 #include "monitor.h"
  26
  27 #ifdef LISP_FEATURE_LINUX
  28 extern int linux_sparc_siginfo_bug;
  29 #endif
  30
  31 void arch_init(void)
  32 {
  33     return;
  34 }
  35
  36 os_vm_address_t arch_get_bad_addr(int sig, siginfo_t *code, os_context_t *context)
  37 {
  38 #if 1 /* New way. */
  39     return (os_vm_address_t)code->si_addr;
  40 #else /* Old way, almost certainly predates sigaction(2)-style handlers */
  41     unsigned int badinst;
  42     unsigned int *pc;
  43     int rs1;
  44
  45     pc = (unsigned int *)(*os_context_pc_addr(context));
  46
  47     /* On the sparc, we have to decode the instruction. */
  48
  49     /* Make sure it's not the pc thats bogus, and that it was lisp code */
  50     /* that caused the fault. */
  51     if ((unsigned long) pc & 3) {
  52       /* Unaligned */
  53       return NULL;
  54     }
  55     if ((pc < READ_ONLY_SPACE_START ||
  56          pc >= READ_ONLY_SPACE_START+READ_ONLY_SPACE_SIZE) &&
  57         (pc < current_dynamic_space ||
  58          pc >= current_dynamic_space + dynamic_space_size)) {
  59       return NULL;
  60     }
  61
  62     badinst = *pc;
  63
  64     if ((badinst >> 30) != 3)
  65         /* All load/store instructions have op = 11 (binary) */
  66         return 0;
  67
  68     rs1 = (badinst>>14)&0x1f;
  69
  70     if (badinst & (1<<13)) {
  71         /* r[rs1] + simm(13) */
  72         int simm13 = badinst & 0x1fff;
  73
  74         if (simm13 & (1<<12))
  75             simm13 |= -1<<13;
  76
  77         return (os_vm_address_t)
  78             (*os_context_register_addr(context, rs1)+simm13);
  79     }
  80     else {
  81         /* r[rs1] + r[rs2] */
  82         int rs2 = badinst & 0x1f;
  83
  84         return (os_vm_address_t)
  85             (*os_context_register_addr(context, rs1) +
  86              *os_context_register_addr(context, rs2));
  87     }
  88 #endif
  89 }
  90
  91 void arch_skip_instruction(os_context_t *context)
  92 {
  93     *os_context_pc_addr(context) = *os_context_npc_addr(context);
  94     /* Note that we're doing integer arithmetic here, not pointer. So
  95      * the value that the return value of os_context_npc_addr() points
  96      * to will be incremented by 4, not 16.
  97      */
  98     *os_context_npc_addr(context) += 4;
  99 }
 100
 101 unsigned char *arch_internal_error_arguments(os_context_t *context)
 102 {
 103     return (unsigned char *)(*os_context_pc_addr(context) + 4);
 104 }
 105
 106 boolean arch_pseudo_atomic_atomic(os_context_t *context)
 107 {
 108     /* FIXME: this foreign_function_call_active test is dubious at
 109      * best. If a foreign call is made in a pseudo atomic section
 110      * (?) or more likely a pseudo atomic section is in a foreign
 111      * call then an interrupt is executed immediately. Maybe it
 112      * has to do with C code not maintaining pseudo atomic
 113      * properly. MG - 2005-08-10
 114      *
 115      * The foreign_function_call_active used to live at each call-site
 116      * to arch_pseudo_atomic_atomic, but this seems clearer.
 117      * --NS 2007-05-15 */
 118     return (!foreign_function_call_active)
 119         && ((*os_context_register_addr(context,reg_ALLOC)) & 4);
 120 }
 121
 122 void arch_set_pseudo_atomic_interrupted(os_context_t *context)
 123 {
 124     *os_context_register_addr(context,reg_ALLOC) |=  1;
 125 }
 126
 127 void arch_clear_pseudo_atomic_interrupted(os_context_t *context)
 128 {
 129     *os_context_register_addr(context,reg_ALLOC) &= ~1;
 130 }
 131
 132 unsigned int arch_install_breakpoint(void *pc)
 133 {
 134     unsigned int *ptr = (unsigned int *)pc;
 135     unsigned int result = *ptr;
 136     *ptr = trap_Breakpoint;
 137
 138     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 139
 140     return result;
 141 }
 142
 143 void arch_remove_breakpoint(void *pc, unsigned int orig_inst)
 144 {
 145     *(unsigned int *)pc = orig_inst;
 146     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 147 }
 148
 149 /*
 150  * Perform the instruction that we overwrote with a breakpoint.  As we
 151  * don't have a single-step facility, this means we have to:
 152  * - put the instruction back
 153  * - put a second breakpoint at the following instruction,
 154  *   set after_breakpoint and continue execution.
 155  *
 156  * When the second breakpoint is hit (very shortly thereafter, we hope)
 157  * sigtrap_handler gets called again, but follows the AfterBreakpoint
 158  * arm, which
 159  * - puts a bpt back in the first breakpoint place (running across a
 160  *   breakpoint shouldn't cause it to be uninstalled)
 161  * - replaces the second bpt with the instruction it was meant to be
 162  * - carries on
 163  *
 164  * Clear?
 165  */
 166 static unsigned int *skipped_break_addr, displaced_after_inst;
 167 static sigset_t orig_sigmask;
 168
 169 void arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst)
 170 {
 171     unsigned int *pc = (unsigned int *)(*os_context_pc_addr(context));
 172     unsigned int *npc = (unsigned int *)(*os_context_npc_addr(context));
 173
 174   /*  orig_sigmask = context->sigmask;
 175       sigemptyset(&context->sigmask); */
 176   /* FIXME!!! */
 177   /* FILLBLOCKSET(&context->uc_sigmask);*/
 178
 179     *pc = orig_inst;
 180     os_flush_icache((os_vm_address_t) pc, sizeof(unsigned int));
 181     skipped_break_addr = pc;
 182     displaced_after_inst = *npc;
 183     *npc = trap_AfterBreakpoint;
 184     os_flush_icache((os_vm_address_t) npc, sizeof(unsigned int));
 185
 186 }
 187
 188 static int pseudo_atomic_trap_p(os_context_t *context)
 189 {
 190     unsigned int* pc;
 191     unsigned int badinst;
 192     int result;
 193
 194
 195     pc = (unsigned int*) *os_context_pc_addr(context);
 196     badinst = *pc;
 197     result = 0;
 198
 199     /* Check to see if the current instruction is a pseudo-atomic-trap */
 200     if (((badinst >> 30) == 2) && (((badinst >> 19) & 0x3f) == 0x3a)
 201         && (((badinst >> 13) & 1) == 1) && ((badinst & 0x7f) == PSEUDO_ATOMIC_TRAP))
 202         {
 203             unsigned int previnst;
 204             previnst = pc[-1];
 205             /*
 206              * Check to see if the previous instruction was an andcc alloc-tn,
 207              * 3, zero-tn instruction.
 208              */
 209             if (((previnst >> 30) == 2) && (((previnst >> 19) & 0x3f) == 0x11)
 210                 && (((previnst >> 14) & 0x1f) == reg_ALLOC)
 211                 && (((previnst >> 25) & 0x1f) == reg_ZERO)
 212                 && (((previnst >> 13) & 1) == 1)
 213                 && ((previnst & 0x1fff) == 3))
 214                 {
 215                     result = 1;
 216                 }
 217             else
 218                 {
 219                     fprintf(stderr, "Oops!  Got a PSEUDO-ATOMIC-TRAP without a preceeding andcc!\n");
 220                 }
 221         }
 222     return result;
 223 }
 224
 225 void
 226 arch_handle_breakpoint(os_context_t *context)
 227 {
 228     handle_breakpoint(context);
 229 }
 230
 231 void
 232 arch_handle_fun_end_breakpoint(os_context_t *context)
 233 {
 234     *os_context_pc_addr(context) = (int) handle_fun_end_breakpoint(context);
 235     *os_context_npc_addr(context) = *os_context_pc_addr(context) + 4;
 236 }
 237
 238 void
 239 arch_handle_after_breakpoint(os_context_t *context)
 240 {
 241     *skipped_break_addr = trap_Breakpoint;
 242     os_flush_icache(skipped_break_addr, sizeof(unsigned int));
 243     skipped_break_addr = NULL;
 244     *(unsigned long *) os_context_pc_addr(context) = displaced_after_inst;
 245     /* context->sigmask = orig_sigmask; */
 246     os_flush_icache((os_vm_address_t) os_context_pc_addr(context), sizeof(unsigned int));
 247 }
 248
 249 void
 250 arch_handle_single_step_trap(os_context_t *context, int trap)
 251 {
 252     unsigned int code = *((u32 *)(*os_context_pc_addr(context)));
 253     int register_offset = code >> 5 & 0x1f;
 254     handle_single_step_trap(context, trap, register_offset);
 255     arch_skip_instruction(context);
 256 }
 257
 258 #ifdef LISP_FEATURE_GENCGC
 259 void
 260 arch_handle_allocation_trap(os_context_t *context)
 261 {
 262     unsigned int* pc;
 263     unsigned int or_inst;
 264     int rs1;
 265     int size;
 266     int immed;
 267     int context_index;
 268     boolean were_in_lisp;
 269     char* memory;
 270
 271     if (foreign_function_call_active)
 272       lose("Allocation trap inside foreign code.");
 273
 274     pc = (unsigned int*) *os_context_pc_addr(context);
 275     or_inst = pc[-1];
 276
 277     /*
 278      * The instruction before this trap instruction had better be an OR
 279      * instruction!
 280      */
 281     if (!(((or_inst >> 30) == 2) && (((or_inst >> 19) & 0x1f) == 2)))
 282         lose("Allocation trap not preceded by an OR instruction: 0x%08x",
 283              or_inst);
 284
 285     /*
 286      * An OR instruction.  RS1 is the register we want to allocate to.
 287      * RS2 (or an immediate) is the size.
 288      */
 289     rs1 = (or_inst >> 14) & 0x1f;
 290     immed = (or_inst >> 13) & 1;
 291
 292     if (immed == 1)
 293         size = or_inst & 0x1fff;
 294     else {
 295         size = or_inst & 0x1f;
 296         size = *os_context_register_addr(context, size);
 297     }
 298
 299     fake_foreign_function_call(context);
 300
 301     /*
 302      * Allocate some memory, store the memory address in rs1.
 303      */
 304     {
 305         struct interrupt_data *data =
 306             arch_os_get_current_thread()->interrupt_data;
 307         data->allocation_trap_context = context;
 308         memory = alloc(size);
 309         data->allocation_trap_context = 0;
 310     }
 311     *os_context_register_addr(context, rs1) = memory;
 312
 313     undo_fake_foreign_function_call(context);
 314 }
 315 #endif
 316
 317 static void sigill_handler(int signal, siginfo_t *siginfo,
 318                            os_context_t *context)
 319 {
 320     if ((siginfo->si_code) == ILL_ILLOPC
 321 #ifdef LISP_FEATURE_LINUX
 322         || (linux_sparc_siginfo_bug && (siginfo->si_code == 2))
 323 #endif
 324         ) {
 325         int trap;
 326         unsigned int inst;
 327         unsigned int* pc = (unsigned int*) siginfo->si_addr;
 328
 329         inst = *pc;
 330         trap = inst & 0x1f;
 331         handle_trap(context,trap);
 332     }
 333     else if ((siginfo->si_code) == ILL_ILLTRP
 334 #ifdef LISP_FEATURE_LINUX
 335              || (linux_sparc_siginfo_bug && (siginfo->si_code) == 192)
 336 #endif
 337              ) {
 338         if (pseudo_atomic_trap_p(context)) {
 339             /* A trap instruction from a pseudo-atomic.  We just need
 340                to fixup up alloc-tn to remove the interrupted flag,
 341                skip over the trap instruction, and then handle the
 342                pending interrupt(s). */
 343             arch_clear_pseudo_atomic_interrupted(context);
 344             arch_skip_instruction(context);
 345             interrupt_handle_pending(context);
 346         }
 347         else {
 348             interrupt_internal_error(context, 0);
 349         }
 350     }
 351     else {
 352         interrupt_handle_now(signal, siginfo, context);
 353     }
 354 }
 355
 356 void arch_install_interrupt_handlers()
 357 {
 358     undoably_install_low_level_interrupt_handler(SIGILL, sigill_handler);
 359 }
 360
 361 \f
 362 #ifdef LISP_FEATURE_LINKAGE_TABLE
 363
 364 /* This a naive port from CMUCL/sparc, which was mostly stolen from the
 365  * CMUCL/x86 version, with adjustments for sparc
 366  *
 367  * Linkage entry size is 16, because we need at least 3 instruction to
 368  * implement a jump:
 369  *
 370  *      sethi %hi(addr), %g4
 371  *      jmpl  [%g4 + %lo(addr)], %g5
 372  *      nop
 373  *
 374  * The Sparc V9 ABI seems to use 8 words for its jump tables.  Maybe
 375  * we should do the same?
 376  */
 377
 378 /*
 379  * Define the registers to use in the linkage jump table. Can be the
 380  * same. Some care must be exercised when choosing these. It has to be
 381  * a register that is not otherwise being used. reg_L0 is a good
 382  * choice. call_into_c trashes reg_L0 without preserving it, so we can
 383  * trash it in the linkage jump table.
 384  */
 385 #define LINKAGE_TEMP_REG        reg_L0
 386 #define LINKAGE_ADDR_REG        reg_L0
 387
 388 /*
 389  * Insert the necessary jump instructions at the given address.
 390  */
 391 void
 392 arch_write_linkage_table_jmp(char *reloc_addr, void *target_addr)
 393 {
 394   /*
 395    * Make JMP to function entry.
 396    *
 397    * The instruction sequence is:
 398    *
 399    *        sethi %hi(addr), temp_reg
 400    *        jmp   %temp_reg + %lo(addr), %addr_reg
 401    *        nop
 402    *        nop
 403    *
 404    */
 405   int* inst_ptr;
 406   unsigned long hi;                   /* Top 22 bits of address */
 407   unsigned long lo;                   /* Low 10 bits of address */
 408   unsigned int inst;
 409
 410   inst_ptr = (int*) reloc_addr;
 411
 412   /*
 413    * Split the target address into hi and lo parts for the sethi
 414    * instruction.  hi is the top 22 bits.  lo is the low 10 bits.
 415    */
 416   hi = (unsigned long) target_addr;
 417   lo = hi & 0x3ff;
 418   hi >>= 10;
 419
 420   /*
 421    * sethi %hi(addr), temp_reg
 422    */
 423
 424   inst = (0 << 30) | (LINKAGE_TEMP_REG << 25) | (4 << 22) | hi;
 425   *inst_ptr++ = inst;
 426
 427   /*
 428    * jmpl [temp_reg + %lo(addr)], addr_reg
 429    */
 430
 431   inst = (2U << 30) | (LINKAGE_ADDR_REG << 25) | (0x38 << 19)
 432     | (LINKAGE_TEMP_REG << 14) | (1 << 13) | lo;
 433   *inst_ptr++ = inst;
 434
 435   /* nop (really sethi 0, %g0) */
 436
 437   inst = (0 << 30) | (0 << 25) | (4 << 22) | 0;
 438
 439   *inst_ptr++ = inst;
 440   *inst_ptr++ = inst;
 441
 442   os_flush_icache((os_vm_address_t) reloc_addr, (char*) inst_ptr - reloc_addr);
 443 }
 444
 445 void
 446 arch_write_linkage_table_ref(void * reloc_addr, void *target_addr)
 447 {
 448     *(unsigned long *)reloc_addr = (unsigned long)target_addr;
 449 }
 450
 451 #endif