1 Programmable Interrupt Controller
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4 Written by Pawel Dziepak <pdziepak@quarnos.org>
5 Last modified: June 01, 2008
10 The main PIC task is to control all interrupts requests (IRQs) reported by
11 hardware. In most computers there are two PIC microcontrollers, each control
12 eight IRQs. When a device reports IRQ, dependently on the PIC configuration
13 a CPU interrupt is performed, which allow the device driver to do all needed
14 things to keep device working.
16 2. PIC configuration (ICW)
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19 PIC is once configured during system start. Then small changes in configuration
20 are performed only while loading or destroying device drivers (look at point 3,
21 Disabling/enabling IRQs).
23 When PIC is initialized, correct connections CPU interrupt - IRQ are set. It is
24 done by sending ICWs (initialization command word).
26 ICW1 has to be send to the ports 0x20 (master) and 0xA0 (slave).
28 0 if set, ICW4 will be sent
29 1 if set there is only one PIC, zero means that there are two PICs
31 3 method of reporting IRQs
32 4-7 signature of the command (0001b)
34 ICW2 and all following commands have to be send to the ports 0x21 (master)
38 3-7 offset of the interrupt vector (in translation IRQ-interrupt)
40 ICW3 is sent only when two PICs are present. The command is different for master
41 and for slave microcontroller.
44 0-7 if bit on specific position is set that means it is place of
45 connection with slave PIC
48 0-2 slave PIC's ID, not really used in standard PCs
51 ICW4 is sent only if bit 0 of ICW1 was set.
53 0 if set 8-bit interrupts vector will be used, if zeroed 16-bit
54 addressing will be used
55 1 if set mode AEOI will be enabled what means that EOI message
56 will be sent automatically
57 2 used to specify which controller is the command addressed to,
58 *only* when bit 3 is set
59 3 if set buffered mode will be enabled, not used on standard PCs
60 4 if set modifies method of transmission master-slave, not used
64 After receiving all 4 commands PIC will be configured and ready to work.
66 3. Disabling/enabling IRQs (OCW1)
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69 After initialization the main PIC functionallity can be controlled by two
70 ports. They can be used to disable or enable specific IRQ the hardware way.
71 These control registers are bit fields where each bit represents one of the
72 IRQs. If bit is set IRQ is disabled. Accessing these registers can be done
73 by using command OCW1 (operation control word) which can be send by
74 reading and/or writing to ports 0x21 (master PIC) and 0xA1 (slave PIC). Master
75 PIC controls IRQs 0-7, slave PIC controls IRQs 8-15.
80 IRQs are used to allow hardware to inform CPU that some event has happened.
81 Each IRQ is used by different device.
89 5 hard disk controller
90 6 floppy disk controller
98 14 hard disk controller
99 15 hard disk controller