1 \documentclass[a4paper,
10pt
]{article
}
3 \renewcommand*
{\tablename}{\small\textbf{Table
}}
4 \renewcommand*
{\figurename}{\small\textbf{Figure
}}
5 \renewcommand*
{\abstractname}{\small\textbf{Abstract
}}
9 \title{\textbf{Programmable Interrupt Controller
}}
10 \author{Pawel Dziepak
}
11 \date{\textit{January
09,
2009}}
14 \section{Role of the PIC
}
15 \paragraph{}The main PIC task is to control all interrupts requests (IRQs) reported by
16 the hardware. In most computers there are two PIC microcontrollers, each control
17 eight IRQs. When a device reports IRQ, dependently on the PIC configuration
18 a CPU interrupt is performed, which allow the device driver to do all needed
19 things to keep device working.
21 \section{PIC configuration (ICW)
}
25 \textbf{bit
} &
\textbf{meaning
} \\
26 0 & if set, ICW4 will be sent \\
27 1 & if set there is only one PIC, zero means that there are two PICs \\
29 3 & method of reporting IRQs \\
30 4-
7 & signature of the command (
0001b)
38 \textbf{bit
} &
\textbf{meaning
} \\
39 0-
2 & always zeroed \\
40 3-
7 & offset of the interrupt vector (in translation IRQ-interrupt)
47 \textbf{bit
} &
\textbf{meaning
} \\
48 0-
7 & if bit on a specific position is set it means that it is \\
49 & the place of the connection with slave PIC
51 \caption{ICW3 (master)
}
56 \textbf{bit
} &
\textbf{meaning
} \\
57 0-
2 & slave PIC's ID, not really used in standard PCs \\
60 \caption{ICW3 (slave)
}
65 \textbf{bit
} &
\textbf{meaning
} \\
66 0 & if set
8-bit interrupts vector will be used, if zeroed
16-bit \\
67 & addressing will be used \\
68 1 & if set mode AEOI will be enabled what means that EOI message \\
69 & will be sent automatically \\
70 2 & used to specify which controller is the command addressed to, \\
71 &
\textbf{only
} when bit
3 is set \\
72 3 & if set buffered mode will be enabled, not used on standard PCs \\
73 4 & if set modifies method of transmission master-slave, not used \\
75 7-
5 & always zeroed \\
81 \paragraph{}PIC is once configured during system start. Then small changes in configuration
82 are performed only while loading or destroying device drivers (look at point
3,
83 Disabling/enabling IRQs).
84 \paragraph{}When PIC is initialized, correct connections CPU interrupt - IRQ are set. It is
85 done by sending ICWs (initialization command word). The first ICW is sent to the port
\texttt{0x20} if
86 it is destinated for master or
\texttt{0xA0} if for slave. The other ICWs are sent to the ports
87 \texttt{0x21} for master and
\texttt{0xA1} for slave. ICW3 is sent only when there are two PICs in
88 the system. The command is different for master and for slave microcontroller. ICW4 is sent
89 only if first bit (bit
0) of ICW1 is set. Tables
\ref{icw1
} to
\ref{icw4
} presents the structure of each
90 ICW. After receiving all
4 commands PIC will be configured and ready to work.
92 \section{Disabling/enabling IRQs (OCW1)
}
93 \paragraph{}After initialization the main PIC functionallity can be controlled by two
94 ports. They can be used to disable or enable specific IRQ the hardware way.
95 These control registers are bit fields where each bit represents one of the
96 IRQs. If bit is set IRQ is disabled. Accessing these registers can be done
97 by using command OCW1 (operation control word) which can be send by
98 reading and/or writing to ports
\texttt{0x21} (master PIC) and
\texttt{0xA1} (slave PIC). Master
99 PIC controls IRQs
0-
7, slave PIC controls IRQs
8-
15.
101 \section{IRQs description
}
104 \textbf{IRQ
} &
\textbf{Device
}\\
108 3 & second serial port \\
109 4 & first serial port \\
110 5 & hard disk controller \\
111 6 & floppy disk controller \\
113 8 & real time clock \\
119 14 & hard disk controller \\
120 15 & hard disk controller
122 \caption{Devices assigned to specific IRQs
}
126 \paragraph{}IRQs are used to allow hardware to inform CPU that some event has happened.
127 Each IRQ is assigned to a certain device. Table
\ref{irqs
} shows which device calls which
128 IRQ. Positions marked as
\textit{not used
} are reserved for PCI and/or other buses automatic