4 #include "qemu-common.h"
10 /* PCI includes legacy ISA access. */
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
26 /* QEMU-specific Vendor and Device ID definitions */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
79 #define FMT_PCIBUS PRIx64
81 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
82 uint32_t address
, uint32_t data
, int len
);
83 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
84 uint32_t address
, int len
);
85 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
86 pcibus_t addr
, pcibus_t size
, int type
);
87 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
89 typedef struct PCIIORegion
{
90 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
93 pcibus_t filtered_size
;
96 MemoryRegion
*address_space
;
99 #define PCI_ROM_SLOT 6
100 #define PCI_NUM_REGIONS 7
102 #include "pci_regs.h"
104 /* PCI HEADER_TYPE */
105 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
107 /* Size of the standard PCI config header */
108 #define PCI_CONFIG_HEADER_SIZE 0x40
109 /* Size of the standard PCI config space */
110 #define PCI_CONFIG_SPACE_SIZE 0x100
111 /* Size of the standart PCIe config space: 4KB */
112 #define PCIE_CONFIG_SPACE_SIZE 0x1000
114 #define PCI_NUM_PINS 4 /* A-D */
116 /* Bits in cap_present field. */
118 QEMU_PCI_CAP_MSI
= 0x1,
119 QEMU_PCI_CAP_MSIX
= 0x2,
120 QEMU_PCI_CAP_EXPRESS
= 0x4,
122 /* multifunction capable device */
123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
124 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
126 /* command register SERR bit enabled */
127 #define QEMU_PCI_CAP_SERR_BITNR 4
128 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
133 /* PCI config space */
136 /* Used to enable config checks on load. Note that writable bits are
137 * never checked even if set in cmask. */
140 /* Used to implement R/W bytes */
143 /* Used to implement RW1C(Write 1 to Clear) bytes */
146 /* Used to allocate config space for capabilities. */
149 /* the following fields are read only */
153 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
155 /* do not access the following fields */
156 PCIConfigReadFunc
*config_read
;
157 PCIConfigWriteFunc
*config_write
;
159 /* IRQ objects for the INTA-INTD pins. */
162 /* Current IRQ levels. Used internally by the generic PCI code. */
165 /* Capability bits */
166 uint32_t cap_present
;
168 /* Offset of MSI-X capability in config space */
174 /* Space to store MSIX table */
175 uint8_t *msix_table_page
;
176 /* MMIO index used to map MSIX table and pending bit entries. */
177 MemoryRegion msix_mmio
;
178 /* Reference-count for entries actually in use by driver. */
179 unsigned *msix_entry_used
;
180 /* Region including the MSI-X table */
181 uint32_t msix_bar_size
;
182 /* Version id needed for VMState */
185 /* Offset of MSI capability in config space */
189 PCIExpressDevice exp
;
191 /* Location of option rom */
198 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
199 int instance_size
, int devfn
,
200 PCIConfigReadFunc
*config_read
,
201 PCIConfigWriteFunc
*config_write
);
203 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
204 uint8_t attr
, MemoryRegion
*memory
);
205 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
207 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
208 uint8_t offset
, uint8_t size
);
210 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
212 void pci_reserve_capability(PCIDevice
*pci_dev
, uint8_t offset
, uint8_t size
);
214 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
217 uint32_t pci_default_read_config(PCIDevice
*d
,
218 uint32_t address
, int len
);
219 void pci_default_write_config(PCIDevice
*d
,
220 uint32_t address
, uint32_t val
, int len
);
221 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
222 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
223 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
225 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
226 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
229 PCI_HOTPLUG_DISABLED
,
231 PCI_COLDPLUG_ENABLED
,
234 typedef int (*pci_hotplug_fn
)(DeviceState
*qdev
, PCIDevice
*pci_dev
,
235 PCIHotplugState state
);
236 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
238 MemoryRegion
*address_space_mem
,
239 MemoryRegion
*address_space_io
,
241 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
242 MemoryRegion
*address_space_mem
,
243 MemoryRegion
*address_space_io
,
245 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
246 void *irq_opaque
, int nirq
);
247 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
248 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*dev
);
249 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
250 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
252 MemoryRegion
*address_space_mem
,
253 MemoryRegion
*address_space_io
,
254 uint8_t devfn_min
, int nirq
);
255 void pci_device_reset(PCIDevice
*dev
);
256 void pci_bus_reset(PCIBus
*bus
);
258 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
);
260 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
261 const char *default_devaddr
);
262 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
263 const char *default_devaddr
);
264 int pci_bus_num(PCIBus
*s
);
265 void pci_for_each_device(PCIBus
*bus
, int bus_num
, void (*fn
)(PCIBus
*bus
, PCIDevice
*d
));
266 PCIBus
*pci_find_root_bus(int domain
);
267 int pci_find_domain(const PCIBus
*bus
);
268 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
);
269 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
270 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
271 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
);
273 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
274 unsigned int *slotp
, unsigned int *funcp
);
275 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
278 void do_pci_info_print(Monitor
*mon
, const QObject
*data
);
279 void do_pci_info(Monitor
*mon
, QObject
**ret_data
);
280 void pci_bridge_update_mappings(PCIBus
*b
);
282 void pci_device_deassert_intx(PCIDevice
*dev
);
285 pci_set_byte(uint8_t *config
, uint8_t val
)
290 static inline uint8_t
291 pci_get_byte(const uint8_t *config
)
297 pci_set_word(uint8_t *config
, uint16_t val
)
299 cpu_to_le16wu((uint16_t *)config
, val
);
302 static inline uint16_t
303 pci_get_word(const uint8_t *config
)
305 return le16_to_cpupu((const uint16_t *)config
);
309 pci_set_long(uint8_t *config
, uint32_t val
)
311 cpu_to_le32wu((uint32_t *)config
, val
);
314 static inline uint32_t
315 pci_get_long(const uint8_t *config
)
317 return le32_to_cpupu((const uint32_t *)config
);
321 pci_set_quad(uint8_t *config
, uint64_t val
)
323 cpu_to_le64w((uint64_t *)config
, val
);
326 static inline uint64_t
327 pci_get_quad(const uint8_t *config
)
329 return le64_to_cpup((const uint64_t *)config
);
333 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
335 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
339 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
341 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
345 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
347 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
351 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
353 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
357 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
359 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
363 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
365 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
369 * helper functions to do bit mask operation on configuration space.
370 * Just to set bit, use test-and-set and discard returned value.
371 * Just to clear bit, use test-and-clear and discard returned value.
372 * NOTE: They aren't atomic.
374 static inline uint8_t
375 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
377 uint8_t val
= pci_get_byte(config
);
378 pci_set_byte(config
, val
& ~mask
);
382 static inline uint8_t
383 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
385 uint8_t val
= pci_get_byte(config
);
386 pci_set_byte(config
, val
| mask
);
390 static inline uint16_t
391 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
393 uint16_t val
= pci_get_word(config
);
394 pci_set_word(config
, val
& ~mask
);
398 static inline uint16_t
399 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
401 uint16_t val
= pci_get_word(config
);
402 pci_set_word(config
, val
| mask
);
406 static inline uint32_t
407 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
409 uint32_t val
= pci_get_long(config
);
410 pci_set_long(config
, val
& ~mask
);
414 static inline uint32_t
415 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
417 uint32_t val
= pci_get_long(config
);
418 pci_set_long(config
, val
| mask
);
422 static inline uint64_t
423 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
425 uint64_t val
= pci_get_quad(config
);
426 pci_set_quad(config
, val
& ~mask
);
430 static inline uint64_t
431 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
433 uint64_t val
= pci_get_quad(config
);
434 pci_set_quad(config
, val
| mask
);
438 typedef int (*pci_qdev_initfn
)(PCIDevice
*dev
);
441 pci_qdev_initfn init
;
442 PCIUnregisterFunc
*exit
;
443 PCIConfigReadFunc
*config_read
;
444 PCIConfigWriteFunc
*config_write
;
450 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
451 uint16_t subsystem_id
; /* only for header type = 0 */
454 * pci-to-pci bridge or normal device.
455 * This doesn't mean pci host switch.
456 * When card bus bridge is supported, this would be enhanced.
461 int is_express
; /* is this device pci express? */
463 /* device isn't hot-pluggable */
470 void pci_qdev_register(PCIDeviceInfo
*info
);
471 void pci_qdev_register_many(PCIDeviceInfo
*info
);
473 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
475 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
478 PCIDevice
*pci_try_create_multifunction(PCIBus
*bus
, int devfn
,
481 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
482 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
483 PCIDevice
*pci_try_create(PCIBus
*bus
, int devfn
, const char *name
);
485 static inline int pci_is_express(const PCIDevice
*d
)
487 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
490 static inline uint32_t pci_config_size(const PCIDevice
*d
)
492 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;