hw/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu-common.h"
  22 #include "pci_bridge.h"
  23 #include "pcie.h"
  24 #include "msix.h"
  25 #include "msi.h"
  26 #include "pci_internals.h"
  27 #include "pcie_regs.h"
  28 #include "range.h"
  29
  30 //#define DEBUG_PCIE
  31 #ifdef DEBUG_PCIE
  32 # define PCIE_DPRINTF(fmt, ...)                                         \
  33     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  34 #else
  35 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  36 #endif
  37 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  38     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  39
  40
  41 /***************************************************************************
  42  * pci express capability helper functions
  43  */
  44 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  45 {
  46     int pos;
  47     uint8_t *exp_cap;
  48
  49     assert(pci_is_express(dev));
  50
  51     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  52                                  PCI_EXP_VER2_SIZEOF);
  53     if (pos < 0) {
  54         return pos;
  55     }
  56     dev->exp.exp_cap = pos;
  57     exp_cap = dev->config + pos;
  58
  59     /* capability register
  60        interrupt message number defaults to 0 */
  61     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  62                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  63                  PCI_EXP_FLAGS_VER2);
  64
  65     /* device capability register
  66      * table 7-12:
  67      * roll based error reporting bit must be set by all
  68      * Functions conforming to the ECN, PCI Express Base
  69      * Specification, Revision 1.1., or subsequent PCI Express Base
  70      * Specification revisions.
  71      */
  72     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  73
  74     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  75                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  76                  PCI_EXP_LNKCAP_ASPMS_0S |
  77                  PCI_EXP_LNK_MLW_1 |
  78                  PCI_EXP_LNK_LS_25);
  79
  80     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  81                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  82
  83     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  84                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  85
  86     pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  87     return pos;
  88 }
  89
  90 void pcie_cap_exit(PCIDevice *dev)
  91 {
  92     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
  93 }
  94
  95 uint8_t pcie_cap_get_type(const PCIDevice *dev)
  96 {
  97     uint32_t pos = dev->exp.exp_cap;
  98     assert(pos > 0);
  99     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 100             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 101 }
 102
 103 /* MSI/MSI-X */
 104 /* pci express interrupt message number */
 105 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 106 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 107 {
 108     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 109     assert(vector < 32);
 110     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 111     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 112                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 113 }
 114
 115 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 116 {
 117     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 118             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 119 }
 120
 121 void pcie_cap_deverr_init(PCIDevice *dev)
 122 {
 123     uint32_t pos = dev->exp.exp_cap;
 124     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 125                                PCI_EXP_DEVCAP_RBER);
 126     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 127                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 128                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 129     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 130                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 131                                PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 132 }
 133
 134 void pcie_cap_deverr_reset(PCIDevice *dev)
 135 {
 136     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 137     pci_long_test_and_clear_mask(devctl,
 138                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 139                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 140 }
 141
 142 static void hotplug_event_update_event_status(PCIDevice *dev)
 143 {
 144     uint32_t pos = dev->exp.exp_cap;
 145     uint8_t *exp_cap = dev->config + pos;
 146     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 147     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 148
 149     dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 150         (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 151 }
 152
 153 static void hotplug_event_notify(PCIDevice *dev)
 154 {
 155     bool prev = dev->exp.hpev_notified;
 156
 157     hotplug_event_update_event_status(dev);
 158
 159     if (prev == dev->exp.hpev_notified) {
 160         return;
 161     }
 162
 163     /* Note: the logic above does not take into account whether interrupts
 164      * are masked. The result is that interrupt will be sent when it is
 165      * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 166      * The Port may optionally send an MSI when there are hot-plug events that
 167      * occur while interrupt generation is disabled, and interrupt generation is
 168      * subsequently enabled. */
 169     if (msix_enabled(dev)) {
 170         msix_notify(dev, pcie_cap_flags_get_vector(dev));
 171     } else if (msi_enabled(dev)) {
 172         msi_notify(dev, pcie_cap_flags_get_vector(dev));
 173     } else {
 174         qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
 175     }
 176 }
 177
 178 /*
 179  * A PCI Express Hot-Plug Event has occured, so update slot status register
 180  * and notify OS of the event if necessary.
 181  *
 182  * 6.7.3 PCI Express Hot-Plug Events
 183  * 6.7.3.4 Software Notification of Hot-Plug Events
 184  */
 185 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 186 {
 187     /* Minor optimization: if nothing changed - no event is needed. */
 188     if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 189                                    PCI_EXP_SLTSTA, event)) {
 190         return;
 191     }
 192     hotplug_event_notify(dev);
 193 }
 194
 195 static int pcie_cap_slot_hotplug(DeviceState *qdev,
 196                                  PCIDevice *pci_dev, PCIHotplugState state)
 197 {
 198     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
 199     uint8_t *exp_cap = d->config + d->exp.exp_cap;
 200     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 201
 202     /* Don't send event when device is enabled during qemu machine creation:
 203      * it is present on boot, no hotplug event is necessary. We do send an
 204      * event when the device is disabled later. */
 205     if (state == PCI_COLDPLUG_ENABLED) {
 206         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 207                                    PCI_EXP_SLTSTA_PDS);
 208         return 0;
 209     }
 210
 211     PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 212     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 213         /* the slot is electromechanically locked.
 214          * This error is propagated up to qdev and then to HMP/QMP.
 215          */
 216         return -EBUSY;
 217     }
 218
 219     /* TODO: multifunction hot-plug.
 220      * Right now, only a device of function = 0 is allowed to be
 221      * hot plugged/unplugged.
 222      */
 223     assert(PCI_FUNC(pci_dev->devfn) == 0);
 224
 225     if (state == PCI_HOTPLUG_ENABLED) {
 226         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 227                                    PCI_EXP_SLTSTA_PDS);
 228         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 229     } else {
 230         qdev_free(&pci_dev->qdev);
 231         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 232                                      PCI_EXP_SLTSTA_PDS);
 233         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 234     }
 235     return 0;
 236 }
 237
 238 /* pci express slot for pci express root/downstream port
 239    PCI express capability slot registers */
 240 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 241 {
 242     uint32_t pos = dev->exp.exp_cap;
 243
 244     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 245                                PCI_EXP_FLAGS_SLOT);
 246
 247     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 248                                  ~PCI_EXP_SLTCAP_PSN);
 249     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 250                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 251                                PCI_EXP_SLTCAP_EIP |
 252                                PCI_EXP_SLTCAP_HPS |
 253                                PCI_EXP_SLTCAP_HPC |
 254                                PCI_EXP_SLTCAP_PIP |
 255                                PCI_EXP_SLTCAP_AIP |
 256                                PCI_EXP_SLTCAP_ABP);
 257
 258     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 259                                  PCI_EXP_SLTCTL_PIC |
 260                                  PCI_EXP_SLTCTL_AIC);
 261     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 262                                PCI_EXP_SLTCTL_PIC_OFF |
 263                                PCI_EXP_SLTCTL_AIC_OFF);
 264     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 265                                PCI_EXP_SLTCTL_PIC |
 266                                PCI_EXP_SLTCTL_AIC |
 267                                PCI_EXP_SLTCTL_HPIE |
 268                                PCI_EXP_SLTCTL_CCIE |
 269                                PCI_EXP_SLTCTL_PDCE |
 270                                PCI_EXP_SLTCTL_ABPE);
 271     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 272      * make the bit writable here in order to detect 1b is written.
 273      * pcie_cap_slot_write_config() test-and-clear the bit, so
 274      * this bit always returns 0 to the guest.
 275      */
 276     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 277                                PCI_EXP_SLTCTL_EIC);
 278
 279     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 280                                PCI_EXP_HP_EV_SUPPORTED);
 281
 282     dev->exp.hpev_notified = false;
 283
 284     pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 285                     pcie_cap_slot_hotplug, &dev->qdev);
 286 }
 287
 288 void pcie_cap_slot_reset(PCIDevice *dev)
 289 {
 290     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 291
 292     PCIE_DEV_PRINTF(dev, "reset\n");
 293
 294     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 295                                  PCI_EXP_SLTCTL_EIC |
 296                                  PCI_EXP_SLTCTL_PIC |
 297                                  PCI_EXP_SLTCTL_AIC |
 298                                  PCI_EXP_SLTCTL_HPIE |
 299                                  PCI_EXP_SLTCTL_CCIE |
 300                                  PCI_EXP_SLTCTL_PDCE |
 301                                  PCI_EXP_SLTCTL_ABPE);
 302     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 303                                PCI_EXP_SLTCTL_PIC_OFF |
 304                                PCI_EXP_SLTCTL_AIC_OFF);
 305
 306     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 307                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 308                                                         the lock is released */
 309                                  PCI_EXP_SLTSTA_CC |
 310                                  PCI_EXP_SLTSTA_PDC |
 311                                  PCI_EXP_SLTSTA_ABP);
 312
 313     hotplug_event_update_event_status(dev);
 314 }
 315
 316 void pcie_cap_slot_write_config(PCIDevice *dev,
 317                                 uint32_t addr, uint32_t val, int len)
 318 {
 319     uint32_t pos = dev->exp.exp_cap;
 320     uint8_t *exp_cap = dev->config + pos;
 321     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 322
 323     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 324         return;
 325     }
 326
 327     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 328                                      PCI_EXP_SLTCTL_EIC)) {
 329         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 330         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 331         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 332                         "sltsta -> 0x%02"PRIx16"\n",
 333                         sltsta);
 334     }
 335
 336     hotplug_event_notify(dev);
 337
 338     /*
 339      * 6.7.3.2 Command Completed Events
 340      *
 341      * Software issues a command to a hot-plug capable Downstream Port by
 342      * issuing a write transaction that targets any portion of the Port’s Slot
 343      * Control register. A single write to the Slot Control register is
 344      * considered to be a single command, even if the write affects more than
 345      * one field in the Slot Control register. In response to this transaction,
 346      * the Port must carry out the requested actions and then set the
 347      * associated status field for the command completed event. */
 348
 349     /* Real hardware might take a while to complete requested command because
 350      * physical movement would be involved like locking the electromechanical
 351      * lock.  However in our case, command is completed instantaneously above,
 352      * so send a command completion event right now.
 353      */
 354     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 355 }
 356
 357 int pcie_cap_slot_post_load(void *opaque, int version_id)
 358 {
 359     PCIDevice *dev = opaque;
 360     hotplug_event_update_event_status(dev);
 361     return 0;
 362 }
 363
 364 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 365 {
 366     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 367 }
 368
 369 /* root control/capabilities/status. PME isn't emulated for now */
 370 void pcie_cap_root_init(PCIDevice *dev)
 371 {
 372     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 373                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 374                  PCI_EXP_RTCTL_SEFEE);
 375 }
 376
 377 void pcie_cap_root_reset(PCIDevice *dev)
 378 {
 379     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 380 }
 381
 382 /* function level reset(FLR) */
 383 void pcie_cap_flr_init(PCIDevice *dev)
 384 {
 385     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 386                                PCI_EXP_DEVCAP_FLR);
 387
 388     /* Although reading BCR_FLR returns always 0,
 389      * the bit is made writable here in order to detect the 1b is written
 390      * pcie_cap_flr_write_config() test-and-clear the bit, so
 391      * this bit always returns 0 to the guest.
 392      */
 393     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 394                                PCI_EXP_DEVCTL_BCR_FLR);
 395 }
 396
 397 void pcie_cap_flr_write_config(PCIDevice *dev,
 398                                uint32_t addr, uint32_t val, int len)
 399 {
 400     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 401     if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
 402         /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
 403            so the handler can detect FLR by looking at this bit. */
 404         pci_device_reset(dev);
 405         pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
 406     }
 407 }
 408
 409 /* Alternative Routing-ID Interpretation (ARI) */
 410 /* ari forwarding support for down stream port */
 411 void pcie_cap_ari_init(PCIDevice *dev)
 412 {
 413     uint32_t pos = dev->exp.exp_cap;
 414     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 415                                PCI_EXP_DEVCAP2_ARI);
 416     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 417                                PCI_EXP_DEVCTL2_ARI);
 418 }
 419
 420 void pcie_cap_ari_reset(PCIDevice *dev)
 421 {
 422     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 423     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 424 }
 425
 426 bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 427 {
 428     if (!pci_is_express(dev)) {
 429         return false;
 430     }
 431     if (!dev->exp.exp_cap) {
 432         return false;
 433     }
 434
 435     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 436         PCI_EXP_DEVCTL2_ARI;
 437 }
 438
 439 /**************************************************************************
 440  * pci express extended capability allocation functions
 441  * uint16_t ext_cap_id (16 bit)
 442  * uint8_t cap_ver (4 bit)
 443  * uint16_t cap_offset (12 bit)
 444  * uint16_t ext_cap_size
 445  */
 446
 447 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 448                                           uint16_t *prev_p)
 449 {
 450     uint16_t prev = 0;
 451     uint16_t next;
 452     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 453
 454     if (!header) {
 455         /* no extended capability */
 456         next = 0;
 457         goto out;
 458     }
 459     for (next = PCI_CONFIG_SPACE_SIZE; next;
 460          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 461
 462         assert(next >= PCI_CONFIG_SPACE_SIZE);
 463         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 464
 465         header = pci_get_long(dev->config + next);
 466         if (PCI_EXT_CAP_ID(header) == cap_id) {
 467             break;
 468         }
 469     }
 470
 471 out:
 472     if (prev_p) {
 473         *prev_p = prev;
 474     }
 475     return next;
 476 }
 477
 478 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 479 {
 480     return pcie_find_capability_list(dev, cap_id, NULL);
 481 }
 482
 483 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 484 {
 485     uint16_t header = pci_get_long(dev->config + pos);
 486     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 487     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 488         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 489     pci_set_long(dev->config + pos, header);
 490 }
 491
 492 /*
 493  * caller must supply valid (offset, size) * such that the range shouldn't
 494  * overlap with other capability or other registers.
 495  * This function doesn't check it.
 496  */
 497 void pcie_add_capability(PCIDevice *dev,
 498                          uint16_t cap_id, uint8_t cap_ver,
 499                          uint16_t offset, uint16_t size)
 500 {
 501     uint32_t header;
 502     uint16_t next;
 503
 504     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 505     assert(offset < offset + size);
 506     assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 507     assert(size >= 8);
 508     assert(pci_is_express(dev));
 509
 510     if (offset == PCI_CONFIG_SPACE_SIZE) {
 511         header = pci_get_long(dev->config + offset);
 512         next = PCI_EXT_CAP_NEXT(header);
 513     } else {
 514         uint16_t prev;
 515
 516         /* 0 is reserved cap id. use internally to find the last capability
 517            in the linked list */
 518         next = pcie_find_capability_list(dev, 0, &prev);
 519
 520         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 521         assert(next == 0);
 522         pcie_ext_cap_set_next(dev, prev, offset);
 523     }
 524     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 525
 526     /* Make capability read-only by default */
 527     memset(dev->wmask + offset, 0, size);
 528     memset(dev->w1cmask + offset, 0, size);
 529     /* Check capability by default */
 530     memset(dev->cmask + offset, 0xFF, size);
 531 }
 532
 533 /**************************************************************************
 534  * pci express extended capability helper functions
 535  */
 536
 537 /* ARI */
 538 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 539 {
 540     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 541                         offset, PCI_ARI_SIZEOF);
 542     pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 543 }