hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/pc.h>
  27 #include <hw/pci.h>
  28 #include <hw/isa.h>
  29 #include "block.h"
  30 #include "dma.h"
  31
  32 #include <hw/ide/pci.h>
  33
  34 #define BMDMA_PAGE_SIZE 4096
  35
  36 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  37                             BlockDriverCompletionFunc *dma_cb)
  38 {
  39     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  40
  41     bm->unit = s->unit;
  42     bm->dma_cb = dma_cb;
  43     bm->cur_prd_last = 0;
  44     bm->cur_prd_addr = 0;
  45     bm->cur_prd_len = 0;
  46     bm->sector_num = ide_get_sector(s);
  47     bm->nsector = s->nsector;
  48
  49     if (bm->status & BM_STATUS_DMAING) {
  50         bm->dma_cb(bmdma_active_if(bm), 0);
  51     }
  52 }
  53
  54 /* return 0 if buffer completed */
  55 static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
  56 {
  57     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  58     IDEState *s = bmdma_active_if(bm);
  59     struct {
  60         uint32_t addr;
  61         uint32_t size;
  62     } prd;
  63     int l, len;
  64
  65     qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  66     s->io_buffer_size = 0;
  67     for(;;) {
  68         if (bm->cur_prd_len == 0) {
  69             /* end of table (with a fail safe of one page) */
  70             if (bm->cur_prd_last ||
  71                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
  72                 return s->io_buffer_size != 0;
  73             cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
  74             bm->cur_addr += 8;
  75             prd.addr = le32_to_cpu(prd.addr);
  76             prd.size = le32_to_cpu(prd.size);
  77             len = prd.size & 0xfffe;
  78             if (len == 0)
  79                 len = 0x10000;
  80             bm->cur_prd_len = len;
  81             bm->cur_prd_addr = prd.addr;
  82             bm->cur_prd_last = (prd.size & 0x80000000);
  83         }
  84         l = bm->cur_prd_len;
  85         if (l > 0) {
  86             qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
  87             bm->cur_prd_addr += l;
  88             bm->cur_prd_len -= l;
  89             s->io_buffer_size += l;
  90         }
  91     }
  92     return 1;
  93 }
  94
  95 /* return 0 if buffer completed */
  96 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
  97 {
  98     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  99     IDEState *s = bmdma_active_if(bm);
 100     struct {
 101         uint32_t addr;
 102         uint32_t size;
 103     } prd;
 104     int l, len;
 105
 106     for(;;) {
 107         l = s->io_buffer_size - s->io_buffer_index;
 108         if (l <= 0)
 109             break;
 110         if (bm->cur_prd_len == 0) {
 111             /* end of table (with a fail safe of one page) */
 112             if (bm->cur_prd_last ||
 113                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 114                 return 0;
 115             cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
 116             bm->cur_addr += 8;
 117             prd.addr = le32_to_cpu(prd.addr);
 118             prd.size = le32_to_cpu(prd.size);
 119             len = prd.size & 0xfffe;
 120             if (len == 0)
 121                 len = 0x10000;
 122             bm->cur_prd_len = len;
 123             bm->cur_prd_addr = prd.addr;
 124             bm->cur_prd_last = (prd.size & 0x80000000);
 125         }
 126         if (l > bm->cur_prd_len)
 127             l = bm->cur_prd_len;
 128         if (l > 0) {
 129             if (is_write) {
 130                 cpu_physical_memory_write(bm->cur_prd_addr,
 131                                           s->io_buffer + s->io_buffer_index, l);
 132             } else {
 133                 cpu_physical_memory_read(bm->cur_prd_addr,
 134                                           s->io_buffer + s->io_buffer_index, l);
 135             }
 136             bm->cur_prd_addr += l;
 137             bm->cur_prd_len -= l;
 138             s->io_buffer_index += l;
 139         }
 140     }
 141     return 1;
 142 }
 143
 144 static int bmdma_set_unit(IDEDMA *dma, int unit)
 145 {
 146     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 147     bm->unit = unit;
 148
 149     return 0;
 150 }
 151
 152 static int bmdma_add_status(IDEDMA *dma, int status)
 153 {
 154     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 155     bm->status |= status;
 156
 157     return 0;
 158 }
 159
 160 static int bmdma_set_inactive(IDEDMA *dma)
 161 {
 162     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 163
 164     bm->status &= ~BM_STATUS_DMAING;
 165     bm->dma_cb = NULL;
 166     bm->unit = -1;
 167
 168     return 0;
 169 }
 170
 171 static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
 172 {
 173     IDEState *s = bmdma_active_if(bm);
 174
 175     ide_set_sector(s, bm->sector_num);
 176     s->io_buffer_index = 0;
 177     s->io_buffer_size = 0;
 178     s->nsector = bm->nsector;
 179     s->dma_cmd = dma_cmd;
 180     bm->cur_addr = bm->addr;
 181     bm->dma_cb = ide_dma_cb;
 182     bmdma_start_dma(&bm->dma, s, bm->dma_cb);
 183 }
 184
 185 /* TODO This should be common IDE code */
 186 static void bmdma_restart_bh(void *opaque)
 187 {
 188     BMDMAState *bm = opaque;
 189     IDEBus *bus = bm->bus;
 190     int is_read;
 191     int error_status;
 192
 193     qemu_bh_delete(bm->bh);
 194     bm->bh = NULL;
 195
 196     if (bm->unit == (uint8_t) -1) {
 197         return;
 198     }
 199
 200     is_read = !!(bus->error_status & BM_STATUS_RETRY_READ);
 201
 202     /* The error status must be cleared before resubmitting the request: The
 203      * request may fail again, and this case can only be distinguished if the
 204      * called function can set a new error status. */
 205     error_status = bus->error_status;
 206     bus->error_status = 0;
 207
 208     if (error_status & BM_STATUS_DMA_RETRY) {
 209         if (error_status & BM_STATUS_RETRY_TRIM) {
 210             bmdma_restart_dma(bm, IDE_DMA_TRIM);
 211         } else {
 212             bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
 213         }
 214     } else if (error_status & BM_STATUS_PIO_RETRY) {
 215         if (is_read) {
 216             ide_sector_read(bmdma_active_if(bm));
 217         } else {
 218             ide_sector_write(bmdma_active_if(bm));
 219         }
 220     } else if (error_status & BM_STATUS_RETRY_FLUSH) {
 221         ide_flush_cache(bmdma_active_if(bm));
 222     }
 223 }
 224
 225 static void bmdma_restart_cb(void *opaque, int running, RunState state)
 226 {
 227     IDEDMA *dma = opaque;
 228     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 229
 230     if (!running)
 231         return;
 232
 233     if (!bm->bh) {
 234         bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
 235         qemu_bh_schedule(bm->bh);
 236     }
 237 }
 238
 239 static void bmdma_cancel(BMDMAState *bm)
 240 {
 241     if (bm->status & BM_STATUS_DMAING) {
 242         /* cancel DMA request */
 243         bmdma_set_inactive(&bm->dma);
 244     }
 245 }
 246
 247 static int bmdma_reset(IDEDMA *dma)
 248 {
 249     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 250
 251 #ifdef DEBUG_IDE
 252     printf("ide: dma_reset\n");
 253 #endif
 254     bmdma_cancel(bm);
 255     bm->cmd = 0;
 256     bm->status = 0;
 257     bm->addr = 0;
 258     bm->cur_addr = 0;
 259     bm->cur_prd_last = 0;
 260     bm->cur_prd_addr = 0;
 261     bm->cur_prd_len = 0;
 262     bm->sector_num = 0;
 263     bm->nsector = 0;
 264
 265     return 0;
 266 }
 267
 268 static int bmdma_start_transfer(IDEDMA *dma)
 269 {
 270     return 0;
 271 }
 272
 273 static void bmdma_irq(void *opaque, int n, int level)
 274 {
 275     BMDMAState *bm = opaque;
 276
 277     if (!level) {
 278         /* pass through lower */
 279         qemu_set_irq(bm->irq, level);
 280         return;
 281     }
 282
 283     bm->status |= BM_STATUS_INT;
 284
 285     /* trigger the real irq */
 286     qemu_set_irq(bm->irq, level);
 287 }
 288
 289 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 290 {
 291 #ifdef DEBUG_IDE
 292     printf("%s: 0x%08x\n", __func__, val);
 293 #endif
 294
 295     /* Ignore writes to SSBM if it keeps the old value */
 296     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 297         if (!(val & BM_CMD_START)) {
 298             /*
 299              * We can't cancel Scatter Gather DMA in the middle of the
 300              * operation or a partial (not full) DMA transfer would reach
 301              * the storage so we wait for completion instead (we beahve
 302              * like if the DMA was completed by the time the guest trying
 303              * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
 304              * set).
 305              *
 306              * In the future we'll be able to safely cancel the I/O if the
 307              * whole DMA operation will be submitted to disk with a single
 308              * aio operation with preadv/pwritev.
 309              */
 310             if (bm->bus->dma->aiocb) {
 311                 qemu_aio_flush();
 312                 assert(bm->bus->dma->aiocb == NULL);
 313                 assert((bm->status & BM_STATUS_DMAING) == 0);
 314             }
 315         } else {
 316             bm->cur_addr = bm->addr;
 317             if (!(bm->status & BM_STATUS_DMAING)) {
 318                 bm->status |= BM_STATUS_DMAING;
 319                 /* start dma transfer if possible */
 320                 if (bm->dma_cb)
 321                     bm->dma_cb(bmdma_active_if(bm), 0);
 322             }
 323         }
 324     }
 325
 326     bm->cmd = val & 0x09;
 327 }
 328
 329 static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
 330                                 unsigned width)
 331 {
 332     BMDMAState *bm = opaque;
 333     uint32_t mask = (1ULL << (width * 8)) - 1;
 334     uint64_t data;
 335
 336     data = (bm->addr >> (addr * 8)) & mask;
 337 #ifdef DEBUG_IDE
 338     printf("%s: 0x%08x\n", __func__, (unsigned)*data);
 339 #endif
 340     return data;
 341 }
 342
 343 static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
 344                              uint64_t data, unsigned width)
 345 {
 346     BMDMAState *bm = opaque;
 347     int shift = addr * 8;
 348     uint32_t mask = (1ULL << (width * 8)) - 1;
 349
 350 #ifdef DEBUG_IDE
 351     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 352 #endif
 353     bm->addr &= ~(mask << shift);
 354     bm->addr |= ((data & mask) << shift) & ~3;
 355 }
 356
 357 MemoryRegionOps bmdma_addr_ioport_ops = {
 358     .read = bmdma_addr_read,
 359     .write = bmdma_addr_write,
 360     .endianness = DEVICE_LITTLE_ENDIAN,
 361 };
 362
 363 static bool ide_bmdma_current_needed(void *opaque)
 364 {
 365     BMDMAState *bm = opaque;
 366
 367     return (bm->cur_prd_len != 0);
 368 }
 369
 370 static bool ide_bmdma_status_needed(void *opaque)
 371 {
 372     BMDMAState *bm = opaque;
 373
 374     /* Older versions abused some bits in the status register for internal
 375      * error state. If any of these bits are set, we must add a subsection to
 376      * transfer the real status register */
 377     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 378
 379     return ((bm->status & abused_bits) != 0);
 380 }
 381
 382 static void ide_bmdma_pre_save(void *opaque)
 383 {
 384     BMDMAState *bm = opaque;
 385     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 386
 387     bm->migration_compat_status =
 388         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 389 }
 390
 391 /* This function accesses bm->bus->error_status which is loaded only after
 392  * BMDMA itself. This is why the function is called from ide_pci_post_load
 393  * instead of being registered with VMState where it would run too early. */
 394 static int ide_bmdma_post_load(void *opaque, int version_id)
 395 {
 396     BMDMAState *bm = opaque;
 397     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 398
 399     if (bm->status == 0) {
 400         bm->status = bm->migration_compat_status & ~abused_bits;
 401         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 402     }
 403
 404     return 0;
 405 }
 406
 407 static const VMStateDescription vmstate_bmdma_current = {
 408     .name = "ide bmdma_current",
 409     .version_id = 1,
 410     .minimum_version_id = 1,
 411     .minimum_version_id_old = 1,
 412     .fields      = (VMStateField []) {
 413         VMSTATE_UINT32(cur_addr, BMDMAState),
 414         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 415         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 416         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 417         VMSTATE_END_OF_LIST()
 418     }
 419 };
 420
 421 const VMStateDescription vmstate_bmdma_status = {
 422     .name ="ide bmdma/status",
 423     .version_id = 1,
 424     .minimum_version_id = 1,
 425     .minimum_version_id_old = 1,
 426     .fields = (VMStateField []) {
 427         VMSTATE_UINT8(status, BMDMAState),
 428         VMSTATE_END_OF_LIST()
 429     }
 430 };
 431
 432 static const VMStateDescription vmstate_bmdma = {
 433     .name = "ide bmdma",
 434     .version_id = 3,
 435     .minimum_version_id = 0,
 436     .minimum_version_id_old = 0,
 437     .pre_save  = ide_bmdma_pre_save,
 438     .fields      = (VMStateField []) {
 439         VMSTATE_UINT8(cmd, BMDMAState),
 440         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 441         VMSTATE_UINT32(addr, BMDMAState),
 442         VMSTATE_INT64(sector_num, BMDMAState),
 443         VMSTATE_UINT32(nsector, BMDMAState),
 444         VMSTATE_UINT8(unit, BMDMAState),
 445         VMSTATE_END_OF_LIST()
 446     },
 447     .subsections = (VMStateSubsection []) {
 448         {
 449             .vmsd = &vmstate_bmdma_current,
 450             .needed = ide_bmdma_current_needed,
 451         }, {
 452             .vmsd = &vmstate_bmdma_status,
 453             .needed = ide_bmdma_status_needed,
 454         }, {
 455             /* empty */
 456         }
 457     }
 458 };
 459
 460 static int ide_pci_post_load(void *opaque, int version_id)
 461 {
 462     PCIIDEState *d = opaque;
 463     int i;
 464
 465     for(i = 0; i < 2; i++) {
 466         /* current versions always store 0/1, but older version
 467            stored bigger values. We only need last bit */
 468         d->bmdma[i].unit &= 1;
 469         ide_bmdma_post_load(&d->bmdma[i], -1);
 470     }
 471
 472     return 0;
 473 }
 474
 475 const VMStateDescription vmstate_ide_pci = {
 476     .name = "ide",
 477     .version_id = 3,
 478     .minimum_version_id = 0,
 479     .minimum_version_id_old = 0,
 480     .post_load = ide_pci_post_load,
 481     .fields      = (VMStateField []) {
 482         VMSTATE_PCI_DEVICE(dev, PCIIDEState),
 483         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 484                              vmstate_bmdma, BMDMAState),
 485         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 486         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 487         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 488         VMSTATE_END_OF_LIST()
 489     }
 490 };
 491
 492 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 493 {
 494     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
 495     static const int bus[4]  = { 0, 0, 1, 1 };
 496     static const int unit[4] = { 0, 1, 0, 1 };
 497     int i;
 498
 499     for (i = 0; i < 4; i++) {
 500         if (hd_table[i] == NULL)
 501             continue;
 502         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 503     }
 504 }
 505
 506 static const struct IDEDMAOps bmdma_ops = {
 507     .start_dma = bmdma_start_dma,
 508     .start_transfer = bmdma_start_transfer,
 509     .prepare_buf = bmdma_prepare_buf,
 510     .rw_buf = bmdma_rw_buf,
 511     .set_unit = bmdma_set_unit,
 512     .add_status = bmdma_add_status,
 513     .set_inactive = bmdma_set_inactive,
 514     .restart_cb = bmdma_restart_cb,
 515     .reset = bmdma_reset,
 516 };
 517
 518 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 519 {
 520     qemu_irq *irq;
 521
 522     if (bus->dma == &bm->dma) {
 523         return;
 524     }
 525
 526     bm->dma.ops = &bmdma_ops;
 527     bus->dma = &bm->dma;
 528     bm->irq = bus->irq;
 529     irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
 530     bus->irq = *irq;
 531     bm->pci_dev = d;
 532 }