2 * QEMU RTL8139 emulation
4 * Copyright (c) 2006 Igor Kovalenko
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
52 #include "qemu-timer.h"
56 /* debug RTL8139 card */
57 //#define DEBUG_RTL8139 1
59 #define PCI_FREQUENCY 33000000L
61 /* debug RTL8139 card C+ mode only */
62 //#define DEBUG_RTL8139CP 1
64 /* Calculate CRCs properly on Rx packets */
65 #define RTL8139_CALCULATE_RXCRC 1
67 #if defined(RTL8139_CALCULATE_RXCRC)
72 #define SET_MASKED(input, mask, curr) \
73 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
75 /* arg % size for size which is a power of 2 */
76 #define MOD2(input, size) \
77 ( ( input ) & ( size - 1 ) )
79 #if defined (DEBUG_RTL8139)
80 # define DEBUG_PRINT(x) do { printf x ; } while (0)
82 # define DEBUG_PRINT(x)
85 /* Symbolic offsets to registers. */
86 enum RTL8139_registers
{
87 MAC0
= 0, /* Ethernet hardware address. */
88 MAR0
= 8, /* Multicast filter. */
89 TxStatus0
= 0x10,/* Transmit status (Four 32bit registers). C mode only */
90 /* Dump Tally Conter control register(64bit). C+ mode only */
91 TxAddr0
= 0x20, /* Tx descriptors (also four 32bit). */
100 Timer
= 0x48, /* A general-purpose counter. */
101 RxMissed
= 0x4C, /* 24 bits valid, write clears. */
108 Config4
= 0x5A, /* absent on RTL-8139A */
111 PCIRevisionID
= 0x5E,
112 TxSummary
= 0x60, /* TSAD register. Transmit Status of All Descriptors*/
113 BasicModeCtrl
= 0x62,
114 BasicModeStatus
= 0x64,
117 NWayExpansion
= 0x6A,
118 /* Undocumented registers, but required for proper operation. */
119 FIFOTMS
= 0x70, /* FIFO Control and test. */
120 CSCR
= 0x74, /* Chip Status and Configuration Register. */
122 PARA7c
= 0x7c, /* Magic transceiver parameter register. */
123 Config5
= 0xD8, /* absent on RTL-8139A */
125 TxPoll
= 0xD9, /* Tell chip to check Tx descriptors for work */
126 RxMaxSize
= 0xDA, /* Max size of an Rx packet (8169 only) */
127 CpCmd
= 0xE0, /* C+ Command register (C+ mode only) */
128 IntrMitigate
= 0xE2, /* rx/tx interrupt mitigation control */
129 RxRingAddrLO
= 0xE4, /* 64-bit start addr of Rx ring */
130 RxRingAddrHI
= 0xE8, /* 64-bit start addr of Rx ring */
131 TxThresh
= 0xEC, /* Early Tx threshold */
135 MultiIntrClear
= 0xF000,
137 Config1Clear
= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
149 CPlusRxVLAN
= 0x0040, /* enable receive VLAN detagging */
150 CPlusRxChkSum
= 0x0020, /* enable receive checksum offloading */
155 /* Interrupt register bits, using my own meaningful names. */
156 enum IntrStatusBits
{
167 RxAckBits
= RxFIFOOver
| RxOverflow
| RxOK
,
174 TxOutOfWindow
= 0x20000000,
175 TxAborted
= 0x40000000,
176 TxCarrierLost
= 0x80000000,
179 RxMulticast
= 0x8000,
181 RxBroadcast
= 0x2000,
182 RxBadSymbol
= 0x0020,
190 /* Bits in RxConfig. */
194 AcceptBroadcast
= 0x08,
195 AcceptMulticast
= 0x04,
197 AcceptAllPhys
= 0x01,
200 /* Bits in TxConfig. */
201 enum tx_config_bits
{
203 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
205 TxIFG84
= (0 << TxIFGShift
), /* 8.4us / 840ns (10 / 100Mbps) */
206 TxIFG88
= (1 << TxIFGShift
), /* 8.8us / 880ns (10 / 100Mbps) */
207 TxIFG92
= (2 << TxIFGShift
), /* 9.2us / 920ns (10 / 100Mbps) */
208 TxIFG96
= (3 << TxIFGShift
), /* 9.6us / 960ns (10 / 100Mbps) */
210 TxLoopBack
= (1 << 18) | (1 << 17), /* enable loopback test mode */
211 TxCRC
= (1 << 16), /* DISABLE appending CRC to end of Tx packets */
212 TxClearAbt
= (1 << 0), /* Clear abort (WO) */
213 TxDMAShift
= 8, /* DMA burst value (0-7) is shifted this many bits */
214 TxRetryShift
= 4, /* TXRR value (0-15) is shifted this many bits */
216 TxVersionMask
= 0x7C800000, /* mask out version bits 30-26, 23 */
220 /* Transmit Status of All Descriptors (TSAD) Register */
222 TSAD_TOK3
= 1<<15, // TOK bit of Descriptor 3
223 TSAD_TOK2
= 1<<14, // TOK bit of Descriptor 2
224 TSAD_TOK1
= 1<<13, // TOK bit of Descriptor 1
225 TSAD_TOK0
= 1<<12, // TOK bit of Descriptor 0
226 TSAD_TUN3
= 1<<11, // TUN bit of Descriptor 3
227 TSAD_TUN2
= 1<<10, // TUN bit of Descriptor 2
228 TSAD_TUN1
= 1<<9, // TUN bit of Descriptor 1
229 TSAD_TUN0
= 1<<8, // TUN bit of Descriptor 0
230 TSAD_TABT3
= 1<<07, // TABT bit of Descriptor 3
231 TSAD_TABT2
= 1<<06, // TABT bit of Descriptor 2
232 TSAD_TABT1
= 1<<05, // TABT bit of Descriptor 1
233 TSAD_TABT0
= 1<<04, // TABT bit of Descriptor 0
234 TSAD_OWN3
= 1<<03, // OWN bit of Descriptor 3
235 TSAD_OWN2
= 1<<02, // OWN bit of Descriptor 2
236 TSAD_OWN1
= 1<<01, // OWN bit of Descriptor 1
237 TSAD_OWN0
= 1<<00, // OWN bit of Descriptor 0
241 /* Bits in Config1 */
243 Cfg1_PM_Enable
= 0x01,
244 Cfg1_VPD_Enable
= 0x02,
247 LWAKE
= 0x10, /* not on 8139, 8139A */
248 Cfg1_Driver_Load
= 0x20,
251 SLEEP
= (1 << 1), /* only on 8139, 8139A */
252 PWRDN
= (1 << 0), /* only on 8139, 8139A */
255 /* Bits in Config3 */
257 Cfg3_FBtBEn
= (1 << 0), /* 1 = Fast Back to Back */
258 Cfg3_FuncRegEn
= (1 << 1), /* 1 = enable CardBus Function registers */
259 Cfg3_CLKRUN_En
= (1 << 2), /* 1 = enable CLKRUN */
260 Cfg3_CardB_En
= (1 << 3), /* 1 = enable CardBus registers */
261 Cfg3_LinkUp
= (1 << 4), /* 1 = wake up on link up */
262 Cfg3_Magic
= (1 << 5), /* 1 = wake up on Magic Packet (tm) */
263 Cfg3_PARM_En
= (1 << 6), /* 0 = software can set twister parameters */
264 Cfg3_GNTSel
= (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
267 /* Bits in Config4 */
269 LWPTN
= (1 << 2), /* not on 8139, 8139A */
272 /* Bits in Config5 */
274 Cfg5_PME_STS
= (1 << 0), /* 1 = PCI reset resets PME_Status */
275 Cfg5_LANWake
= (1 << 1), /* 1 = enable LANWake signal */
276 Cfg5_LDPS
= (1 << 2), /* 0 = save power when link is down */
277 Cfg5_FIFOAddrPtr
= (1 << 3), /* Realtek internal SRAM testing */
278 Cfg5_UWF
= (1 << 4), /* 1 = accept unicast wakeup frame */
279 Cfg5_MWF
= (1 << 5), /* 1 = accept multicast wakeup frame */
280 Cfg5_BWF
= (1 << 6), /* 1 = accept broadcast wakeup frame */
284 /* rx fifo threshold */
286 RxCfgFIFONone
= (7 << RxCfgFIFOShift
),
290 RxCfgDMAUnlimited
= (7 << RxCfgDMAShift
),
292 /* rx ring buffer length */
294 RxCfgRcv16K
= (1 << 11),
295 RxCfgRcv32K
= (1 << 12),
296 RxCfgRcv64K
= (1 << 11) | (1 << 12),
298 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
302 /* Twister tuning parameters from RealTek.
303 Completely undocumented, but required to tune bad links on some boards. */
306 CSCR_LinkOKBit = 0x0400,
307 CSCR_LinkChangeBit = 0x0800,
308 CSCR_LinkStatusBits = 0x0f000,
309 CSCR_LinkDownOffCmd = 0x003c0,
310 CSCR_LinkDownCmd = 0x0f3c0,
313 CSCR_Testfun
= 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
314 CSCR_LD
= 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
315 CSCR_HEART_BIT
= 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
316 CSCR_JBEN
= 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
317 CSCR_F_LINK_100
= 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
318 CSCR_F_Connect
= 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
319 CSCR_Con_status
= 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
320 CSCR_Con_status_En
= 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
321 CSCR_PASS_SCR
= 1<<0, /* Bypass Scramble, def 0*/
326 Cfg9346_Unlock
= 0xC0,
343 HasHltClk
= (1 << 0),
347 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
348 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
349 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
351 #define RTL8139_PCI_REVID_8139 0x10
352 #define RTL8139_PCI_REVID_8139CPLUS 0x20
354 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
356 /* Size is 64 * 16bit words */
357 #define EEPROM_9346_ADDR_BITS 6
358 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
359 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
361 enum Chip9346Operation
363 Chip9346_op_mask
= 0xc0, /* 10 zzzzzz */
364 Chip9346_op_read
= 0x80, /* 10 AAAAAA */
365 Chip9346_op_write
= 0x40, /* 01 AAAAAA D(15)..D(0) */
366 Chip9346_op_ext_mask
= 0xf0, /* 11 zzzzzz */
367 Chip9346_op_write_enable
= 0x30, /* 00 11zzzz */
368 Chip9346_op_write_all
= 0x10, /* 00 01zzzz */
369 Chip9346_op_write_disable
= 0x00, /* 00 00zzzz */
375 Chip9346_enter_command_mode
,
376 Chip9346_read_command
,
377 Chip9346_data_read
, /* from output register */
378 Chip9346_data_write
, /* to input register, then to contents at specified address */
379 Chip9346_data_write_all
, /* to input register, then filling contents */
382 typedef struct EEprom9346
384 uint16_t contents
[EEPROM_9346_SIZE
];
397 typedef struct RTL8139TallyCounters
413 } RTL8139TallyCounters
;
415 /* Clears all tally counters */
416 static void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
);
418 /* Writes tally counters to specified physical memory address */
419 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* counters
);
421 typedef struct RTL8139State
{
423 uint8_t phys
[8]; /* mac address */
424 uint8_t mult
[8]; /* multicast mask array */
426 uint32_t TxStatus
[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
427 uint32_t TxAddr
[4]; /* TxAddr0 */
428 uint32_t RxBuf
; /* Receive buffer */
429 uint32_t RxBufferSize
;/* internal variable, receive ring buffer size in C mode */
449 uint8_t clock_enabled
;
450 uint8_t bChipCmdState
;
454 uint16_t BasicModeCtrl
;
455 uint16_t BasicModeStatus
;
458 uint16_t NWayExpansion
;
465 int rtl8139_mmio_io_addr
;
471 uint32_t cplus_enabled
;
473 uint32_t currCPlusRxDesc
;
474 uint32_t currCPlusTxDesc
;
476 uint32_t RxRingAddrLO
;
477 uint32_t RxRingAddrHI
;
486 RTL8139TallyCounters tally_counters
;
488 /* Non-persistent data */
489 uint8_t *cplus_txbuffer
;
490 int cplus_txbuffer_len
;
491 int cplus_txbuffer_offset
;
493 /* PCI interrupt timer */
499 static void rtl8139_set_next_tctr_time(RTL8139State
*s
, int64_t current_time
);
501 static void prom9346_decode_command(EEprom9346
*eeprom
, uint8_t command
)
503 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command
));
505 switch (command
& Chip9346_op_mask
)
507 case Chip9346_op_read
:
509 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
510 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
513 eeprom
->mode
= Chip9346_data_read
;
514 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
515 eeprom
->address
, eeprom
->output
));
519 case Chip9346_op_write
:
521 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
524 eeprom
->mode
= Chip9346_none
; /* Chip9346_data_write */
525 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
530 eeprom
->mode
= Chip9346_none
;
531 switch (command
& Chip9346_op_ext_mask
)
533 case Chip9346_op_write_enable
:
534 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
536 case Chip9346_op_write_all
:
537 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
539 case Chip9346_op_write_disable
:
540 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
547 static void prom9346_shift_clock(EEprom9346
*eeprom
)
549 int bit
= eeprom
->eedi
?1:0;
553 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom
->tick
, eeprom
->eedi
, eeprom
->eedo
));
555 switch (eeprom
->mode
)
557 case Chip9346_enter_command_mode
:
560 eeprom
->mode
= Chip9346_read_command
;
563 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
567 case Chip9346_read_command
:
568 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
569 if (eeprom
->tick
== 8)
571 prom9346_decode_command(eeprom
, eeprom
->input
& 0xff);
575 case Chip9346_data_read
:
576 eeprom
->eedo
= (eeprom
->output
& 0x8000)?1:0;
577 eeprom
->output
<<= 1;
578 if (eeprom
->tick
== 16)
581 // the FreeBSD drivers (rl and re) don't explicitly toggle
582 // CS between reads (or does setting Cfg9346 to 0 count too?),
583 // so we need to enter wait-for-command state here
584 eeprom
->mode
= Chip9346_enter_command_mode
;
588 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
590 // original behaviour
592 eeprom
->address
&= EEPROM_9346_ADDR_MASK
;
593 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
596 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
597 eeprom
->address
, eeprom
->output
));
602 case Chip9346_data_write
:
603 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
604 if (eeprom
->tick
== 16)
606 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
607 eeprom
->address
, eeprom
->input
));
609 eeprom
->contents
[eeprom
->address
] = eeprom
->input
;
610 eeprom
->mode
= Chip9346_none
; /* waiting for next command after CS cycle */
616 case Chip9346_data_write_all
:
617 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
618 if (eeprom
->tick
== 16)
621 for (i
= 0; i
< EEPROM_9346_SIZE
; i
++)
623 eeprom
->contents
[i
] = eeprom
->input
;
625 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
628 eeprom
->mode
= Chip9346_enter_command_mode
;
639 static int prom9346_get_wire(RTL8139State
*s
)
641 EEprom9346
*eeprom
= &s
->eeprom
;
648 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
649 static void prom9346_set_wire(RTL8139State
*s
, int eecs
, int eesk
, int eedi
)
651 EEprom9346
*eeprom
= &s
->eeprom
;
652 uint8_t old_eecs
= eeprom
->eecs
;
653 uint8_t old_eesk
= eeprom
->eesk
;
659 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
660 eeprom
->eecs
, eeprom
->eesk
, eeprom
->eedi
, eeprom
->eedo
));
662 if (!old_eecs
&& eecs
)
664 /* Synchronize start */
668 eeprom
->mode
= Chip9346_enter_command_mode
;
670 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
675 DEBUG_PRINT(("=== eeprom: end access\n"));
679 if (!old_eesk
&& eesk
)
682 prom9346_shift_clock(eeprom
);
686 static void rtl8139_update_irq(RTL8139State
*s
)
689 isr
= (s
->IntrStatus
& s
->IntrMask
) & 0xffff;
691 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
692 isr
? 1 : 0, s
->IntrStatus
, s
->IntrMask
));
694 qemu_set_irq(s
->dev
.irq
[0], (isr
!= 0));
697 #define POLYNOMIAL 0x04c11db6
701 static int compute_mcast_idx(const uint8_t *ep
)
708 for (i
= 0; i
< 6; i
++) {
710 for (j
= 0; j
< 8; j
++) {
711 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
715 crc
= ((crc
^ POLYNOMIAL
) | carry
);
721 static int rtl8139_RxWrap(RTL8139State
*s
)
723 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
724 return (s
->RxConfig
& (1 << 7));
727 static int rtl8139_receiver_enabled(RTL8139State
*s
)
729 return s
->bChipCmdState
& CmdRxEnb
;
732 static int rtl8139_transmitter_enabled(RTL8139State
*s
)
734 return s
->bChipCmdState
& CmdTxEnb
;
737 static int rtl8139_cp_receiver_enabled(RTL8139State
*s
)
739 return s
->CpCmd
& CPlusRxEnb
;
742 static int rtl8139_cp_transmitter_enabled(RTL8139State
*s
)
744 return s
->CpCmd
& CPlusTxEnb
;
747 static void rtl8139_write_buffer(RTL8139State
*s
, const void *buf
, int size
)
749 if (s
->RxBufAddr
+ size
> s
->RxBufferSize
)
751 int wrapped
= MOD2(s
->RxBufAddr
+ size
, s
->RxBufferSize
);
753 /* write packet data */
754 if (wrapped
&& !(s
->RxBufferSize
< 65536 && rtl8139_RxWrap(s
)))
756 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size
-wrapped
));
760 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
764 /* reset buffer pointer */
767 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
768 buf
+ (size
-wrapped
), wrapped
);
770 s
->RxBufAddr
= wrapped
;
776 /* non-wrapping path or overwrapping enabled */
777 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
, buf
, size
);
779 s
->RxBufAddr
+= size
;
782 #define MIN_BUF_SIZE 60
783 static inline target_phys_addr_t
rtl8139_addr64(uint32_t low
, uint32_t high
)
785 #if TARGET_PHYS_ADDR_BITS > 32
786 return low
| ((target_phys_addr_t
)high
<< 32);
792 static int rtl8139_can_receive(VLANClientState
*nc
)
794 RTL8139State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
797 /* Receive (drop) packets if card is disabled. */
798 if (!s
->clock_enabled
)
800 if (!rtl8139_receiver_enabled(s
))
803 if (rtl8139_cp_receiver_enabled(s
)) {
804 /* ??? Flow control not implemented in c+ mode.
805 This is a hack to work around slirp deficiencies anyway. */
808 avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
,
810 return (avail
== 0 || avail
>= 1514);
814 static ssize_t
rtl8139_do_receive(VLANClientState
*nc
, const uint8_t *buf
, size_t size_
, int do_interrupt
)
816 RTL8139State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
819 uint32_t packet_header
= 0;
822 static const uint8_t broadcast_macaddr
[6] =
823 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
825 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size
));
827 /* test if board clock is stopped */
828 if (!s
->clock_enabled
)
830 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
834 /* first check if receiver is enabled */
836 if (!rtl8139_receiver_enabled(s
))
838 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
842 /* XXX: check this */
843 if (s
->RxConfig
& AcceptAllPhys
) {
844 /* promiscuous: receive all */
845 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
848 if (!memcmp(buf
, broadcast_macaddr
, 6)) {
849 /* broadcast address */
850 if (!(s
->RxConfig
& AcceptBroadcast
))
852 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
854 /* update tally counter */
855 ++s
->tally_counters
.RxERR
;
860 packet_header
|= RxBroadcast
;
862 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
864 /* update tally counter */
865 ++s
->tally_counters
.RxOkBrd
;
867 } else if (buf
[0] & 0x01) {
869 if (!(s
->RxConfig
& AcceptMulticast
))
871 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
873 /* update tally counter */
874 ++s
->tally_counters
.RxERR
;
879 int mcast_idx
= compute_mcast_idx(buf
);
881 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))))
883 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
885 /* update tally counter */
886 ++s
->tally_counters
.RxERR
;
891 packet_header
|= RxMulticast
;
893 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
895 /* update tally counter */
896 ++s
->tally_counters
.RxOkMul
;
898 } else if (s
->phys
[0] == buf
[0] &&
899 s
->phys
[1] == buf
[1] &&
900 s
->phys
[2] == buf
[2] &&
901 s
->phys
[3] == buf
[3] &&
902 s
->phys
[4] == buf
[4] &&
903 s
->phys
[5] == buf
[5]) {
905 if (!(s
->RxConfig
& AcceptMyPhys
))
907 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
909 /* update tally counter */
910 ++s
->tally_counters
.RxERR
;
915 packet_header
|= RxPhysical
;
917 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
919 /* update tally counter */
920 ++s
->tally_counters
.RxOkPhy
;
924 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
926 /* update tally counter */
927 ++s
->tally_counters
.RxERR
;
933 /* if too small buffer, then expand it */
934 if (size
< MIN_BUF_SIZE
) {
935 memcpy(buf1
, buf
, size
);
936 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
941 if (rtl8139_cp_receiver_enabled(s
))
943 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
945 /* begin C+ receiver mode */
947 /* w0 ownership flag */
948 #define CP_RX_OWN (1<<31)
949 /* w0 end of ring flag */
950 #define CP_RX_EOR (1<<30)
951 /* w0 bits 0...12 : buffer size */
952 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
953 /* w1 tag available flag */
954 #define CP_RX_TAVA (1<<16)
955 /* w1 bits 0...15 : VLAN tag */
956 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
957 /* w2 low 32bit of Rx buffer ptr */
958 /* w3 high 32bit of Rx buffer ptr */
960 int descriptor
= s
->currCPlusRxDesc
;
961 target_phys_addr_t cplus_rx_ring_desc
;
963 cplus_rx_ring_desc
= rtl8139_addr64(s
->RxRingAddrLO
, s
->RxRingAddrHI
);
964 cplus_rx_ring_desc
+= 16 * descriptor
;
966 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64
"\n",
967 descriptor
, s
->RxRingAddrHI
, s
->RxRingAddrLO
, (uint64_t)cplus_rx_ring_desc
));
969 uint32_t val
, rxdw0
,rxdw1
,rxbufLO
,rxbufHI
;
971 cpu_physical_memory_read(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
972 rxdw0
= le32_to_cpu(val
);
973 cpu_physical_memory_read(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
974 rxdw1
= le32_to_cpu(val
);
975 cpu_physical_memory_read(cplus_rx_ring_desc
+8, (uint8_t *)&val
, 4);
976 rxbufLO
= le32_to_cpu(val
);
977 cpu_physical_memory_read(cplus_rx_ring_desc
+12, (uint8_t *)&val
, 4);
978 rxbufHI
= le32_to_cpu(val
);
980 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
982 rxdw0
, rxdw1
, rxbufLO
, rxbufHI
));
984 if (!(rxdw0
& CP_RX_OWN
))
986 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor
));
988 s
->IntrStatus
|= RxOverflow
;
991 /* update tally counter */
992 ++s
->tally_counters
.RxERR
;
993 ++s
->tally_counters
.MissPkt
;
995 rtl8139_update_irq(s
);
999 uint32_t rx_space
= rxdw0
& CP_RX_BUFFER_SIZE_MASK
;
1001 /* TODO: scatter the packet over available receive ring descriptors space */
1003 if (size
+4 > rx_space
)
1005 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1006 descriptor
, rx_space
, size
));
1008 s
->IntrStatus
|= RxOverflow
;
1011 /* update tally counter */
1012 ++s
->tally_counters
.RxERR
;
1013 ++s
->tally_counters
.MissPkt
;
1015 rtl8139_update_irq(s
);
1019 target_phys_addr_t rx_addr
= rtl8139_addr64(rxbufLO
, rxbufHI
);
1021 /* receive/copy to target memory */
1022 cpu_physical_memory_write( rx_addr
, buf
, size
);
1024 if (s
->CpCmd
& CPlusRxChkSum
)
1026 /* do some packet checksumming */
1029 /* write checksum */
1030 #if defined (RTL8139_CALCULATE_RXCRC)
1031 val
= cpu_to_le32(crc32(0, buf
, size
));
1035 cpu_physical_memory_write( rx_addr
+size
, (uint8_t *)&val
, 4);
1037 /* first segment of received packet flag */
1038 #define CP_RX_STATUS_FS (1<<29)
1039 /* last segment of received packet flag */
1040 #define CP_RX_STATUS_LS (1<<28)
1041 /* multicast packet flag */
1042 #define CP_RX_STATUS_MAR (1<<26)
1043 /* physical-matching packet flag */
1044 #define CP_RX_STATUS_PAM (1<<25)
1045 /* broadcast packet flag */
1046 #define CP_RX_STATUS_BAR (1<<24)
1047 /* runt packet flag */
1048 #define CP_RX_STATUS_RUNT (1<<19)
1049 /* crc error flag */
1050 #define CP_RX_STATUS_CRC (1<<18)
1051 /* IP checksum error flag */
1052 #define CP_RX_STATUS_IPF (1<<15)
1053 /* UDP checksum error flag */
1054 #define CP_RX_STATUS_UDPF (1<<14)
1055 /* TCP checksum error flag */
1056 #define CP_RX_STATUS_TCPF (1<<13)
1058 /* transfer ownership to target */
1059 rxdw0
&= ~CP_RX_OWN
;
1061 /* set first segment bit */
1062 rxdw0
|= CP_RX_STATUS_FS
;
1064 /* set last segment bit */
1065 rxdw0
|= CP_RX_STATUS_LS
;
1067 /* set received packet type flags */
1068 if (packet_header
& RxBroadcast
)
1069 rxdw0
|= CP_RX_STATUS_BAR
;
1070 if (packet_header
& RxMulticast
)
1071 rxdw0
|= CP_RX_STATUS_MAR
;
1072 if (packet_header
& RxPhysical
)
1073 rxdw0
|= CP_RX_STATUS_PAM
;
1075 /* set received size */
1076 rxdw0
&= ~CP_RX_BUFFER_SIZE_MASK
;
1079 /* reset VLAN tag flag */
1080 rxdw1
&= ~CP_RX_TAVA
;
1082 /* update ring data */
1083 val
= cpu_to_le32(rxdw0
);
1084 cpu_physical_memory_write(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
1085 val
= cpu_to_le32(rxdw1
);
1086 cpu_physical_memory_write(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
1088 /* update tally counter */
1089 ++s
->tally_counters
.RxOk
;
1091 /* seek to next Rx descriptor */
1092 if (rxdw0
& CP_RX_EOR
)
1094 s
->currCPlusRxDesc
= 0;
1098 ++s
->currCPlusRxDesc
;
1101 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1106 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1108 /* begin ring receiver mode */
1109 int avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
, s
->RxBufferSize
);
1111 /* if receiver buffer is empty then avail == 0 */
1113 if (avail
!= 0 && size
+ 8 >= avail
)
1115 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1116 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
, avail
, size
+ 8));
1118 s
->IntrStatus
|= RxOverflow
;
1120 rtl8139_update_irq(s
);
1124 packet_header
|= RxStatusOK
;
1126 packet_header
|= (((size
+4) << 16) & 0xffff0000);
1129 uint32_t val
= cpu_to_le32(packet_header
);
1131 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1133 rtl8139_write_buffer(s
, buf
, size
);
1135 /* write checksum */
1136 #if defined (RTL8139_CALCULATE_RXCRC)
1137 val
= cpu_to_le32(crc32(0, buf
, size
));
1142 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1144 /* correct buffer write pointer */
1145 s
->RxBufAddr
= MOD2((s
->RxBufAddr
+ 3) & ~0x3, s
->RxBufferSize
);
1147 /* now we can signal we have received something */
1149 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1150 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
1153 s
->IntrStatus
|= RxOK
;
1157 rtl8139_update_irq(s
);
1163 static ssize_t
rtl8139_receive(VLANClientState
*nc
, const uint8_t *buf
, size_t size
)
1165 return rtl8139_do_receive(nc
, buf
, size
, 1);
1168 static void rtl8139_reset_rxring(RTL8139State
*s
, uint32_t bufferSize
)
1170 s
->RxBufferSize
= bufferSize
;
1175 static void rtl8139_reset(DeviceState
*d
)
1177 RTL8139State
*s
= container_of(d
, RTL8139State
, dev
.qdev
);
1180 /* restore MAC address */
1181 memcpy(s
->phys
, s
->conf
.macaddr
.a
, 6);
1183 /* reset interrupt mask */
1187 rtl8139_update_irq(s
);
1189 /* prepare eeprom */
1190 s
->eeprom
.contents
[0] = 0x8129;
1192 // PCI vendor and device ID should be mirrored here
1193 s
->eeprom
.contents
[1] = PCI_VENDOR_ID_REALTEK
;
1194 s
->eeprom
.contents
[2] = PCI_DEVICE_ID_REALTEK_8139
;
1197 s
->eeprom
.contents
[7] = s
->conf
.macaddr
.a
[0] | s
->conf
.macaddr
.a
[1] << 8;
1198 s
->eeprom
.contents
[8] = s
->conf
.macaddr
.a
[2] | s
->conf
.macaddr
.a
[3] << 8;
1199 s
->eeprom
.contents
[9] = s
->conf
.macaddr
.a
[4] | s
->conf
.macaddr
.a
[5] << 8;
1201 /* mark all status registers as owned by host */
1202 for (i
= 0; i
< 4; ++i
)
1204 s
->TxStatus
[i
] = TxHostOwns
;
1208 s
->currCPlusRxDesc
= 0;
1209 s
->currCPlusTxDesc
= 0;
1211 s
->RxRingAddrLO
= 0;
1212 s
->RxRingAddrHI
= 0;
1216 rtl8139_reset_rxring(s
, 8192);
1222 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1223 s
->clock_enabled
= 0;
1225 s
->TxConfig
|= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1226 s
->clock_enabled
= 1;
1229 s
->bChipCmdState
= CmdReset
; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1231 /* set initial state data */
1232 s
->Config0
= 0x0; /* No boot ROM */
1233 s
->Config1
= 0xC; /* IO mapped and MEM mapped registers available */
1234 s
->Config3
= 0x1; /* fast back-to-back compatible */
1237 s
->CSCR
= CSCR_F_LINK_100
| CSCR_HEART_BIT
| CSCR_LD
;
1239 s
->CpCmd
= 0x0; /* reset C+ mode */
1240 s
->cplus_enabled
= 0;
1243 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1244 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1245 s
->BasicModeCtrl
= 0x1000; // autonegotiation
1247 s
->BasicModeStatus
= 0x7809;
1248 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1249 s
->BasicModeStatus
|= 0x0020; /* autonegotiation completed */
1250 s
->BasicModeStatus
|= 0x0004; /* link is up */
1252 s
->NWayAdvert
= 0x05e1; /* all modes, full duplex */
1253 s
->NWayLPAR
= 0x05e1; /* all modes, full duplex */
1254 s
->NWayExpansion
= 0x0001; /* autonegotiation supported */
1256 /* also reset timer and disable timer interrupt */
1261 /* reset tally counters */
1262 RTL8139TallyCounters_clear(&s
->tally_counters
);
1265 static void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
)
1269 counters
->TxERR
= 0;
1270 counters
->RxERR
= 0;
1271 counters
->MissPkt
= 0;
1273 counters
->Tx1Col
= 0;
1274 counters
->TxMCol
= 0;
1275 counters
->RxOkPhy
= 0;
1276 counters
->RxOkBrd
= 0;
1277 counters
->RxOkMul
= 0;
1278 counters
->TxAbt
= 0;
1279 counters
->TxUndrn
= 0;
1282 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* tally_counters
)
1288 val64
= cpu_to_le64(tally_counters
->TxOk
);
1289 cpu_physical_memory_write(tc_addr
+ 0, (uint8_t *)&val64
, 8);
1291 val64
= cpu_to_le64(tally_counters
->RxOk
);
1292 cpu_physical_memory_write(tc_addr
+ 8, (uint8_t *)&val64
, 8);
1294 val64
= cpu_to_le64(tally_counters
->TxERR
);
1295 cpu_physical_memory_write(tc_addr
+ 16, (uint8_t *)&val64
, 8);
1297 val32
= cpu_to_le32(tally_counters
->RxERR
);
1298 cpu_physical_memory_write(tc_addr
+ 24, (uint8_t *)&val32
, 4);
1300 val16
= cpu_to_le16(tally_counters
->MissPkt
);
1301 cpu_physical_memory_write(tc_addr
+ 28, (uint8_t *)&val16
, 2);
1303 val16
= cpu_to_le16(tally_counters
->FAE
);
1304 cpu_physical_memory_write(tc_addr
+ 30, (uint8_t *)&val16
, 2);
1306 val32
= cpu_to_le32(tally_counters
->Tx1Col
);
1307 cpu_physical_memory_write(tc_addr
+ 32, (uint8_t *)&val32
, 4);
1309 val32
= cpu_to_le32(tally_counters
->TxMCol
);
1310 cpu_physical_memory_write(tc_addr
+ 36, (uint8_t *)&val32
, 4);
1312 val64
= cpu_to_le64(tally_counters
->RxOkPhy
);
1313 cpu_physical_memory_write(tc_addr
+ 40, (uint8_t *)&val64
, 8);
1315 val64
= cpu_to_le64(tally_counters
->RxOkBrd
);
1316 cpu_physical_memory_write(tc_addr
+ 48, (uint8_t *)&val64
, 8);
1318 val32
= cpu_to_le32(tally_counters
->RxOkMul
);
1319 cpu_physical_memory_write(tc_addr
+ 56, (uint8_t *)&val32
, 4);
1321 val16
= cpu_to_le16(tally_counters
->TxAbt
);
1322 cpu_physical_memory_write(tc_addr
+ 60, (uint8_t *)&val16
, 2);
1324 val16
= cpu_to_le16(tally_counters
->TxUndrn
);
1325 cpu_physical_memory_write(tc_addr
+ 62, (uint8_t *)&val16
, 2);
1328 /* Loads values of tally counters from VM state file */
1330 static const VMStateDescription vmstate_tally_counters
= {
1331 .name
= "tally_counters",
1333 .minimum_version_id
= 1,
1334 .minimum_version_id_old
= 1,
1335 .fields
= (VMStateField
[]) {
1336 VMSTATE_UINT64(TxOk
, RTL8139TallyCounters
),
1337 VMSTATE_UINT64(RxOk
, RTL8139TallyCounters
),
1338 VMSTATE_UINT64(TxERR
, RTL8139TallyCounters
),
1339 VMSTATE_UINT32(RxERR
, RTL8139TallyCounters
),
1340 VMSTATE_UINT16(MissPkt
, RTL8139TallyCounters
),
1341 VMSTATE_UINT16(FAE
, RTL8139TallyCounters
),
1342 VMSTATE_UINT32(Tx1Col
, RTL8139TallyCounters
),
1343 VMSTATE_UINT32(TxMCol
, RTL8139TallyCounters
),
1344 VMSTATE_UINT64(RxOkPhy
, RTL8139TallyCounters
),
1345 VMSTATE_UINT64(RxOkBrd
, RTL8139TallyCounters
),
1346 VMSTATE_UINT16(TxAbt
, RTL8139TallyCounters
),
1347 VMSTATE_UINT16(TxUndrn
, RTL8139TallyCounters
),
1348 VMSTATE_END_OF_LIST()
1352 static void rtl8139_ChipCmd_write(RTL8139State
*s
, uint32_t val
)
1356 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val
));
1360 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1361 rtl8139_reset(&s
->dev
.qdev
);
1365 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1367 s
->currCPlusRxDesc
= 0;
1371 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1373 s
->currCPlusTxDesc
= 0;
1376 /* mask unwriteable bits */
1377 val
= SET_MASKED(val
, 0xe3, s
->bChipCmdState
);
1379 /* Deassert reset pin before next read */
1382 s
->bChipCmdState
= val
;
1385 static int rtl8139_RxBufferEmpty(RTL8139State
*s
)
1387 int unread
= MOD2(s
->RxBufferSize
+ s
->RxBufAddr
- s
->RxBufPtr
, s
->RxBufferSize
);
1391 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread
));
1395 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1400 static uint32_t rtl8139_ChipCmd_read(RTL8139State
*s
)
1402 uint32_t ret
= s
->bChipCmdState
;
1404 if (rtl8139_RxBufferEmpty(s
))
1407 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret
));
1412 static void rtl8139_CpCmd_write(RTL8139State
*s
, uint32_t val
)
1416 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val
));
1418 s
->cplus_enabled
= 1;
1420 /* mask unwriteable bits */
1421 val
= SET_MASKED(val
, 0xff84, s
->CpCmd
);
1426 static uint32_t rtl8139_CpCmd_read(RTL8139State
*s
)
1428 uint32_t ret
= s
->CpCmd
;
1430 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret
));
1435 static void rtl8139_IntrMitigate_write(RTL8139State
*s
, uint32_t val
)
1437 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val
));
1440 static uint32_t rtl8139_IntrMitigate_read(RTL8139State
*s
)
1444 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret
));
1449 static int rtl8139_config_writeable(RTL8139State
*s
)
1451 if (s
->Cfg9346
& Cfg9346_Unlock
)
1456 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1461 static void rtl8139_BasicModeCtrl_write(RTL8139State
*s
, uint32_t val
)
1465 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val
));
1467 /* mask unwriteable bits */
1468 uint32_t mask
= 0x4cff;
1470 if (1 || !rtl8139_config_writeable(s
))
1472 /* Speed setting and autonegotiation enable bits are read-only */
1474 /* Duplex mode setting is read-only */
1478 val
= SET_MASKED(val
, mask
, s
->BasicModeCtrl
);
1480 s
->BasicModeCtrl
= val
;
1483 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State
*s
)
1485 uint32_t ret
= s
->BasicModeCtrl
;
1487 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret
));
1492 static void rtl8139_BasicModeStatus_write(RTL8139State
*s
, uint32_t val
)
1496 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val
));
1498 /* mask unwriteable bits */
1499 val
= SET_MASKED(val
, 0xff3f, s
->BasicModeStatus
);
1501 s
->BasicModeStatus
= val
;
1504 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State
*s
)
1506 uint32_t ret
= s
->BasicModeStatus
;
1508 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret
));
1513 static void rtl8139_Cfg9346_write(RTL8139State
*s
, uint32_t val
)
1517 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val
));
1519 /* mask unwriteable bits */
1520 val
= SET_MASKED(val
, 0x31, s
->Cfg9346
);
1522 uint32_t opmode
= val
& 0xc0;
1523 uint32_t eeprom_val
= val
& 0xf;
1525 if (opmode
== 0x80) {
1527 int eecs
= (eeprom_val
& 0x08)?1:0;
1528 int eesk
= (eeprom_val
& 0x04)?1:0;
1529 int eedi
= (eeprom_val
& 0x02)?1:0;
1530 prom9346_set_wire(s
, eecs
, eesk
, eedi
);
1531 } else if (opmode
== 0x40) {
1534 rtl8139_reset(&s
->dev
.qdev
);
1540 static uint32_t rtl8139_Cfg9346_read(RTL8139State
*s
)
1542 uint32_t ret
= s
->Cfg9346
;
1544 uint32_t opmode
= ret
& 0xc0;
1549 int eedo
= prom9346_get_wire(s
);
1560 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret
));
1565 static void rtl8139_Config0_write(RTL8139State
*s
, uint32_t val
)
1569 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val
));
1571 if (!rtl8139_config_writeable(s
))
1574 /* mask unwriteable bits */
1575 val
= SET_MASKED(val
, 0xf8, s
->Config0
);
1580 static uint32_t rtl8139_Config0_read(RTL8139State
*s
)
1582 uint32_t ret
= s
->Config0
;
1584 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret
));
1589 static void rtl8139_Config1_write(RTL8139State
*s
, uint32_t val
)
1593 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val
));
1595 if (!rtl8139_config_writeable(s
))
1598 /* mask unwriteable bits */
1599 val
= SET_MASKED(val
, 0xC, s
->Config1
);
1604 static uint32_t rtl8139_Config1_read(RTL8139State
*s
)
1606 uint32_t ret
= s
->Config1
;
1608 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret
));
1613 static void rtl8139_Config3_write(RTL8139State
*s
, uint32_t val
)
1617 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val
));
1619 if (!rtl8139_config_writeable(s
))
1622 /* mask unwriteable bits */
1623 val
= SET_MASKED(val
, 0x8F, s
->Config3
);
1628 static uint32_t rtl8139_Config3_read(RTL8139State
*s
)
1630 uint32_t ret
= s
->Config3
;
1632 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret
));
1637 static void rtl8139_Config4_write(RTL8139State
*s
, uint32_t val
)
1641 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val
));
1643 if (!rtl8139_config_writeable(s
))
1646 /* mask unwriteable bits */
1647 val
= SET_MASKED(val
, 0x0a, s
->Config4
);
1652 static uint32_t rtl8139_Config4_read(RTL8139State
*s
)
1654 uint32_t ret
= s
->Config4
;
1656 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret
));
1661 static void rtl8139_Config5_write(RTL8139State
*s
, uint32_t val
)
1665 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val
));
1667 /* mask unwriteable bits */
1668 val
= SET_MASKED(val
, 0x80, s
->Config5
);
1673 static uint32_t rtl8139_Config5_read(RTL8139State
*s
)
1675 uint32_t ret
= s
->Config5
;
1677 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret
));
1682 static void rtl8139_TxConfig_write(RTL8139State
*s
, uint32_t val
)
1684 if (!rtl8139_transmitter_enabled(s
))
1686 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val
));
1690 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val
));
1692 val
= SET_MASKED(val
, TxVersionMask
| 0x8070f80f, s
->TxConfig
);
1697 static void rtl8139_TxConfig_writeb(RTL8139State
*s
, uint32_t val
)
1699 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val
));
1701 uint32_t tc
= s
->TxConfig
;
1703 tc
|= (val
& 0x000000FF);
1704 rtl8139_TxConfig_write(s
, tc
);
1707 static uint32_t rtl8139_TxConfig_read(RTL8139State
*s
)
1709 uint32_t ret
= s
->TxConfig
;
1711 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret
));
1716 static void rtl8139_RxConfig_write(RTL8139State
*s
, uint32_t val
)
1718 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val
));
1720 /* mask unwriteable bits */
1721 val
= SET_MASKED(val
, 0xf0fc0040, s
->RxConfig
);
1725 /* reset buffer size and read/write pointers */
1726 rtl8139_reset_rxring(s
, 8192 << ((s
->RxConfig
>> 11) & 0x3));
1728 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s
->RxBufferSize
));
1731 static uint32_t rtl8139_RxConfig_read(RTL8139State
*s
)
1733 uint32_t ret
= s
->RxConfig
;
1735 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret
));
1740 static void rtl8139_transfer_frame(RTL8139State
*s
, const uint8_t *buf
, int size
, int do_interrupt
)
1744 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1748 if (TxLoopBack
== (s
->TxConfig
& TxLoopBack
))
1750 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1751 rtl8139_do_receive(&s
->nic
->nc
, buf
, size
, do_interrupt
);
1755 qemu_send_packet(&s
->nic
->nc
, buf
, size
);
1759 static int rtl8139_transmit_one(RTL8139State
*s
, int descriptor
)
1761 if (!rtl8139_transmitter_enabled(s
))
1763 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1768 if (s
->TxStatus
[descriptor
] & TxHostOwns
)
1770 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1771 descriptor
, s
->TxStatus
[descriptor
]));
1775 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor
));
1777 int txsize
= s
->TxStatus
[descriptor
] & 0x1fff;
1778 uint8_t txbuffer
[0x2000];
1780 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1781 txsize
, s
->TxAddr
[descriptor
]));
1783 cpu_physical_memory_read(s
->TxAddr
[descriptor
], txbuffer
, txsize
);
1785 /* Mark descriptor as transferred */
1786 s
->TxStatus
[descriptor
] |= TxHostOwns
;
1787 s
->TxStatus
[descriptor
] |= TxStatOK
;
1789 rtl8139_transfer_frame(s
, txbuffer
, txsize
, 0);
1791 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize
, descriptor
));
1793 /* update interrupt */
1794 s
->IntrStatus
|= TxOK
;
1795 rtl8139_update_irq(s
);
1800 /* structures and macros for task offloading */
1801 typedef struct ip_header
1803 uint8_t ip_ver_len
; /* version and header length */
1804 uint8_t ip_tos
; /* type of service */
1805 uint16_t ip_len
; /* total length */
1806 uint16_t ip_id
; /* identification */
1807 uint16_t ip_off
; /* fragment offset field */
1808 uint8_t ip_ttl
; /* time to live */
1809 uint8_t ip_p
; /* protocol */
1810 uint16_t ip_sum
; /* checksum */
1811 uint32_t ip_src
,ip_dst
; /* source and dest address */
1814 #define IP_HEADER_VERSION_4 4
1815 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1816 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1818 typedef struct tcp_header
1820 uint16_t th_sport
; /* source port */
1821 uint16_t th_dport
; /* destination port */
1822 uint32_t th_seq
; /* sequence number */
1823 uint32_t th_ack
; /* acknowledgement number */
1824 uint16_t th_offset_flags
; /* data offset, reserved 6 bits, TCP protocol flags */
1825 uint16_t th_win
; /* window */
1826 uint16_t th_sum
; /* checksum */
1827 uint16_t th_urp
; /* urgent pointer */
1830 typedef struct udp_header
1832 uint16_t uh_sport
; /* source port */
1833 uint16_t uh_dport
; /* destination port */
1834 uint16_t uh_ulen
; /* udp length */
1835 uint16_t uh_sum
; /* udp checksum */
1838 typedef struct ip_pseudo_header
1844 uint16_t ip_payload
;
1847 #define IP_PROTO_TCP 6
1848 #define IP_PROTO_UDP 17
1850 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1851 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1852 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1854 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1856 #define TCP_FLAG_FIN 0x01
1857 #define TCP_FLAG_PUSH 0x08
1859 /* produces ones' complement sum of data */
1860 static uint16_t ones_complement_sum(uint8_t *data
, size_t len
)
1862 uint32_t result
= 0;
1864 for (; len
> 1; data
+=2, len
-=2)
1866 result
+= *(uint16_t*)data
;
1869 /* add the remainder byte */
1872 uint8_t odd
[2] = {*data
, 0};
1873 result
+= *(uint16_t*)odd
;
1877 result
= (result
& 0xffff) + (result
>> 16);
1882 static uint16_t ip_checksum(void *data
, size_t len
)
1884 return ~ones_complement_sum((uint8_t*)data
, len
);
1887 static int rtl8139_cplus_transmit_one(RTL8139State
*s
)
1889 if (!rtl8139_transmitter_enabled(s
))
1891 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1895 if (!rtl8139_cp_transmitter_enabled(s
))
1897 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1901 int descriptor
= s
->currCPlusTxDesc
;
1903 target_phys_addr_t cplus_tx_ring_desc
=
1904 rtl8139_addr64(s
->TxAddr
[0], s
->TxAddr
[1]);
1906 /* Normal priority ring */
1907 cplus_tx_ring_desc
+= 16 * descriptor
;
1909 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1910 descriptor
, s
->TxAddr
[1], s
->TxAddr
[0], cplus_tx_ring_desc
));
1912 uint32_t val
, txdw0
,txdw1
,txbufLO
,txbufHI
;
1914 cpu_physical_memory_read(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
1915 txdw0
= le32_to_cpu(val
);
1916 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
1917 cpu_physical_memory_read(cplus_tx_ring_desc
+4, (uint8_t *)&val
, 4);
1918 txdw1
= le32_to_cpu(val
);
1919 cpu_physical_memory_read(cplus_tx_ring_desc
+8, (uint8_t *)&val
, 4);
1920 txbufLO
= le32_to_cpu(val
);
1921 cpu_physical_memory_read(cplus_tx_ring_desc
+12, (uint8_t *)&val
, 4);
1922 txbufHI
= le32_to_cpu(val
);
1924 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1926 txdw0
, txdw1
, txbufLO
, txbufHI
));
1928 /* TODO: the following discard cast should clean clang analyzer output */
1931 /* w0 ownership flag */
1932 #define CP_TX_OWN (1<<31)
1933 /* w0 end of ring flag */
1934 #define CP_TX_EOR (1<<30)
1935 /* first segment of received packet flag */
1936 #define CP_TX_FS (1<<29)
1937 /* last segment of received packet flag */
1938 #define CP_TX_LS (1<<28)
1939 /* large send packet flag */
1940 #define CP_TX_LGSEN (1<<27)
1941 /* large send MSS mask, bits 16...25 */
1942 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1944 /* IP checksum offload flag */
1945 #define CP_TX_IPCS (1<<18)
1946 /* UDP checksum offload flag */
1947 #define CP_TX_UDPCS (1<<17)
1948 /* TCP checksum offload flag */
1949 #define CP_TX_TCPCS (1<<16)
1951 /* w0 bits 0...15 : buffer size */
1952 #define CP_TX_BUFFER_SIZE (1<<16)
1953 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1954 /* w1 tag available flag */
1955 #define CP_RX_TAGC (1<<17)
1956 /* w1 bits 0...15 : VLAN tag */
1957 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1958 /* w2 low 32bit of Rx buffer ptr */
1959 /* w3 high 32bit of Rx buffer ptr */
1961 /* set after transmission */
1962 /* FIFO underrun flag */
1963 #define CP_TX_STATUS_UNF (1<<25)
1964 /* transmit error summary flag, valid if set any of three below */
1965 #define CP_TX_STATUS_TES (1<<23)
1966 /* out-of-window collision flag */
1967 #define CP_TX_STATUS_OWC (1<<22)
1968 /* link failure flag */
1969 #define CP_TX_STATUS_LNKF (1<<21)
1970 /* excessive collisions flag */
1971 #define CP_TX_STATUS_EXC (1<<20)
1973 if (!(txdw0
& CP_TX_OWN
))
1975 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor
));
1979 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor
));
1981 if (txdw0
& CP_TX_FS
)
1983 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor
));
1985 /* reset internal buffer offset */
1986 s
->cplus_txbuffer_offset
= 0;
1989 int txsize
= txdw0
& CP_TX_BUFFER_SIZE_MASK
;
1990 target_phys_addr_t tx_addr
= rtl8139_addr64(txbufLO
, txbufHI
);
1992 /* make sure we have enough space to assemble the packet */
1993 if (!s
->cplus_txbuffer
)
1995 s
->cplus_txbuffer_len
= CP_TX_BUFFER_SIZE
;
1996 s
->cplus_txbuffer
= qemu_malloc(s
->cplus_txbuffer_len
);
1997 s
->cplus_txbuffer_offset
= 0;
1999 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s
->cplus_txbuffer_len
));
2002 while (s
->cplus_txbuffer
&& s
->cplus_txbuffer_offset
+ txsize
>= s
->cplus_txbuffer_len
)
2004 s
->cplus_txbuffer_len
+= CP_TX_BUFFER_SIZE
;
2005 s
->cplus_txbuffer
= qemu_realloc(s
->cplus_txbuffer
, s
->cplus_txbuffer_len
);
2007 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s
->cplus_txbuffer_len
));
2010 if (!s
->cplus_txbuffer
)
2014 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s
->cplus_txbuffer_len
));
2016 /* update tally counter */
2017 ++s
->tally_counters
.TxERR
;
2018 ++s
->tally_counters
.TxAbt
;
2023 /* append more data to the packet */
2025 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64
" to offset %d\n",
2026 txsize
, (uint64_t)tx_addr
, s
->cplus_txbuffer_offset
));
2028 cpu_physical_memory_read(tx_addr
, s
->cplus_txbuffer
+ s
->cplus_txbuffer_offset
, txsize
);
2029 s
->cplus_txbuffer_offset
+= txsize
;
2031 /* seek to next Rx descriptor */
2032 if (txdw0
& CP_TX_EOR
)
2034 s
->currCPlusTxDesc
= 0;
2038 ++s
->currCPlusTxDesc
;
2039 if (s
->currCPlusTxDesc
>= 64)
2040 s
->currCPlusTxDesc
= 0;
2043 /* transfer ownership to target */
2044 txdw0
&= ~CP_RX_OWN
;
2046 /* reset error indicator bits */
2047 txdw0
&= ~CP_TX_STATUS_UNF
;
2048 txdw0
&= ~CP_TX_STATUS_TES
;
2049 txdw0
&= ~CP_TX_STATUS_OWC
;
2050 txdw0
&= ~CP_TX_STATUS_LNKF
;
2051 txdw0
&= ~CP_TX_STATUS_EXC
;
2053 /* update ring data */
2054 val
= cpu_to_le32(txdw0
);
2055 cpu_physical_memory_write(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
2056 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
2057 // val = cpu_to_le32(txdw1);
2058 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2060 /* Now decide if descriptor being processed is holding the last segment of packet */
2061 if (txdw0
& CP_TX_LS
)
2063 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor
));
2065 /* can transfer fully assembled packet */
2067 uint8_t *saved_buffer
= s
->cplus_txbuffer
;
2068 int saved_size
= s
->cplus_txbuffer_offset
;
2069 int saved_buffer_len
= s
->cplus_txbuffer_len
;
2071 /* reset the card space to protect from recursive call */
2072 s
->cplus_txbuffer
= NULL
;
2073 s
->cplus_txbuffer_offset
= 0;
2074 s
->cplus_txbuffer_len
= 0;
2076 if (txdw0
& (CP_TX_IPCS
| CP_TX_UDPCS
| CP_TX_TCPCS
| CP_TX_LGSEN
))
2078 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2080 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2082 #define ETH_MTU 1500
2084 /* ip packet header */
2085 ip_header
*ip
= NULL
;
2087 uint8_t ip_protocol
= 0;
2088 uint16_t ip_data_len
= 0;
2090 uint8_t *eth_payload_data
= NULL
;
2091 size_t eth_payload_len
= 0;
2093 int proto
= be16_to_cpu(*(uint16_t *)(saved_buffer
+ 12));
2094 if (proto
== ETH_P_IP
)
2096 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2099 eth_payload_data
= saved_buffer
+ ETH_HLEN
;
2100 eth_payload_len
= saved_size
- ETH_HLEN
;
2102 ip
= (ip_header
*)eth_payload_data
;
2104 if (IP_HEADER_VERSION(ip
) != IP_HEADER_VERSION_4
) {
2105 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip
), IP_HEADER_VERSION_4
));
2108 hlen
= IP_HEADER_LENGTH(ip
);
2109 ip_protocol
= ip
->ip_p
;
2110 ip_data_len
= be16_to_cpu(ip
->ip_len
) - hlen
;
2116 if (txdw0
& CP_TX_IPCS
)
2118 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2120 if (hlen
<sizeof(ip_header
) || hlen
>eth_payload_len
) {/* min header length */
2121 /* bad packet header len */
2122 /* or packet too short */
2127 ip
->ip_sum
= ip_checksum(ip
, hlen
);
2128 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2132 if ((txdw0
& CP_TX_LGSEN
) && ip_protocol
== IP_PROTO_TCP
)
2134 #if defined (DEBUG_RTL8139)
2135 int large_send_mss
= (txdw0
>> 16) & CP_TC_LGSEN_MSS_MASK
;
2137 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2138 ETH_MTU
, ip_data_len
, saved_size
- ETH_HLEN
, large_send_mss
));
2140 int tcp_send_offset
= 0;
2143 /* maximum IP header length is 60 bytes */
2144 uint8_t saved_ip_header
[60];
2146 /* save IP header template; data area is used in tcp checksum calculation */
2147 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2149 /* a placeholder for checksum calculation routine in tcp case */
2150 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2151 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2153 /* pointer to TCP header */
2154 tcp_header
*p_tcp_hdr
= (tcp_header
*)(eth_payload_data
+ hlen
);
2156 int tcp_hlen
= TCP_HEADER_DATA_OFFSET(p_tcp_hdr
);
2158 /* ETH_MTU = ip header len + tcp header len + payload */
2159 int tcp_data_len
= ip_data_len
- tcp_hlen
;
2160 int tcp_chunk_size
= ETH_MTU
- hlen
- tcp_hlen
;
2162 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2163 ip_data_len
, tcp_hlen
, tcp_data_len
, tcp_chunk_size
));
2165 /* note the cycle below overwrites IP header data,
2166 but restores it from saved_ip_header before sending packet */
2168 int is_last_frame
= 0;
2170 for (tcp_send_offset
= 0; tcp_send_offset
< tcp_data_len
; tcp_send_offset
+= tcp_chunk_size
)
2172 uint16_t chunk_size
= tcp_chunk_size
;
2174 /* check if this is the last frame */
2175 if (tcp_send_offset
+ tcp_chunk_size
>= tcp_data_len
)
2178 chunk_size
= tcp_data_len
- tcp_send_offset
;
2181 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr
->th_seq
)));
2183 /* add 4 TCP pseudoheader fields */
2184 /* copy IP source and destination fields */
2185 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2187 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen
+ chunk_size
));
2189 if (tcp_send_offset
)
2191 memcpy((uint8_t*)p_tcp_hdr
+ tcp_hlen
, (uint8_t*)p_tcp_hdr
+ tcp_hlen
+ tcp_send_offset
, chunk_size
);
2194 /* keep PUSH and FIN flags only for the last frame */
2197 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr
, TCP_FLAG_PUSH
|TCP_FLAG_FIN
);
2200 /* recalculate TCP checksum */
2201 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2202 p_tcpip_hdr
->zeros
= 0;
2203 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2204 p_tcpip_hdr
->ip_payload
= cpu_to_be16(tcp_hlen
+ chunk_size
);
2206 p_tcp_hdr
->th_sum
= 0;
2208 int tcp_checksum
= ip_checksum(data_to_checksum
, tcp_hlen
+ chunk_size
+ 12);
2209 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum
));
2211 p_tcp_hdr
->th_sum
= tcp_checksum
;
2213 /* restore IP header */
2214 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2216 /* set IP data length and recalculate IP checksum */
2217 ip
->ip_len
= cpu_to_be16(hlen
+ tcp_hlen
+ chunk_size
);
2219 /* increment IP id for subsequent frames */
2220 ip
->ip_id
= cpu_to_be16(tcp_send_offset
/tcp_chunk_size
+ be16_to_cpu(ip
->ip_id
));
2223 ip
->ip_sum
= ip_checksum(eth_payload_data
, hlen
);
2224 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2226 int tso_send_size
= ETH_HLEN
+ hlen
+ tcp_hlen
+ chunk_size
;
2227 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size
));
2228 rtl8139_transfer_frame(s
, saved_buffer
, tso_send_size
, 0);
2230 /* add transferred count to TCP sequence number */
2231 p_tcp_hdr
->th_seq
= cpu_to_be32(chunk_size
+ be32_to_cpu(p_tcp_hdr
->th_seq
));
2235 /* Stop sending this frame */
2238 else if (txdw0
& (CP_TX_TCPCS
|CP_TX_UDPCS
))
2240 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2242 /* maximum IP header length is 60 bytes */
2243 uint8_t saved_ip_header
[60];
2244 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2246 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2247 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2249 /* add 4 TCP pseudoheader fields */
2250 /* copy IP source and destination fields */
2251 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2253 if ((txdw0
& CP_TX_TCPCS
) && ip_protocol
== IP_PROTO_TCP
)
2255 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len
));
2257 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2258 p_tcpip_hdr
->zeros
= 0;
2259 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2260 p_tcpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2262 tcp_header
* p_tcp_hdr
= (tcp_header
*) (data_to_checksum
+12);
2264 p_tcp_hdr
->th_sum
= 0;
2266 int tcp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2267 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum
));
2269 p_tcp_hdr
->th_sum
= tcp_checksum
;
2271 else if ((txdw0
& CP_TX_UDPCS
) && ip_protocol
== IP_PROTO_UDP
)
2273 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len
));
2275 ip_pseudo_header
*p_udpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2276 p_udpip_hdr
->zeros
= 0;
2277 p_udpip_hdr
->ip_proto
= IP_PROTO_UDP
;
2278 p_udpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2280 udp_header
*p_udp_hdr
= (udp_header
*) (data_to_checksum
+12);
2282 p_udp_hdr
->uh_sum
= 0;
2284 int udp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2285 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum
));
2287 p_udp_hdr
->uh_sum
= udp_checksum
;
2290 /* restore IP header */
2291 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2296 /* update tally counter */
2297 ++s
->tally_counters
.TxOk
;
2299 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size
));
2301 rtl8139_transfer_frame(s
, saved_buffer
, saved_size
, 1);
2303 /* restore card space if there was no recursion and reset offset */
2304 if (!s
->cplus_txbuffer
)
2306 s
->cplus_txbuffer
= saved_buffer
;
2307 s
->cplus_txbuffer_len
= saved_buffer_len
;
2308 s
->cplus_txbuffer_offset
= 0;
2312 qemu_free(saved_buffer
);
2317 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2323 static void rtl8139_cplus_transmit(RTL8139State
*s
)
2327 while (rtl8139_cplus_transmit_one(s
))
2332 /* Mark transfer completed */
2335 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2336 s
->currCPlusTxDesc
));
2340 /* update interrupt status */
2341 s
->IntrStatus
|= TxOK
;
2342 rtl8139_update_irq(s
);
2346 static void rtl8139_transmit(RTL8139State
*s
)
2348 int descriptor
= s
->currTxDesc
, txcount
= 0;
2351 if (rtl8139_transmit_one(s
, descriptor
))
2358 /* Mark transfer completed */
2361 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s
->currTxDesc
));
2365 static void rtl8139_TxStatus_write(RTL8139State
*s
, uint32_t txRegOffset
, uint32_t val
)
2368 int descriptor
= txRegOffset
/4;
2370 /* handle C+ transmit mode register configuration */
2372 if (s
->cplus_enabled
)
2374 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2376 /* handle Dump Tally Counters command */
2377 s
->TxStatus
[descriptor
] = val
;
2379 if (descriptor
== 0 && (val
& 0x8))
2381 target_phys_addr_t tc_addr
= rtl8139_addr64(s
->TxStatus
[0] & ~0x3f, s
->TxStatus
[1]);
2383 /* dump tally counters to specified memory location */
2384 RTL8139TallyCounters_physical_memory_write( tc_addr
, &s
->tally_counters
);
2386 /* mark dump completed */
2387 s
->TxStatus
[0] &= ~0x8;
2393 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2395 /* mask only reserved bits */
2396 val
&= ~0xff00c000; /* these bits are reset on write */
2397 val
= SET_MASKED(val
, 0x00c00000, s
->TxStatus
[descriptor
]);
2399 s
->TxStatus
[descriptor
] = val
;
2401 /* attempt to start transmission */
2402 rtl8139_transmit(s
);
2405 static uint32_t rtl8139_TxStatus_read(RTL8139State
*s
, uint32_t txRegOffset
)
2407 uint32_t ret
= s
->TxStatus
[txRegOffset
/4];
2409 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset
, ret
));
2414 static uint16_t rtl8139_TSAD_read(RTL8139State
*s
)
2418 /* Simulate TSAD, it is read only anyway */
2420 ret
= ((s
->TxStatus
[3] & TxStatOK
)?TSAD_TOK3
:0)
2421 |((s
->TxStatus
[2] & TxStatOK
)?TSAD_TOK2
:0)
2422 |((s
->TxStatus
[1] & TxStatOK
)?TSAD_TOK1
:0)
2423 |((s
->TxStatus
[0] & TxStatOK
)?TSAD_TOK0
:0)
2425 |((s
->TxStatus
[3] & TxUnderrun
)?TSAD_TUN3
:0)
2426 |((s
->TxStatus
[2] & TxUnderrun
)?TSAD_TUN2
:0)
2427 |((s
->TxStatus
[1] & TxUnderrun
)?TSAD_TUN1
:0)
2428 |((s
->TxStatus
[0] & TxUnderrun
)?TSAD_TUN0
:0)
2430 |((s
->TxStatus
[3] & TxAborted
)?TSAD_TABT3
:0)
2431 |((s
->TxStatus
[2] & TxAborted
)?TSAD_TABT2
:0)
2432 |((s
->TxStatus
[1] & TxAborted
)?TSAD_TABT1
:0)
2433 |((s
->TxStatus
[0] & TxAborted
)?TSAD_TABT0
:0)
2435 |((s
->TxStatus
[3] & TxHostOwns
)?TSAD_OWN3
:0)
2436 |((s
->TxStatus
[2] & TxHostOwns
)?TSAD_OWN2
:0)
2437 |((s
->TxStatus
[1] & TxHostOwns
)?TSAD_OWN1
:0)
2438 |((s
->TxStatus
[0] & TxHostOwns
)?TSAD_OWN0
:0) ;
2441 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret
));
2446 static uint16_t rtl8139_CSCR_read(RTL8139State
*s
)
2448 uint16_t ret
= s
->CSCR
;
2450 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret
));
2455 static void rtl8139_TxAddr_write(RTL8139State
*s
, uint32_t txAddrOffset
, uint32_t val
)
2457 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset
, val
));
2459 s
->TxAddr
[txAddrOffset
/4] = val
;
2462 static uint32_t rtl8139_TxAddr_read(RTL8139State
*s
, uint32_t txAddrOffset
)
2464 uint32_t ret
= s
->TxAddr
[txAddrOffset
/4];
2466 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset
, ret
));
2471 static void rtl8139_RxBufPtr_write(RTL8139State
*s
, uint32_t val
)
2473 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val
));
2475 /* this value is off by 16 */
2476 s
->RxBufPtr
= MOD2(val
+ 0x10, s
->RxBufferSize
);
2478 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2479 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
2482 static uint32_t rtl8139_RxBufPtr_read(RTL8139State
*s
)
2484 /* this value is off by 16 */
2485 uint32_t ret
= s
->RxBufPtr
- 0x10;
2487 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret
));
2492 static uint32_t rtl8139_RxBufAddr_read(RTL8139State
*s
)
2494 /* this value is NOT off by 16 */
2495 uint32_t ret
= s
->RxBufAddr
;
2497 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret
));
2502 static void rtl8139_RxBuf_write(RTL8139State
*s
, uint32_t val
)
2504 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val
));
2508 /* may need to reset rxring here */
2511 static uint32_t rtl8139_RxBuf_read(RTL8139State
*s
)
2513 uint32_t ret
= s
->RxBuf
;
2515 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret
));
2520 static void rtl8139_IntrMask_write(RTL8139State
*s
, uint32_t val
)
2522 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val
));
2524 /* mask unwriteable bits */
2525 val
= SET_MASKED(val
, 0x1e00, s
->IntrMask
);
2529 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
2530 rtl8139_update_irq(s
);
2534 static uint32_t rtl8139_IntrMask_read(RTL8139State
*s
)
2536 uint32_t ret
= s
->IntrMask
;
2538 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret
));
2543 static void rtl8139_IntrStatus_write(RTL8139State
*s
, uint32_t val
)
2545 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val
));
2549 /* writing to ISR has no effect */
2554 uint16_t newStatus
= s
->IntrStatus
& ~val
;
2556 /* mask unwriteable bits */
2557 newStatus
= SET_MASKED(newStatus
, 0x1e00, s
->IntrStatus
);
2559 /* writing 1 to interrupt status register bit clears it */
2561 rtl8139_update_irq(s
);
2563 s
->IntrStatus
= newStatus
;
2565 * Computing if we miss an interrupt here is not that correct but
2566 * considered that we should have had already an interrupt
2567 * and probably emulated is slower is better to assume this resetting was
2568 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2570 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
2571 rtl8139_update_irq(s
);
2576 static uint32_t rtl8139_IntrStatus_read(RTL8139State
*s
)
2578 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
2580 uint32_t ret
= s
->IntrStatus
;
2582 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret
));
2586 /* reading ISR clears all interrupts */
2589 rtl8139_update_irq(s
);
2596 static void rtl8139_MultiIntr_write(RTL8139State
*s
, uint32_t val
)
2598 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val
));
2600 /* mask unwriteable bits */
2601 val
= SET_MASKED(val
, 0xf000, s
->MultiIntr
);
2606 static uint32_t rtl8139_MultiIntr_read(RTL8139State
*s
)
2608 uint32_t ret
= s
->MultiIntr
;
2610 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret
));
2615 static void rtl8139_io_writeb(void *opaque
, uint8_t addr
, uint32_t val
)
2617 RTL8139State
*s
= opaque
;
2623 case MAC0
... MAC0
+5:
2624 s
->phys
[addr
- MAC0
] = val
;
2626 case MAC0
+6 ... MAC0
+7:
2629 case MAR0
... MAR0
+7:
2630 s
->mult
[addr
- MAR0
] = val
;
2633 rtl8139_ChipCmd_write(s
, val
);
2636 rtl8139_Cfg9346_write(s
, val
);
2638 case TxConfig
: /* windows driver sometimes writes using byte-lenth call */
2639 rtl8139_TxConfig_writeb(s
, val
);
2642 rtl8139_Config0_write(s
, val
);
2645 rtl8139_Config1_write(s
, val
);
2648 rtl8139_Config3_write(s
, val
);
2651 rtl8139_Config4_write(s
, val
);
2654 rtl8139_Config5_write(s
, val
);
2658 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val
));
2662 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val
));
2665 s
->clock_enabled
= 1;
2667 else if (val
== 'H')
2669 s
->clock_enabled
= 0;
2674 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val
));
2679 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val
));
2682 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2683 //rtl8139_cplus_transmit(s);
2687 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2688 rtl8139_cplus_transmit(s
);
2694 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr
, val
));
2699 static void rtl8139_io_writew(void *opaque
, uint8_t addr
, uint32_t val
)
2701 RTL8139State
*s
= opaque
;
2708 rtl8139_IntrMask_write(s
, val
);
2712 rtl8139_IntrStatus_write(s
, val
);
2716 rtl8139_MultiIntr_write(s
, val
);
2720 rtl8139_RxBufPtr_write(s
, val
);
2724 rtl8139_BasicModeCtrl_write(s
, val
);
2726 case BasicModeStatus
:
2727 rtl8139_BasicModeStatus_write(s
, val
);
2730 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val
));
2731 s
->NWayAdvert
= val
;
2734 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val
));
2737 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val
));
2738 s
->NWayExpansion
= val
;
2742 rtl8139_CpCmd_write(s
, val
);
2746 rtl8139_IntrMitigate_write(s
, val
);
2750 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr
, val
));
2752 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2753 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2758 static void rtl8139_set_next_tctr_time(RTL8139State
*s
, int64_t current_time
)
2760 int64_t pci_time
, next_time
;
2763 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2765 if (s
->TimerExpire
&& current_time
>= s
->TimerExpire
) {
2766 s
->IntrStatus
|= PCSTimeout
;
2767 rtl8139_update_irq(s
);
2770 /* Set QEMU timer only if needed that is
2771 * - TimerInt <> 0 (we have a timer)
2772 * - mask = 1 (we want an interrupt timer)
2773 * - irq = 0 (irq is not already active)
2774 * If any of above change we need to compute timer again
2775 * Also we must check if timer is passed without QEMU timer
2782 pci_time
= muldiv64(current_time
- s
->TCTR_base
, PCI_FREQUENCY
,
2783 get_ticks_per_sec());
2784 low_pci
= pci_time
& 0xffffffff;
2785 pci_time
= pci_time
- low_pci
+ s
->TimerInt
;
2786 if (low_pci
>= s
->TimerInt
) {
2787 pci_time
+= 0x100000000LL
;
2789 next_time
= s
->TCTR_base
+ muldiv64(pci_time
, get_ticks_per_sec(),
2791 s
->TimerExpire
= next_time
;
2793 if ((s
->IntrMask
& PCSTimeout
) != 0 && (s
->IntrStatus
& PCSTimeout
) == 0) {
2794 qemu_mod_timer(s
->timer
, next_time
);
2798 static void rtl8139_io_writel(void *opaque
, uint8_t addr
, uint32_t val
)
2800 RTL8139State
*s
= opaque
;
2807 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2812 rtl8139_TxConfig_write(s
, val
);
2816 rtl8139_RxConfig_write(s
, val
);
2819 case TxStatus0
... TxStatus0
+4*4-1:
2820 rtl8139_TxStatus_write(s
, addr
-TxStatus0
, val
);
2823 case TxAddr0
... TxAddr0
+4*4-1:
2824 rtl8139_TxAddr_write(s
, addr
-TxAddr0
, val
);
2828 rtl8139_RxBuf_write(s
, val
);
2832 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val
));
2833 s
->RxRingAddrLO
= val
;
2837 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val
));
2838 s
->RxRingAddrHI
= val
;
2842 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2843 s
->TCTR_base
= qemu_get_clock(vm_clock
);
2844 rtl8139_set_next_tctr_time(s
, s
->TCTR_base
);
2848 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val
));
2849 if (s
->TimerInt
!= val
) {
2851 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
2856 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr
, val
));
2857 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2858 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2859 rtl8139_io_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2860 rtl8139_io_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2865 static uint32_t rtl8139_io_readb(void *opaque
, uint8_t addr
)
2867 RTL8139State
*s
= opaque
;
2874 case MAC0
... MAC0
+5:
2875 ret
= s
->phys
[addr
- MAC0
];
2877 case MAC0
+6 ... MAC0
+7:
2880 case MAR0
... MAR0
+7:
2881 ret
= s
->mult
[addr
- MAR0
];
2884 ret
= rtl8139_ChipCmd_read(s
);
2887 ret
= rtl8139_Cfg9346_read(s
);
2890 ret
= rtl8139_Config0_read(s
);
2893 ret
= rtl8139_Config1_read(s
);
2896 ret
= rtl8139_Config3_read(s
);
2899 ret
= rtl8139_Config4_read(s
);
2902 ret
= rtl8139_Config5_read(s
);
2907 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret
));
2911 ret
= s
->clock_enabled
;
2912 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret
));
2916 ret
= RTL8139_PCI_REVID
;
2917 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret
));
2922 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret
));
2925 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2926 ret
= s
->TxConfig
>> 24;
2927 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret
));
2931 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr
));
2939 static uint32_t rtl8139_io_readw(void *opaque
, uint8_t addr
)
2941 RTL8139State
*s
= opaque
;
2944 addr
&= 0xfe; /* mask lower bit */
2949 ret
= rtl8139_IntrMask_read(s
);
2953 ret
= rtl8139_IntrStatus_read(s
);
2957 ret
= rtl8139_MultiIntr_read(s
);
2961 ret
= rtl8139_RxBufPtr_read(s
);
2965 ret
= rtl8139_RxBufAddr_read(s
);
2969 ret
= rtl8139_BasicModeCtrl_read(s
);
2971 case BasicModeStatus
:
2972 ret
= rtl8139_BasicModeStatus_read(s
);
2975 ret
= s
->NWayAdvert
;
2976 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret
));
2980 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret
));
2983 ret
= s
->NWayExpansion
;
2984 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret
));
2988 ret
= rtl8139_CpCmd_read(s
);
2992 ret
= rtl8139_IntrMitigate_read(s
);
2996 ret
= rtl8139_TSAD_read(s
);
3000 ret
= rtl8139_CSCR_read(s
);
3004 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr
));
3006 ret
= rtl8139_io_readb(opaque
, addr
);
3007 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
3009 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr
, ret
));
3016 static uint32_t rtl8139_io_readl(void *opaque
, uint8_t addr
)
3018 RTL8139State
*s
= opaque
;
3021 addr
&= 0xfc; /* also mask low 2 bits */
3028 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret
));
3032 ret
= rtl8139_TxConfig_read(s
);
3036 ret
= rtl8139_RxConfig_read(s
);
3039 case TxStatus0
... TxStatus0
+4*4-1:
3040 ret
= rtl8139_TxStatus_read(s
, addr
-TxStatus0
);
3043 case TxAddr0
... TxAddr0
+4*4-1:
3044 ret
= rtl8139_TxAddr_read(s
, addr
-TxAddr0
);
3048 ret
= rtl8139_RxBuf_read(s
);
3052 ret
= s
->RxRingAddrLO
;
3053 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret
));
3057 ret
= s
->RxRingAddrHI
;
3058 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret
));
3062 ret
= muldiv64(qemu_get_clock(vm_clock
) - s
->TCTR_base
,
3063 PCI_FREQUENCY
, get_ticks_per_sec());
3064 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret
));
3069 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret
));
3073 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr
));
3075 ret
= rtl8139_io_readb(opaque
, addr
);
3076 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
3077 ret
|= rtl8139_io_readb(opaque
, addr
+ 2) << 16;
3078 ret
|= rtl8139_io_readb(opaque
, addr
+ 3) << 24;
3080 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr
, ret
));
3089 static void rtl8139_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
3091 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3094 static void rtl8139_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
3096 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3099 static void rtl8139_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
3101 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3104 static uint32_t rtl8139_ioport_readb(void *opaque
, uint32_t addr
)
3106 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3109 static uint32_t rtl8139_ioport_readw(void *opaque
, uint32_t addr
)
3111 return rtl8139_io_readw(opaque
, addr
& 0xFF);
3114 static uint32_t rtl8139_ioport_readl(void *opaque
, uint32_t addr
)
3116 return rtl8139_io_readl(opaque
, addr
& 0xFF);
3121 static void rtl8139_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3123 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3126 static void rtl8139_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3128 #ifdef TARGET_WORDS_BIGENDIAN
3131 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3134 static void rtl8139_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3136 #ifdef TARGET_WORDS_BIGENDIAN
3139 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3142 static uint32_t rtl8139_mmio_readb(void *opaque
, target_phys_addr_t addr
)
3144 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3147 static uint32_t rtl8139_mmio_readw(void *opaque
, target_phys_addr_t addr
)
3149 uint32_t val
= rtl8139_io_readw(opaque
, addr
& 0xFF);
3150 #ifdef TARGET_WORDS_BIGENDIAN
3156 static uint32_t rtl8139_mmio_readl(void *opaque
, target_phys_addr_t addr
)
3158 uint32_t val
= rtl8139_io_readl(opaque
, addr
& 0xFF);
3159 #ifdef TARGET_WORDS_BIGENDIAN
3165 static int rtl8139_post_load(void *opaque
, int version_id
)
3167 RTL8139State
* s
= opaque
;
3168 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
3169 if (version_id
< 4) {
3170 s
->cplus_enabled
= s
->CpCmd
!= 0;
3176 static void rtl8139_pre_save(void *opaque
)
3178 RTL8139State
* s
= opaque
;
3179 int64_t current_time
= qemu_get_clock(vm_clock
);
3181 /* set IntrStatus correctly */
3182 rtl8139_set_next_tctr_time(s
, current_time
);
3183 s
->TCTR
= muldiv64(current_time
- s
->TCTR_base
, PCI_FREQUENCY
,
3184 get_ticks_per_sec());
3187 static const VMStateDescription vmstate_rtl8139
= {
3190 .minimum_version_id
= 3,
3191 .minimum_version_id_old
= 3,
3192 .post_load
= rtl8139_post_load
,
3193 .pre_save
= rtl8139_pre_save
,
3194 .fields
= (VMStateField
[]) {
3195 VMSTATE_PCI_DEVICE(dev
, RTL8139State
),
3196 VMSTATE_PARTIAL_BUFFER(phys
, RTL8139State
, 6),
3197 VMSTATE_BUFFER(mult
, RTL8139State
),
3198 VMSTATE_UINT32_ARRAY(TxStatus
, RTL8139State
, 4),
3199 VMSTATE_UINT32_ARRAY(TxAddr
, RTL8139State
, 4),
3201 VMSTATE_UINT32(RxBuf
, RTL8139State
),
3202 VMSTATE_UINT32(RxBufferSize
, RTL8139State
),
3203 VMSTATE_UINT32(RxBufPtr
, RTL8139State
),
3204 VMSTATE_UINT32(RxBufAddr
, RTL8139State
),
3206 VMSTATE_UINT16(IntrStatus
, RTL8139State
),
3207 VMSTATE_UINT16(IntrMask
, RTL8139State
),
3209 VMSTATE_UINT32(TxConfig
, RTL8139State
),
3210 VMSTATE_UINT32(RxConfig
, RTL8139State
),
3211 VMSTATE_UINT32(RxMissed
, RTL8139State
),
3212 VMSTATE_UINT16(CSCR
, RTL8139State
),
3214 VMSTATE_UINT8(Cfg9346
, RTL8139State
),
3215 VMSTATE_UINT8(Config0
, RTL8139State
),
3216 VMSTATE_UINT8(Config1
, RTL8139State
),
3217 VMSTATE_UINT8(Config3
, RTL8139State
),
3218 VMSTATE_UINT8(Config4
, RTL8139State
),
3219 VMSTATE_UINT8(Config5
, RTL8139State
),
3221 VMSTATE_UINT8(clock_enabled
, RTL8139State
),
3222 VMSTATE_UINT8(bChipCmdState
, RTL8139State
),
3224 VMSTATE_UINT16(MultiIntr
, RTL8139State
),
3226 VMSTATE_UINT16(BasicModeCtrl
, RTL8139State
),
3227 VMSTATE_UINT16(BasicModeStatus
, RTL8139State
),
3228 VMSTATE_UINT16(NWayAdvert
, RTL8139State
),
3229 VMSTATE_UINT16(NWayLPAR
, RTL8139State
),
3230 VMSTATE_UINT16(NWayExpansion
, RTL8139State
),
3232 VMSTATE_UINT16(CpCmd
, RTL8139State
),
3233 VMSTATE_UINT8(TxThresh
, RTL8139State
),
3236 VMSTATE_MACADDR(conf
.macaddr
, RTL8139State
),
3237 VMSTATE_INT32(rtl8139_mmio_io_addr
, RTL8139State
),
3239 VMSTATE_UINT32(currTxDesc
, RTL8139State
),
3240 VMSTATE_UINT32(currCPlusRxDesc
, RTL8139State
),
3241 VMSTATE_UINT32(currCPlusTxDesc
, RTL8139State
),
3242 VMSTATE_UINT32(RxRingAddrLO
, RTL8139State
),
3243 VMSTATE_UINT32(RxRingAddrHI
, RTL8139State
),
3245 VMSTATE_UINT16_ARRAY(eeprom
.contents
, RTL8139State
, EEPROM_9346_SIZE
),
3246 VMSTATE_INT32(eeprom
.mode
, RTL8139State
),
3247 VMSTATE_UINT32(eeprom
.tick
, RTL8139State
),
3248 VMSTATE_UINT8(eeprom
.address
, RTL8139State
),
3249 VMSTATE_UINT16(eeprom
.input
, RTL8139State
),
3250 VMSTATE_UINT16(eeprom
.output
, RTL8139State
),
3252 VMSTATE_UINT8(eeprom
.eecs
, RTL8139State
),
3253 VMSTATE_UINT8(eeprom
.eesk
, RTL8139State
),
3254 VMSTATE_UINT8(eeprom
.eedi
, RTL8139State
),
3255 VMSTATE_UINT8(eeprom
.eedo
, RTL8139State
),
3257 VMSTATE_UINT32(TCTR
, RTL8139State
),
3258 VMSTATE_UINT32(TimerInt
, RTL8139State
),
3259 VMSTATE_INT64(TCTR_base
, RTL8139State
),
3261 VMSTATE_STRUCT(tally_counters
, RTL8139State
, 0,
3262 vmstate_tally_counters
, RTL8139TallyCounters
),
3264 VMSTATE_UINT32_V(cplus_enabled
, RTL8139State
, 4),
3265 VMSTATE_END_OF_LIST()
3269 /***********************************************************/
3270 /* PCI RTL8139 definitions */
3272 static void rtl8139_mmio_map(PCIDevice
*pci_dev
, int region_num
,
3273 pcibus_t addr
, pcibus_t size
, int type
)
3275 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, pci_dev
);
3277 cpu_register_physical_memory(addr
+ 0, 0x100, s
->rtl8139_mmio_io_addr
);
3280 static void rtl8139_ioport_map(PCIDevice
*pci_dev
, int region_num
,
3281 pcibus_t addr
, pcibus_t size
, int type
)
3283 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, pci_dev
);
3285 register_ioport_write(addr
, 0x100, 1, rtl8139_ioport_writeb
, s
);
3286 register_ioport_read( addr
, 0x100, 1, rtl8139_ioport_readb
, s
);
3288 register_ioport_write(addr
, 0x100, 2, rtl8139_ioport_writew
, s
);
3289 register_ioport_read( addr
, 0x100, 2, rtl8139_ioport_readw
, s
);
3291 register_ioport_write(addr
, 0x100, 4, rtl8139_ioport_writel
, s
);
3292 register_ioport_read( addr
, 0x100, 4, rtl8139_ioport_readl
, s
);
3295 static CPUReadMemoryFunc
* const rtl8139_mmio_read
[3] = {
3301 static CPUWriteMemoryFunc
* const rtl8139_mmio_write
[3] = {
3302 rtl8139_mmio_writeb
,
3303 rtl8139_mmio_writew
,
3304 rtl8139_mmio_writel
,
3307 static void rtl8139_timer(void *opaque
)
3309 RTL8139State
*s
= opaque
;
3311 if (!s
->clock_enabled
)
3313 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3317 s
->IntrStatus
|= PCSTimeout
;
3318 rtl8139_update_irq(s
);
3319 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
3322 static void rtl8139_cleanup(VLANClientState
*nc
)
3324 RTL8139State
*s
= DO_UPCAST(NICState
, nc
, nc
)->opaque
;
3329 static int pci_rtl8139_uninit(PCIDevice
*dev
)
3331 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, dev
);
3333 cpu_unregister_io_memory(s
->rtl8139_mmio_io_addr
);
3334 if (s
->cplus_txbuffer
) {
3335 qemu_free(s
->cplus_txbuffer
);
3336 s
->cplus_txbuffer
= NULL
;
3338 qemu_del_timer(s
->timer
);
3339 qemu_free_timer(s
->timer
);
3340 qemu_del_vlan_client(&s
->nic
->nc
);
3344 static NetClientInfo net_rtl8139_info
= {
3345 .type
= NET_CLIENT_TYPE_NIC
,
3346 .size
= sizeof(NICState
),
3347 .can_receive
= rtl8139_can_receive
,
3348 .receive
= rtl8139_receive
,
3349 .cleanup
= rtl8139_cleanup
,
3352 static int pci_rtl8139_init(PCIDevice
*dev
)
3354 RTL8139State
* s
= DO_UPCAST(RTL8139State
, dev
, dev
);
3357 pci_conf
= s
->dev
.config
;
3358 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_REALTEK
);
3359 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_REALTEK_8139
);
3360 /* TODO: value should be 0 at RST#. */
3361 pci_conf
[PCI_COMMAND
] = PCI_COMMAND_IO
| PCI_COMMAND_MASTER
;
3362 pci_conf
[PCI_REVISION_ID
] = RTL8139_PCI_REVID
; /* >=0x20 is for 8139C+ */
3363 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
3364 /* TODO: value should be 0 at RST# */
3365 pci_conf
[PCI_INTERRUPT_PIN
] = 1; /* interrupt pin 0 */
3366 /* TODO: start of capability list, but no capability
3367 * list bit in status register, and offset 0xdc seems unused. */
3368 pci_conf
[PCI_CAPABILITY_LIST
] = 0xdc;
3370 /* I/O handler for memory-mapped I/O */
3371 s
->rtl8139_mmio_io_addr
=
3372 cpu_register_io_memory(rtl8139_mmio_read
, rtl8139_mmio_write
, s
);
3374 pci_register_bar(&s
->dev
, 0, 0x100,
3375 PCI_BASE_ADDRESS_SPACE_IO
, rtl8139_ioport_map
);
3377 pci_register_bar(&s
->dev
, 1, 0x100,
3378 PCI_BASE_ADDRESS_SPACE_MEMORY
, rtl8139_mmio_map
);
3380 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
3382 s
->nic
= qemu_new_nic(&net_rtl8139_info
, &s
->conf
,
3383 dev
->qdev
.info
->name
, dev
->qdev
.id
, s
);
3384 qemu_format_nic_info_str(&s
->nic
->nc
, s
->conf
.macaddr
.a
);
3386 s
->cplus_txbuffer
= NULL
;
3387 s
->cplus_txbuffer_len
= 0;
3388 s
->cplus_txbuffer_offset
= 0;
3391 s
->timer
= qemu_new_timer(vm_clock
, rtl8139_timer
, s
);
3392 rtl8139_set_next_tctr_time(s
, qemu_get_clock(vm_clock
));
3396 static PCIDeviceInfo rtl8139_info
= {
3397 .qdev
.name
= "rtl8139",
3398 .qdev
.size
= sizeof(RTL8139State
),
3399 .qdev
.reset
= rtl8139_reset
,
3400 .qdev
.vmsd
= &vmstate_rtl8139
,
3401 .init
= pci_rtl8139_init
,
3402 .exit
= pci_rtl8139_uninit
,
3403 .romfile
= "pxe-rtl8139.bin",
3404 .qdev
.props
= (Property
[]) {
3405 DEFINE_NIC_PROPERTIES(RTL8139State
, conf
),
3406 DEFINE_PROP_END_OF_LIST(),
3410 static void rtl8139_register_devices(void)
3412 pci_qdev_register(&rtl8139_info
);
3415 device_init(rtl8139_register_devices
)