hw/omap_gpmc.c

   1 /*
   2  * TI OMAP general purpose memory controller emulation.
   3  *
   4  * Copyright (C) 2007-2009 Nokia Corporation
   5  * Original code written by Andrzej Zaborowski <andrew@openedhand.com>
   6  * Enhancements for OMAP3 and NAND support written by Juha Riihimäki
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) any later version of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "hw.h"
  22 #include "flash.h"
  23 #include "omap.h"
  24 #include "memory.h"
  25 #include "exec-memory.h"
  26
  27 /* General-Purpose Memory Controller */
  28 struct omap_gpmc_s {
  29     qemu_irq irq;
  30     MemoryRegion iomem;
  31
  32     uint8_t sysconfig;
  33     uint16_t irqst;
  34     uint16_t irqen;
  35     uint16_t timeout;
  36     uint16_t config;
  37     uint32_t prefconfig[2];
  38     int prefcontrol;
  39     int preffifo;
  40     int prefcount;
  41     struct omap_gpmc_cs_file_s {
  42         uint32_t config[7];
  43         target_phys_addr_t base;
  44         size_t size;
  45         MemoryRegion *iomem;
  46         MemoryRegion container;
  47         void (*base_update)(void *opaque, target_phys_addr_t new);
  48         void (*unmap)(void *opaque);
  49         void *opaque;
  50     } cs_file[8];
  51     int ecc_cs;
  52     int ecc_ptr;
  53     uint32_t ecc_cfg;
  54     ECCState ecc[9];
  55 };
  56
  57 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
  58 {
  59     qemu_set_irq(s->irq, s->irqen & s->irqst);
  60 }
  61
  62 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
  63 {
  64     /* TODO: check for overlapping regions and report access errors */
  65     if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
  66                     (base < 0 || base >= 0x40) ||
  67                     (base & 0x0f & ~mask)) {
  68         fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
  69                         __FUNCTION__);
  70         return;
  71     }
  72
  73     if (!f->opaque)
  74         return;
  75
  76     f->base = base << 24;
  77     f->size = (0x0fffffff & ~(mask << 24)) + 1;
  78     /* TODO: rather than setting the size of the mapping (which should be
  79      * constant), the mask should cause wrapping of the address space, so
  80      * that the same memory becomes accessible at every <i>size</i> bytes
  81      * starting from <i>base</i>.  */
  82     if (f->iomem) {
  83         memory_region_init(&f->container, "omap-gpmc-file", f->size);
  84         memory_region_add_subregion(&f->container, 0, f->iomem);
  85         memory_region_add_subregion(get_system_memory(), f->base,
  86                                     &f->container);
  87     }
  88
  89     if (f->base_update)
  90         f->base_update(f->opaque, f->base);
  91 }
  92
  93 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
  94 {
  95     if (f->size) {
  96         if (f->unmap)
  97             f->unmap(f->opaque);
  98         if (f->iomem) {
  99             memory_region_del_subregion(get_system_memory(), &f->container);
 100             memory_region_del_subregion(&f->container, f->iomem);
 101             memory_region_destroy(&f->container);
 102         }
 103         f->base = 0;
 104         f->size = 0;
 105     }
 106 }
 107
 108 void omap_gpmc_reset(struct omap_gpmc_s *s)
 109 {
 110     int i;
 111
 112     s->sysconfig = 0;
 113     s->irqst = 0;
 114     s->irqen = 0;
 115     omap_gpmc_int_update(s);
 116     s->timeout = 0;
 117     s->config = 0xa00;
 118     s->prefconfig[0] = 0x00004000;
 119     s->prefconfig[1] = 0x00000000;
 120     s->prefcontrol = 0;
 121     s->preffifo = 0;
 122     s->prefcount = 0;
 123     for (i = 0; i < 8; i ++) {
 124         if (s->cs_file[i].config[6] & (1 << 6))                 /* CSVALID */
 125             omap_gpmc_cs_unmap(s->cs_file + i);
 126         s->cs_file[i].config[0] = i ? 1 << 12 : 0;
 127         s->cs_file[i].config[1] = 0x101001;
 128         s->cs_file[i].config[2] = 0x020201;
 129         s->cs_file[i].config[3] = 0x10031003;
 130         s->cs_file[i].config[4] = 0x10f1111;
 131         s->cs_file[i].config[5] = 0;
 132         s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
 133         if (s->cs_file[i].config[6] & (1 << 6))                 /* CSVALID */
 134             omap_gpmc_cs_map(&s->cs_file[i],
 135                             s->cs_file[i].config[6] & 0x1f,     /* MASKADDR */
 136                         (s->cs_file[i].config[6] >> 8 & 0xf));  /* BASEADDR */
 137     }
 138     omap_gpmc_cs_map(s->cs_file, 0, 0xf);
 139     s->ecc_cs = 0;
 140     s->ecc_ptr = 0;
 141     s->ecc_cfg = 0x3fcff000;
 142     for (i = 0; i < 9; i ++)
 143         ecc_reset(&s->ecc[i]);
 144 }
 145
 146 static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
 147                                unsigned size)
 148 {
 149     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 150     int cs;
 151     struct omap_gpmc_cs_file_s *f;
 152
 153     if (size != 4) {
 154         return omap_badwidth_read32(opaque, addr);
 155     }
 156
 157     switch (addr) {
 158     case 0x000: /* GPMC_REVISION */
 159         return 0x20;
 160
 161     case 0x010: /* GPMC_SYSCONFIG */
 162         return s->sysconfig;
 163
 164     case 0x014: /* GPMC_SYSSTATUS */
 165         return 1;                                               /* RESETDONE */
 166
 167     case 0x018: /* GPMC_IRQSTATUS */
 168         return s->irqst;
 169
 170     case 0x01c: /* GPMC_IRQENABLE */
 171         return s->irqen;
 172
 173     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 174         return s->timeout;
 175
 176     case 0x044: /* GPMC_ERR_ADDRESS */
 177     case 0x048: /* GPMC_ERR_TYPE */
 178         return 0;
 179
 180     case 0x050: /* GPMC_CONFIG */
 181         return s->config;
 182
 183     case 0x054: /* GPMC_STATUS */
 184         return 0x001;
 185
 186     case 0x060 ... 0x1d4:
 187         cs = (addr - 0x060) / 0x30;
 188         addr -= cs * 0x30;
 189         f = s->cs_file + cs;
 190         switch (addr) {
 191             case 0x60:  /* GPMC_CONFIG1 */
 192                 return f->config[0];
 193             case 0x64:  /* GPMC_CONFIG2 */
 194                 return f->config[1];
 195             case 0x68:  /* GPMC_CONFIG3 */
 196                 return f->config[2];
 197             case 0x6c:  /* GPMC_CONFIG4 */
 198                 return f->config[3];
 199             case 0x70:  /* GPMC_CONFIG5 */
 200                 return f->config[4];
 201             case 0x74:  /* GPMC_CONFIG6 */
 202                 return f->config[5];
 203             case 0x78:  /* GPMC_CONFIG7 */
 204                 return f->config[6];
 205             case 0x84:  /* GPMC_NAND_DATA */
 206                 return 0;
 207         }
 208         break;
 209
 210     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 211         return s->prefconfig[0];
 212     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 213         return s->prefconfig[1];
 214     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 215         return s->prefcontrol;
 216     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 217         return (s->preffifo << 24) |
 218                 ((s->preffifo >
 219                   ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
 220                 s->prefcount;
 221
 222     case 0x1f4: /* GPMC_ECC_CONFIG */
 223         return s->ecc_cs;
 224     case 0x1f8: /* GPMC_ECC_CONTROL */
 225         return s->ecc_ptr;
 226     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 227         return s->ecc_cfg;
 228     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 229         cs = (addr & 0x1f) >> 2;
 230         /* TODO: check correctness */
 231         return
 232                 ((s->ecc[cs].cp    &  0x07) <<  0) |
 233                 ((s->ecc[cs].cp    &  0x38) << 13) |
 234                 ((s->ecc[cs].lp[0] & 0x1ff) <<  3) |
 235                 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
 236
 237     case 0x230: /* GPMC_TESTMODE_CTRL */
 238         return 0;
 239     case 0x234: /* GPMC_PSA_LSB */
 240     case 0x238: /* GPMC_PSA_MSB */
 241         return 0x00000000;
 242     }
 243
 244     OMAP_BAD_REG(addr);
 245     return 0;
 246 }
 247
 248 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
 249                             uint64_t value, unsigned size)
 250 {
 251     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 252     int cs;
 253     struct omap_gpmc_cs_file_s *f;
 254
 255     if (size != 4) {
 256         return omap_badwidth_write32(opaque, addr, value);
 257     }
 258
 259     switch (addr) {
 260     case 0x000: /* GPMC_REVISION */
 261     case 0x014: /* GPMC_SYSSTATUS */
 262     case 0x054: /* GPMC_STATUS */
 263     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 264     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 265     case 0x234: /* GPMC_PSA_LSB */
 266     case 0x238: /* GPMC_PSA_MSB */
 267         OMAP_RO_REG(addr);
 268         break;
 269
 270     case 0x010: /* GPMC_SYSCONFIG */
 271         if ((value >> 3) == 0x3)
 272             fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
 273                             __FUNCTION__, value >> 3);
 274         if (value & 2)
 275             omap_gpmc_reset(s);
 276         s->sysconfig = value & 0x19;
 277         break;
 278
 279     case 0x018: /* GPMC_IRQSTATUS */
 280         s->irqen = ~value;
 281         omap_gpmc_int_update(s);
 282         break;
 283
 284     case 0x01c: /* GPMC_IRQENABLE */
 285         s->irqen = value & 0xf03;
 286         omap_gpmc_int_update(s);
 287         break;
 288
 289     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 290         s->timeout = value & 0x1ff1;
 291         break;
 292
 293     case 0x044: /* GPMC_ERR_ADDRESS */
 294     case 0x048: /* GPMC_ERR_TYPE */
 295         break;
 296
 297     case 0x050: /* GPMC_CONFIG */
 298         s->config = value & 0xf13;
 299         break;
 300
 301     case 0x060 ... 0x1d4:
 302         cs = (addr - 0x060) / 0x30;
 303         addr -= cs * 0x30;
 304         f = s->cs_file + cs;
 305         switch (addr) {
 306             case 0x60:  /* GPMC_CONFIG1 */
 307                 f->config[0] = value & 0xffef3e13;
 308                 break;
 309             case 0x64:  /* GPMC_CONFIG2 */
 310                 f->config[1] = value & 0x001f1f8f;
 311                 break;
 312             case 0x68:  /* GPMC_CONFIG3 */
 313                 f->config[2] = value & 0x001f1f8f;
 314                 break;
 315             case 0x6c:  /* GPMC_CONFIG4 */
 316                 f->config[3] = value & 0x1f8f1f8f;
 317                 break;
 318             case 0x70:  /* GPMC_CONFIG5 */
 319                 f->config[4] = value & 0x0f1f1f1f;
 320                 break;
 321             case 0x74:  /* GPMC_CONFIG6 */
 322                 f->config[5] = value & 0x00000fcf;
 323                 break;
 324             case 0x78:  /* GPMC_CONFIG7 */
 325                 if ((f->config[6] ^ value) & 0xf7f) {
 326                     if (f->config[6] & (1 << 6))                /* CSVALID */
 327                         omap_gpmc_cs_unmap(f);
 328                     if (value & (1 << 6))                       /* CSVALID */
 329                         omap_gpmc_cs_map(f, value & 0x1f,       /* MASKADDR */
 330                                         (value >> 8 & 0xf));    /* BASEADDR */
 331                 }
 332                 f->config[6] = value & 0x00000f7f;
 333                 break;
 334             case 0x7c:  /* GPMC_NAND_COMMAND */
 335             case 0x80:  /* GPMC_NAND_ADDRESS */
 336             case 0x84:  /* GPMC_NAND_DATA */
 337                 break;
 338
 339             default:
 340                 goto bad_reg;
 341         }
 342         break;
 343
 344     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 345         s->prefconfig[0] = value & 0x7f8f7fbf;
 346         /* TODO: update interrupts, fifos, dmas */
 347         break;
 348
 349     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 350         s->prefconfig[1] = value & 0x3fff;
 351         break;
 352
 353     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 354         s->prefcontrol = value & 1;
 355         if (s->prefcontrol) {
 356             if (s->prefconfig[0] & 1)
 357                 s->preffifo = 0x40;
 358             else
 359                 s->preffifo = 0x00;
 360         }
 361         /* TODO: start */
 362         break;
 363
 364     case 0x1f4: /* GPMC_ECC_CONFIG */
 365         s->ecc_cs = 0x8f;
 366         break;
 367     case 0x1f8: /* GPMC_ECC_CONTROL */
 368         if (value & (1 << 8))
 369             for (cs = 0; cs < 9; cs ++)
 370                 ecc_reset(&s->ecc[cs]);
 371         s->ecc_ptr = value & 0xf;
 372         if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
 373             s->ecc_ptr = 0;
 374             s->ecc_cs &= ~1;
 375         }
 376         break;
 377     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 378         s->ecc_cfg = value & 0x3fcff1ff;
 379         break;
 380     case 0x230: /* GPMC_TESTMODE_CTRL */
 381         if (value & 7)
 382             fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
 383         break;
 384
 385     default:
 386     bad_reg:
 387         OMAP_BAD_REG(addr);
 388         return;
 389     }
 390 }
 391
 392 static const MemoryRegionOps omap_gpmc_ops = {
 393     .read = omap_gpmc_read,
 394     .write = omap_gpmc_write,
 395     .endianness = DEVICE_NATIVE_ENDIAN,
 396 };
 397
 398 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
 399 {
 400     struct omap_gpmc_s *s = (struct omap_gpmc_s *)
 401             g_malloc0(sizeof(struct omap_gpmc_s));
 402
 403     omap_gpmc_reset(s);
 404
 405     memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
 406     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 407
 408     return s;
 409 }
 410
 411 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
 412                 void (*base_upd)(void *opaque, target_phys_addr_t new),
 413                 void (*unmap)(void *opaque), void *opaque)
 414 {
 415     struct omap_gpmc_cs_file_s *f;
 416
 417     if (cs < 0 || cs >= 8) {
 418         fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
 419         exit(-1);
 420     }
 421     f = &s->cs_file[cs];
 422
 423     f->iomem = iomem;
 424     f->base_update = base_upd;
 425     f->unmap = unmap;
 426     f->opaque = opaque;
 427
 428     if (f->config[6] & (1 << 6))                                /* CSVALID */
 429         omap_gpmc_cs_map(f, f->config[6] & 0x1f,                /* MASKADDR */
 430                         (f->config[6] >> 8 & 0xf));             /* BASEADDR */
 431 }