2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "qdev-addr.h"
46 * Sun4m architecture was used in the following machines:
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
58 * Sun4d architecture was used in the following machines:
63 * Sun4c architecture was used in the following machines:
64 * SPARCstation 1/1+, SPARCserver 1/1+
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
74 #define DPRINTF(fmt, ...) \
75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #define DPRINTF(fmt, ...)
80 #define KERNEL_LOAD_ADDR 0x00004000
81 #define CMDLINE_ADDR 0x007ff000
82 #define INITRD_LOAD_ADDR 0x00800000
83 #define PROM_SIZE_MAX (1024 * 1024)
84 #define PROM_VADDR 0xffd00000
85 #define PROM_FILENAME "openbios-sparc32"
86 #define CFG_ADDR 0xd00000510ULL
87 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
92 #define ESCC_CLOCK 4915200
95 target_phys_addr_t iommu_base
, slavio_base
;
96 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
97 target_phys_addr_t serial_base
, fd_base
;
98 target_phys_addr_t afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
99 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
100 target_phys_addr_t ecc_base
;
101 uint32_t ecc_version
;
102 uint8_t nvram_machine_id
;
104 uint32_t iommu_version
;
106 const char * const default_cpu_model
;
109 #define MAX_IOUNITS 5
112 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
113 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
114 target_phys_addr_t serial_base
;
115 target_phys_addr_t espdma_base
, esp_base
;
116 target_phys_addr_t ledma_base
, le_base
;
117 target_phys_addr_t tcx_base
;
118 target_phys_addr_t sbi_base
;
119 uint8_t nvram_machine_id
;
121 uint32_t iounit_version
;
123 const char * const default_cpu_model
;
127 target_phys_addr_t iommu_base
, slavio_base
;
128 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
129 target_phys_addr_t serial_base
, fd_base
;
130 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
131 target_phys_addr_t tcx_base
, aux1_base
;
132 uint8_t nvram_machine_id
;
134 uint32_t iommu_version
;
136 const char * const default_cpu_model
;
139 int DMA_get_channel_mode (int nchan
)
143 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
147 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
151 void DMA_hold_DREQ (int nchan
) {}
152 void DMA_release_DREQ (int nchan
) {}
153 void DMA_schedule(int nchan
) {}
154 void DMA_init (int high_page_enable
) {}
155 void DMA_register_channel (int nchan
,
156 DMA_transfer_handler transfer_handler
,
161 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
163 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
167 static void nvram_init(M48t59State
*nvram
, uint8_t *macaddr
,
168 const char *cmdline
, const char *boot_devices
,
169 ram_addr_t RAM_size
, uint32_t kernel_size
,
170 int width
, int height
, int depth
,
171 int nvram_machine_id
, const char *arch
)
175 uint8_t image
[0x1ff0];
176 struct OpenBIOS_nvpart_v1
*part_header
;
178 memset(image
, '\0', sizeof(image
));
182 // OpenBIOS nvram variables
183 // Variable partition
184 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
185 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
186 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
188 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
189 for (i
= 0; i
< nb_prom_envs
; i
++)
190 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
195 end
= start
+ ((end
- start
+ 15) & ~15);
196 OpenBIOS_finish_partition(part_header
, end
- start
);
200 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
201 part_header
->signature
= OPENBIOS_PART_FREE
;
202 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
205 OpenBIOS_finish_partition(part_header
, end
- start
);
207 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
210 for (i
= 0; i
< sizeof(image
); i
++)
211 m48t59_write(nvram
, i
, image
[i
]);
214 static DeviceState
*slavio_intctl
;
216 void pic_info(Monitor
*mon
)
219 slavio_pic_info(mon
, slavio_intctl
);
222 void irq_info(Monitor
*mon
)
225 slavio_irq_info(mon
, slavio_intctl
);
228 void cpu_check_irqs(CPUState
*env
)
230 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
231 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
234 for (i
= 15; i
> 0; i
--) {
235 if (env
->pil_in
& (1 << i
)) {
236 int old_interrupt
= env
->interrupt_index
;
238 env
->interrupt_index
= TT_EXTINT
| i
;
239 if (old_interrupt
!= env
->interrupt_index
) {
240 DPRINTF("Set CPU IRQ %d\n", i
);
241 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
246 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
247 DPRINTF("Reset CPU IRQ %d\n", env
->interrupt_index
& 15);
248 env
->interrupt_index
= 0;
249 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
253 static void cpu_set_irq(void *opaque
, int irq
, int level
)
255 CPUState
*env
= opaque
;
258 DPRINTF("Raise CPU IRQ %d\n", irq
);
260 env
->pil_in
|= 1 << irq
;
263 DPRINTF("Lower CPU IRQ %d\n", irq
);
264 env
->pil_in
&= ~(1 << irq
);
269 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
273 static void main_cpu_reset(void *opaque
)
275 CPUState
*env
= opaque
;
281 static void secondary_cpu_reset(void *opaque
)
283 CPUState
*env
= opaque
;
289 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
291 if (level
&& cpu_single_env
)
292 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
295 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
297 return addr
- 0xf0000000ULL
;
300 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
301 const char *initrd_filename
,
306 long initrd_size
, kernel_size
;
309 linux_boot
= (kernel_filename
!= NULL
);
320 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
321 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
323 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
324 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
327 kernel_size
= load_image_targphys(kernel_filename
,
329 RAM_size
- KERNEL_LOAD_ADDR
);
330 if (kernel_size
< 0) {
331 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
338 if (initrd_filename
) {
339 initrd_size
= load_image_targphys(initrd_filename
,
341 RAM_size
- INITRD_LOAD_ADDR
);
342 if (initrd_size
< 0) {
343 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
348 if (initrd_size
> 0) {
349 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
350 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
351 if (ldl_p(ptr
) == 0x48647253) { // HdrS
352 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
353 stl_p(ptr
+ 20, initrd_size
);
362 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
367 dev
= qdev_create(NULL
, "iommu");
368 qdev_prop_set_uint32(dev
, "version", version
);
369 qdev_init_nofail(dev
);
370 s
= sysbus_from_qdev(dev
);
371 sysbus_connect_irq(s
, 0, irq
);
372 sysbus_mmio_map(s
, 0, addr
);
377 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
378 void *iommu
, qemu_irq
*dev_irq
)
383 dev
= qdev_create(NULL
, "sparc32_dma");
384 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
385 qdev_init_nofail(dev
);
386 s
= sysbus_from_qdev(dev
);
387 sysbus_connect_irq(s
, 0, parent_irq
);
388 *dev_irq
= qdev_get_gpio_in(dev
, 0);
389 sysbus_mmio_map(s
, 0, daddr
);
394 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
395 void *dma_opaque
, qemu_irq irq
)
401 qemu_check_nic_model(&nd_table
[0], "lance");
403 dev
= qdev_create(NULL
, "lance");
404 qdev_set_nic_properties(dev
, nd
);
405 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
406 qdev_init_nofail(dev
);
407 s
= sysbus_from_qdev(dev
);
408 sysbus_mmio_map(s
, 0, leaddr
);
409 sysbus_connect_irq(s
, 0, irq
);
410 reset
= qdev_get_gpio_in(dev
, 0);
411 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
414 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
415 target_phys_addr_t addrg
,
416 qemu_irq
**parent_irq
)
422 dev
= qdev_create(NULL
, "slavio_intctl");
423 qdev_init_nofail(dev
);
425 s
= sysbus_from_qdev(dev
);
427 for (i
= 0; i
< MAX_CPUS
; i
++) {
428 for (j
= 0; j
< MAX_PILS
; j
++) {
429 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
432 sysbus_mmio_map(s
, 0, addrg
);
433 for (i
= 0; i
< MAX_CPUS
; i
++) {
434 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
440 #define SYS_TIMER_OFFSET 0x10000ULL
441 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
443 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
444 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
450 dev
= qdev_create(NULL
, "slavio_timer");
451 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
452 qdev_init_nofail(dev
);
453 s
= sysbus_from_qdev(dev
);
454 sysbus_connect_irq(s
, 0, master_irq
);
455 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
457 for (i
= 0; i
< MAX_CPUS
; i
++) {
458 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
459 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
463 #define MISC_LEDS 0x01600000
464 #define MISC_CFG 0x01800000
465 #define MISC_DIAG 0x01a00000
466 #define MISC_MDM 0x01b00000
467 #define MISC_SYS 0x01f00000
469 static void slavio_misc_init(target_phys_addr_t base
,
470 target_phys_addr_t aux1_base
,
471 target_phys_addr_t aux2_base
, qemu_irq irq
,
477 dev
= qdev_create(NULL
, "slavio_misc");
478 qdev_init_nofail(dev
);
479 s
= sysbus_from_qdev(dev
);
481 /* 8 bit registers */
483 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
485 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
487 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
488 /* 16 bit registers */
489 /* ss600mp diag LEDs */
490 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
491 /* 32 bit registers */
493 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
496 /* AUX 1 (Misc System Functions) */
497 sysbus_mmio_map(s
, 5, aux1_base
);
500 /* AUX 2 (Software Powerdown Control) */
501 sysbus_mmio_map(s
, 6, aux2_base
);
503 sysbus_connect_irq(s
, 0, irq
);
504 sysbus_connect_irq(s
, 1, fdc_tc
);
505 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
508 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
513 dev
= qdev_create(NULL
, "eccmemctl");
514 qdev_prop_set_uint32(dev
, "version", version
);
515 qdev_init_nofail(dev
);
516 s
= sysbus_from_qdev(dev
);
517 sysbus_connect_irq(s
, 0, irq
);
518 sysbus_mmio_map(s
, 0, base
);
519 if (version
== 0) { // SS-600MP only
520 sysbus_mmio_map(s
, 1, base
+ 0x1000);
524 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
529 dev
= qdev_create(NULL
, "apc");
530 qdev_init_nofail(dev
);
531 s
= sysbus_from_qdev(dev
);
532 /* Power management (APC) XXX: not a Slavio device */
533 sysbus_mmio_map(s
, 0, power_base
);
534 sysbus_connect_irq(s
, 0, cpu_halt
);
537 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
538 int height
, int depth
)
543 dev
= qdev_create(NULL
, "SUNW,tcx");
544 qdev_prop_set_taddr(dev
, "addr", addr
);
545 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
546 qdev_prop_set_uint16(dev
, "width", width
);
547 qdev_prop_set_uint16(dev
, "height", height
);
548 qdev_prop_set_uint16(dev
, "depth", depth
);
549 qdev_init_nofail(dev
);
550 s
= sysbus_from_qdev(dev
);
552 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
554 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
556 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
557 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
558 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
561 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
563 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
565 /* THC 8 bit (dummy) */
566 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
570 /* NCR89C100/MACIO Internal ID register */
571 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
573 static void idreg_init(target_phys_addr_t addr
)
578 dev
= qdev_create(NULL
, "macio_idreg");
579 qdev_init_nofail(dev
);
580 s
= sysbus_from_qdev(dev
);
582 sysbus_mmio_map(s
, 0, addr
);
583 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
586 static int idreg_init1(SysBusDevice
*dev
)
588 ram_addr_t idreg_offset
;
590 idreg_offset
= qemu_ram_alloc(sizeof(idreg_data
));
591 sysbus_init_mmio(dev
, sizeof(idreg_data
), idreg_offset
| IO_MEM_ROM
);
595 static SysBusDeviceInfo idreg_info
= {
597 .qdev
.name
= "macio_idreg",
598 .qdev
.size
= sizeof(SysBusDevice
),
601 static void idreg_register_devices(void)
603 sysbus_register_withprop(&idreg_info
);
606 device_init(idreg_register_devices
);
608 /* SS-5 TCX AFX register */
609 static void afx_init(target_phys_addr_t addr
)
614 dev
= qdev_create(NULL
, "tcx_afx");
615 qdev_init_nofail(dev
);
616 s
= sysbus_from_qdev(dev
);
618 sysbus_mmio_map(s
, 0, addr
);
621 static int afx_init1(SysBusDevice
*dev
)
623 ram_addr_t afx_offset
;
625 afx_offset
= qemu_ram_alloc(4);
626 sysbus_init_mmio(dev
, 4, afx_offset
| IO_MEM_RAM
);
630 static SysBusDeviceInfo afx_info
= {
632 .qdev
.name
= "tcx_afx",
633 .qdev
.size
= sizeof(SysBusDevice
),
636 static void afx_register_devices(void)
638 sysbus_register_withprop(&afx_info
);
641 device_init(afx_register_devices
);
643 /* Boot PROM (OpenBIOS) */
644 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
646 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
647 return addr
+ *base_addr
- PROM_VADDR
;
650 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
657 dev
= qdev_create(NULL
, "openprom");
658 qdev_init_nofail(dev
);
659 s
= sysbus_from_qdev(dev
);
661 sysbus_mmio_map(s
, 0, addr
);
664 if (bios_name
== NULL
) {
665 bios_name
= PROM_FILENAME
;
667 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
669 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
670 NULL
, NULL
, 1, ELF_MACHINE
, 0);
671 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
672 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
678 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
679 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
684 static int prom_init1(SysBusDevice
*dev
)
686 ram_addr_t prom_offset
;
688 prom_offset
= qemu_ram_alloc(PROM_SIZE_MAX
);
689 sysbus_init_mmio(dev
, PROM_SIZE_MAX
, prom_offset
| IO_MEM_ROM
);
693 static SysBusDeviceInfo prom_info
= {
695 .qdev
.name
= "openprom",
696 .qdev
.size
= sizeof(SysBusDevice
),
697 .qdev
.props
= (Property
[]) {
698 {/* end of property list */}
702 static void prom_register_devices(void)
704 sysbus_register_withprop(&prom_info
);
707 device_init(prom_register_devices
);
709 typedef struct RamDevice
716 static int ram_init1(SysBusDevice
*dev
)
718 ram_addr_t RAM_size
, ram_offset
;
719 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
723 ram_offset
= qemu_ram_alloc(RAM_size
);
724 sysbus_init_mmio(dev
, RAM_size
, ram_offset
);
728 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
736 if ((uint64_t)RAM_size
> max_mem
) {
738 "qemu: Too much memory for this machine: %d, maximum %d\n",
739 (unsigned int)(RAM_size
/ (1024 * 1024)),
740 (unsigned int)(max_mem
/ (1024 * 1024)));
743 dev
= qdev_create(NULL
, "memory");
744 s
= sysbus_from_qdev(dev
);
746 d
= FROM_SYSBUS(RamDevice
, s
);
748 qdev_init_nofail(dev
);
750 sysbus_mmio_map(s
, 0, addr
);
753 static SysBusDeviceInfo ram_info
= {
755 .qdev
.name
= "memory",
756 .qdev
.size
= sizeof(RamDevice
),
757 .qdev
.props
= (Property
[]) {
758 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
759 DEFINE_PROP_END_OF_LIST(),
763 static void ram_register_devices(void)
765 sysbus_register_withprop(&ram_info
);
768 device_init(ram_register_devices
);
770 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
771 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
775 env
= cpu_init(cpu_model
);
777 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
781 cpu_sparc_set_id(env
, id
);
783 qemu_register_reset(main_cpu_reset
, env
);
785 qemu_register_reset(secondary_cpu_reset
, env
);
788 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
789 env
->prom_addr
= prom_addr
;
792 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
793 const char *boot_device
,
794 const char *kernel_filename
,
795 const char *kernel_cmdline
,
796 const char *initrd_filename
, const char *cpu_model
)
799 void *iommu
, *espdma
, *ledma
, *nvram
;
800 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
801 espdma_irq
, ledma_irq
;
805 unsigned long kernel_size
;
806 DriveInfo
*fd
[MAX_FD
];
811 cpu_model
= hwdef
->default_cpu_model
;
813 for(i
= 0; i
< smp_cpus
; i
++) {
814 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
817 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
818 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
822 ram_init(0, RAM_size
, hwdef
->max_mem
);
824 prom_init(hwdef
->slavio_base
, bios_name
);
826 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
827 hwdef
->intctl_base
+ 0x10000ULL
,
830 for (i
= 0; i
< 32; i
++) {
831 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
833 for (i
= 0; i
< MAX_CPUS
; i
++) {
834 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
837 if (hwdef
->idreg_base
) {
838 idreg_init(hwdef
->idreg_base
);
841 if (hwdef
->afx_base
) {
842 afx_init(hwdef
->afx_base
);
845 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
848 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
851 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
852 slavio_irq
[16], iommu
, &ledma_irq
);
854 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
855 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
858 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
861 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
863 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
865 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
867 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
868 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
869 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
870 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
871 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
872 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
874 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
875 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
876 slavio_irq
[30], fdc_tc
);
878 if (hwdef
->apc_base
) {
879 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
882 if (hwdef
->fd_base
) {
883 /* there is zero or one floppy drive */
884 memset(fd
, 0, sizeof(fd
));
885 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
886 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
890 if (drive_get_max_bus(IF_SCSI
) > 0) {
891 fprintf(stderr
, "qemu: too many SCSI bus\n");
895 esp_reset
= qdev_get_gpio_in(espdma
, 0);
896 esp_init(hwdef
->esp_base
, 2,
897 espdma_memory_read
, espdma_memory_write
,
898 espdma
, espdma_irq
, &esp_reset
);
901 if (hwdef
->cs_base
) {
902 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
906 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
909 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
910 boot_device
, RAM_size
, kernel_size
, graphic_width
,
911 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
915 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
918 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
919 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
920 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
921 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
922 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
923 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
924 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
925 if (kernel_cmdline
) {
926 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
927 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
928 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
929 (uint8_t*)strdup(kernel_cmdline
),
930 strlen(kernel_cmdline
) + 1);
932 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
934 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
935 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
936 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
937 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
955 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
958 .iommu_base
= 0x10000000,
959 .tcx_base
= 0x50000000,
960 .cs_base
= 0x6c000000,
961 .slavio_base
= 0x70000000,
962 .ms_kb_base
= 0x71000000,
963 .serial_base
= 0x71100000,
964 .nvram_base
= 0x71200000,
965 .fd_base
= 0x71400000,
966 .counter_base
= 0x71d00000,
967 .intctl_base
= 0x71e00000,
968 .idreg_base
= 0x78000000,
969 .dma_base
= 0x78400000,
970 .esp_base
= 0x78800000,
971 .le_base
= 0x78c00000,
972 .apc_base
= 0x6a000000,
973 .afx_base
= 0x6e000000,
974 .aux1_base
= 0x71900000,
975 .aux2_base
= 0x71910000,
976 .nvram_machine_id
= 0x80,
977 .machine_id
= ss5_id
,
978 .iommu_version
= 0x05000000,
979 .max_mem
= 0x10000000,
980 .default_cpu_model
= "Fujitsu MB86904",
984 .iommu_base
= 0xfe0000000ULL
,
985 .tcx_base
= 0xe20000000ULL
,
986 .slavio_base
= 0xff0000000ULL
,
987 .ms_kb_base
= 0xff1000000ULL
,
988 .serial_base
= 0xff1100000ULL
,
989 .nvram_base
= 0xff1200000ULL
,
990 .fd_base
= 0xff1700000ULL
,
991 .counter_base
= 0xff1300000ULL
,
992 .intctl_base
= 0xff1400000ULL
,
993 .idreg_base
= 0xef0000000ULL
,
994 .dma_base
= 0xef0400000ULL
,
995 .esp_base
= 0xef0800000ULL
,
996 .le_base
= 0xef0c00000ULL
,
997 .apc_base
= 0xefa000000ULL
, // XXX should not exist
998 .aux1_base
= 0xff1800000ULL
,
999 .aux2_base
= 0xff1a01000ULL
,
1000 .ecc_base
= 0xf00000000ULL
,
1001 .ecc_version
= 0x10000000, // version 0, implementation 1
1002 .nvram_machine_id
= 0x72,
1003 .machine_id
= ss10_id
,
1004 .iommu_version
= 0x03000000,
1005 .max_mem
= 0xf00000000ULL
,
1006 .default_cpu_model
= "TI SuperSparc II",
1010 .iommu_base
= 0xfe0000000ULL
,
1011 .tcx_base
= 0xe20000000ULL
,
1012 .slavio_base
= 0xff0000000ULL
,
1013 .ms_kb_base
= 0xff1000000ULL
,
1014 .serial_base
= 0xff1100000ULL
,
1015 .nvram_base
= 0xff1200000ULL
,
1016 .counter_base
= 0xff1300000ULL
,
1017 .intctl_base
= 0xff1400000ULL
,
1018 .dma_base
= 0xef0081000ULL
,
1019 .esp_base
= 0xef0080000ULL
,
1020 .le_base
= 0xef0060000ULL
,
1021 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1022 .aux1_base
= 0xff1800000ULL
,
1023 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1024 .ecc_base
= 0xf00000000ULL
,
1025 .ecc_version
= 0x00000000, // version 0, implementation 0
1026 .nvram_machine_id
= 0x71,
1027 .machine_id
= ss600mp_id
,
1028 .iommu_version
= 0x01000000,
1029 .max_mem
= 0xf00000000ULL
,
1030 .default_cpu_model
= "TI SuperSparc II",
1034 .iommu_base
= 0xfe0000000ULL
,
1035 .tcx_base
= 0xe20000000ULL
,
1036 .slavio_base
= 0xff0000000ULL
,
1037 .ms_kb_base
= 0xff1000000ULL
,
1038 .serial_base
= 0xff1100000ULL
,
1039 .nvram_base
= 0xff1200000ULL
,
1040 .fd_base
= 0xff1700000ULL
,
1041 .counter_base
= 0xff1300000ULL
,
1042 .intctl_base
= 0xff1400000ULL
,
1043 .idreg_base
= 0xef0000000ULL
,
1044 .dma_base
= 0xef0400000ULL
,
1045 .esp_base
= 0xef0800000ULL
,
1046 .le_base
= 0xef0c00000ULL
,
1047 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1048 .aux1_base
= 0xff1800000ULL
,
1049 .aux2_base
= 0xff1a01000ULL
,
1050 .ecc_base
= 0xf00000000ULL
,
1051 .ecc_version
= 0x20000000, // version 0, implementation 2
1052 .nvram_machine_id
= 0x72,
1053 .machine_id
= ss20_id
,
1054 .iommu_version
= 0x13000000,
1055 .max_mem
= 0xf00000000ULL
,
1056 .default_cpu_model
= "TI SuperSparc II",
1060 .iommu_base
= 0x10000000,
1061 .tcx_base
= 0x50000000,
1062 .slavio_base
= 0x70000000,
1063 .ms_kb_base
= 0x71000000,
1064 .serial_base
= 0x71100000,
1065 .nvram_base
= 0x71200000,
1066 .fd_base
= 0x71400000,
1067 .counter_base
= 0x71d00000,
1068 .intctl_base
= 0x71e00000,
1069 .idreg_base
= 0x78000000,
1070 .dma_base
= 0x78400000,
1071 .esp_base
= 0x78800000,
1072 .le_base
= 0x78c00000,
1073 .apc_base
= 0x71300000, // pmc
1074 .aux1_base
= 0x71900000,
1075 .aux2_base
= 0x71910000,
1076 .nvram_machine_id
= 0x80,
1077 .machine_id
= vger_id
,
1078 .iommu_version
= 0x05000000,
1079 .max_mem
= 0x10000000,
1080 .default_cpu_model
= "Fujitsu MB86904",
1084 .iommu_base
= 0x10000000,
1085 .tcx_base
= 0x50000000,
1086 .slavio_base
= 0x70000000,
1087 .ms_kb_base
= 0x71000000,
1088 .serial_base
= 0x71100000,
1089 .nvram_base
= 0x71200000,
1090 .fd_base
= 0x71400000,
1091 .counter_base
= 0x71d00000,
1092 .intctl_base
= 0x71e00000,
1093 .idreg_base
= 0x78000000,
1094 .dma_base
= 0x78400000,
1095 .esp_base
= 0x78800000,
1096 .le_base
= 0x78c00000,
1097 .aux1_base
= 0x71900000,
1098 .aux2_base
= 0x71910000,
1099 .nvram_machine_id
= 0x80,
1100 .machine_id
= lx_id
,
1101 .iommu_version
= 0x04000000,
1102 .max_mem
= 0x10000000,
1103 .default_cpu_model
= "TI MicroSparc I",
1107 .iommu_base
= 0x10000000,
1108 .tcx_base
= 0x50000000,
1109 .cs_base
= 0x6c000000,
1110 .slavio_base
= 0x70000000,
1111 .ms_kb_base
= 0x71000000,
1112 .serial_base
= 0x71100000,
1113 .nvram_base
= 0x71200000,
1114 .fd_base
= 0x71400000,
1115 .counter_base
= 0x71d00000,
1116 .intctl_base
= 0x71e00000,
1117 .idreg_base
= 0x78000000,
1118 .dma_base
= 0x78400000,
1119 .esp_base
= 0x78800000,
1120 .le_base
= 0x78c00000,
1121 .apc_base
= 0x6a000000,
1122 .aux1_base
= 0x71900000,
1123 .aux2_base
= 0x71910000,
1124 .nvram_machine_id
= 0x80,
1125 .machine_id
= ss4_id
,
1126 .iommu_version
= 0x05000000,
1127 .max_mem
= 0x10000000,
1128 .default_cpu_model
= "Fujitsu MB86904",
1132 .iommu_base
= 0x10000000,
1133 .tcx_base
= 0x50000000,
1134 .slavio_base
= 0x70000000,
1135 .ms_kb_base
= 0x71000000,
1136 .serial_base
= 0x71100000,
1137 .nvram_base
= 0x71200000,
1138 .fd_base
= 0x71400000,
1139 .counter_base
= 0x71d00000,
1140 .intctl_base
= 0x71e00000,
1141 .idreg_base
= 0x78000000,
1142 .dma_base
= 0x78400000,
1143 .esp_base
= 0x78800000,
1144 .le_base
= 0x78c00000,
1145 .apc_base
= 0x6a000000,
1146 .aux1_base
= 0x71900000,
1147 .aux2_base
= 0x71910000,
1148 .nvram_machine_id
= 0x80,
1149 .machine_id
= scls_id
,
1150 .iommu_version
= 0x05000000,
1151 .max_mem
= 0x10000000,
1152 .default_cpu_model
= "TI MicroSparc I",
1156 .iommu_base
= 0x10000000,
1157 .tcx_base
= 0x50000000, // XXX
1158 .slavio_base
= 0x70000000,
1159 .ms_kb_base
= 0x71000000,
1160 .serial_base
= 0x71100000,
1161 .nvram_base
= 0x71200000,
1162 .fd_base
= 0x71400000,
1163 .counter_base
= 0x71d00000,
1164 .intctl_base
= 0x71e00000,
1165 .idreg_base
= 0x78000000,
1166 .dma_base
= 0x78400000,
1167 .esp_base
= 0x78800000,
1168 .le_base
= 0x78c00000,
1169 .apc_base
= 0x6a000000,
1170 .aux1_base
= 0x71900000,
1171 .aux2_base
= 0x71910000,
1172 .nvram_machine_id
= 0x80,
1173 .machine_id
= sbook_id
,
1174 .iommu_version
= 0x05000000,
1175 .max_mem
= 0x10000000,
1176 .default_cpu_model
= "TI MicroSparc I",
1180 /* SPARCstation 5 hardware initialisation */
1181 static void ss5_init(ram_addr_t RAM_size
,
1182 const char *boot_device
,
1183 const char *kernel_filename
, const char *kernel_cmdline
,
1184 const char *initrd_filename
, const char *cpu_model
)
1186 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1187 kernel_cmdline
, initrd_filename
, cpu_model
);
1190 /* SPARCstation 10 hardware initialisation */
1191 static void ss10_init(ram_addr_t RAM_size
,
1192 const char *boot_device
,
1193 const char *kernel_filename
, const char *kernel_cmdline
,
1194 const char *initrd_filename
, const char *cpu_model
)
1196 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1197 kernel_cmdline
, initrd_filename
, cpu_model
);
1200 /* SPARCserver 600MP hardware initialisation */
1201 static void ss600mp_init(ram_addr_t RAM_size
,
1202 const char *boot_device
,
1203 const char *kernel_filename
,
1204 const char *kernel_cmdline
,
1205 const char *initrd_filename
, const char *cpu_model
)
1207 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1208 kernel_cmdline
, initrd_filename
, cpu_model
);
1211 /* SPARCstation 20 hardware initialisation */
1212 static void ss20_init(ram_addr_t RAM_size
,
1213 const char *boot_device
,
1214 const char *kernel_filename
, const char *kernel_cmdline
,
1215 const char *initrd_filename
, const char *cpu_model
)
1217 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1218 kernel_cmdline
, initrd_filename
, cpu_model
);
1221 /* SPARCstation Voyager hardware initialisation */
1222 static void vger_init(ram_addr_t RAM_size
,
1223 const char *boot_device
,
1224 const char *kernel_filename
, const char *kernel_cmdline
,
1225 const char *initrd_filename
, const char *cpu_model
)
1227 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1228 kernel_cmdline
, initrd_filename
, cpu_model
);
1231 /* SPARCstation LX hardware initialisation */
1232 static void ss_lx_init(ram_addr_t RAM_size
,
1233 const char *boot_device
,
1234 const char *kernel_filename
, const char *kernel_cmdline
,
1235 const char *initrd_filename
, const char *cpu_model
)
1237 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1238 kernel_cmdline
, initrd_filename
, cpu_model
);
1241 /* SPARCstation 4 hardware initialisation */
1242 static void ss4_init(ram_addr_t RAM_size
,
1243 const char *boot_device
,
1244 const char *kernel_filename
, const char *kernel_cmdline
,
1245 const char *initrd_filename
, const char *cpu_model
)
1247 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1248 kernel_cmdline
, initrd_filename
, cpu_model
);
1251 /* SPARCClassic hardware initialisation */
1252 static void scls_init(ram_addr_t RAM_size
,
1253 const char *boot_device
,
1254 const char *kernel_filename
, const char *kernel_cmdline
,
1255 const char *initrd_filename
, const char *cpu_model
)
1257 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1258 kernel_cmdline
, initrd_filename
, cpu_model
);
1261 /* SPARCbook hardware initialisation */
1262 static void sbook_init(ram_addr_t RAM_size
,
1263 const char *boot_device
,
1264 const char *kernel_filename
, const char *kernel_cmdline
,
1265 const char *initrd_filename
, const char *cpu_model
)
1267 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1268 kernel_cmdline
, initrd_filename
, cpu_model
);
1271 static QEMUMachine ss5_machine
= {
1273 .desc
= "Sun4m platform, SPARCstation 5",
1279 static QEMUMachine ss10_machine
= {
1281 .desc
= "Sun4m platform, SPARCstation 10",
1287 static QEMUMachine ss600mp_machine
= {
1289 .desc
= "Sun4m platform, SPARCserver 600MP",
1290 .init
= ss600mp_init
,
1295 static QEMUMachine ss20_machine
= {
1297 .desc
= "Sun4m platform, SPARCstation 20",
1303 static QEMUMachine voyager_machine
= {
1305 .desc
= "Sun4m platform, SPARCstation Voyager",
1310 static QEMUMachine ss_lx_machine
= {
1312 .desc
= "Sun4m platform, SPARCstation LX",
1317 static QEMUMachine ss4_machine
= {
1319 .desc
= "Sun4m platform, SPARCstation 4",
1324 static QEMUMachine scls_machine
= {
1325 .name
= "SPARCClassic",
1326 .desc
= "Sun4m platform, SPARCClassic",
1331 static QEMUMachine sbook_machine
= {
1332 .name
= "SPARCbook",
1333 .desc
= "Sun4m platform, SPARCbook",
1338 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1348 .tcx_base
= 0x820000000ULL
,
1349 .slavio_base
= 0xf00000000ULL
,
1350 .ms_kb_base
= 0xf00240000ULL
,
1351 .serial_base
= 0xf00200000ULL
,
1352 .nvram_base
= 0xf00280000ULL
,
1353 .counter_base
= 0xf00300000ULL
,
1354 .espdma_base
= 0x800081000ULL
,
1355 .esp_base
= 0x800080000ULL
,
1356 .ledma_base
= 0x800040000ULL
,
1357 .le_base
= 0x800060000ULL
,
1358 .sbi_base
= 0xf02800000ULL
,
1359 .nvram_machine_id
= 0x80,
1360 .machine_id
= ss1000_id
,
1361 .iounit_version
= 0x03000000,
1362 .max_mem
= 0xf00000000ULL
,
1363 .default_cpu_model
= "TI SuperSparc II",
1374 .tcx_base
= 0x820000000ULL
,
1375 .slavio_base
= 0xf00000000ULL
,
1376 .ms_kb_base
= 0xf00240000ULL
,
1377 .serial_base
= 0xf00200000ULL
,
1378 .nvram_base
= 0xf00280000ULL
,
1379 .counter_base
= 0xf00300000ULL
,
1380 .espdma_base
= 0x800081000ULL
,
1381 .esp_base
= 0x800080000ULL
,
1382 .ledma_base
= 0x800040000ULL
,
1383 .le_base
= 0x800060000ULL
,
1384 .sbi_base
= 0xf02800000ULL
,
1385 .nvram_machine_id
= 0x80,
1386 .machine_id
= ss2000_id
,
1387 .iounit_version
= 0x03000000,
1388 .max_mem
= 0xf00000000ULL
,
1389 .default_cpu_model
= "TI SuperSparc II",
1393 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1399 dev
= qdev_create(NULL
, "sbi");
1400 qdev_init_nofail(dev
);
1402 s
= sysbus_from_qdev(dev
);
1404 for (i
= 0; i
< MAX_CPUS
; i
++) {
1405 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1408 sysbus_mmio_map(s
, 0, addr
);
1413 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1414 const char *boot_device
,
1415 const char *kernel_filename
,
1416 const char *kernel_cmdline
,
1417 const char *initrd_filename
, const char *cpu_model
)
1420 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1421 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1422 espdma_irq
, ledma_irq
;
1424 unsigned long kernel_size
;
1430 cpu_model
= hwdef
->default_cpu_model
;
1432 for(i
= 0; i
< smp_cpus
; i
++) {
1433 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1436 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1437 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1439 /* set up devices */
1440 ram_init(0, RAM_size
, hwdef
->max_mem
);
1442 prom_init(hwdef
->slavio_base
, bios_name
);
1444 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1446 for (i
= 0; i
< 32; i
++) {
1447 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1449 for (i
= 0; i
< MAX_CPUS
; i
++) {
1450 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1453 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1454 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1455 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1456 hwdef
->iounit_version
,
1459 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1460 iounits
[0], &espdma_irq
);
1462 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1463 iounits
[0], &ledma_irq
);
1465 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1466 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1469 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1472 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1474 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1476 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1478 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1479 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1480 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1481 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1482 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1483 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1485 if (drive_get_max_bus(IF_SCSI
) > 0) {
1486 fprintf(stderr
, "qemu: too many SCSI bus\n");
1490 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1491 esp_init(hwdef
->esp_base
, 2,
1492 espdma_memory_read
, espdma_memory_write
,
1493 espdma
, espdma_irq
, &esp_reset
);
1495 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1498 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1499 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1500 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1503 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1504 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1505 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1506 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1507 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1508 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1509 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1510 if (kernel_cmdline
) {
1511 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1512 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1513 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1514 (uint8_t*)strdup(kernel_cmdline
),
1515 strlen(kernel_cmdline
) + 1);
1517 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1519 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1520 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1521 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1522 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1525 /* SPARCserver 1000 hardware initialisation */
1526 static void ss1000_init(ram_addr_t RAM_size
,
1527 const char *boot_device
,
1528 const char *kernel_filename
, const char *kernel_cmdline
,
1529 const char *initrd_filename
, const char *cpu_model
)
1531 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1532 kernel_cmdline
, initrd_filename
, cpu_model
);
1535 /* SPARCcenter 2000 hardware initialisation */
1536 static void ss2000_init(ram_addr_t RAM_size
,
1537 const char *boot_device
,
1538 const char *kernel_filename
, const char *kernel_cmdline
,
1539 const char *initrd_filename
, const char *cpu_model
)
1541 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1542 kernel_cmdline
, initrd_filename
, cpu_model
);
1545 static QEMUMachine ss1000_machine
= {
1547 .desc
= "Sun4d platform, SPARCserver 1000",
1548 .init
= ss1000_init
,
1553 static QEMUMachine ss2000_machine
= {
1555 .desc
= "Sun4d platform, SPARCcenter 2000",
1556 .init
= ss2000_init
,
1561 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1564 .iommu_base
= 0xf8000000,
1565 .tcx_base
= 0xfe000000,
1566 .slavio_base
= 0xf6000000,
1567 .intctl_base
= 0xf5000000,
1568 .counter_base
= 0xf3000000,
1569 .ms_kb_base
= 0xf0000000,
1570 .serial_base
= 0xf1000000,
1571 .nvram_base
= 0xf2000000,
1572 .fd_base
= 0xf7200000,
1573 .dma_base
= 0xf8400000,
1574 .esp_base
= 0xf8800000,
1575 .le_base
= 0xf8c00000,
1576 .aux1_base
= 0xf7400003,
1577 .nvram_machine_id
= 0x55,
1578 .machine_id
= ss2_id
,
1579 .max_mem
= 0x10000000,
1580 .default_cpu_model
= "Cypress CY7C601",
1584 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1585 qemu_irq
*parent_irq
)
1591 dev
= qdev_create(NULL
, "sun4c_intctl");
1592 qdev_init_nofail(dev
);
1594 s
= sysbus_from_qdev(dev
);
1596 for (i
= 0; i
< MAX_PILS
; i
++) {
1597 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1599 sysbus_mmio_map(s
, 0, addr
);
1604 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1605 const char *boot_device
,
1606 const char *kernel_filename
,
1607 const char *kernel_cmdline
,
1608 const char *initrd_filename
, const char *cpu_model
)
1610 void *iommu
, *espdma
, *ledma
, *nvram
;
1611 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1614 unsigned long kernel_size
;
1615 DriveInfo
*fd
[MAX_FD
];
1622 cpu_model
= hwdef
->default_cpu_model
;
1624 cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1626 /* set up devices */
1627 ram_init(0, RAM_size
, hwdef
->max_mem
);
1629 prom_init(hwdef
->slavio_base
, bios_name
);
1631 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1633 for (i
= 0; i
< 8; i
++) {
1634 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1637 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1640 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1641 iommu
, &espdma_irq
);
1643 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1644 slavio_irq
[3], iommu
, &ledma_irq
);
1646 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1647 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1650 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1653 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1655 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1657 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1658 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1659 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1660 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1661 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1662 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1665 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1667 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1668 /* there is zero or one floppy drive */
1669 memset(fd
, 0, sizeof(fd
));
1670 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1671 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1675 if (drive_get_max_bus(IF_SCSI
) > 0) {
1676 fprintf(stderr
, "qemu: too many SCSI bus\n");
1680 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1681 esp_init(hwdef
->esp_base
, 2,
1682 espdma_memory_read
, espdma_memory_write
,
1683 espdma
, espdma_irq
, &esp_reset
);
1685 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1688 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1689 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1690 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1693 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1694 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1695 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1696 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1697 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1698 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1699 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1700 if (kernel_cmdline
) {
1701 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1702 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1703 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1704 (uint8_t*)strdup(kernel_cmdline
),
1705 strlen(kernel_cmdline
) + 1);
1707 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1709 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1710 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1711 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1712 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1715 /* SPARCstation 2 hardware initialisation */
1716 static void ss2_init(ram_addr_t RAM_size
,
1717 const char *boot_device
,
1718 const char *kernel_filename
, const char *kernel_cmdline
,
1719 const char *initrd_filename
, const char *cpu_model
)
1721 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1722 kernel_cmdline
, initrd_filename
, cpu_model
);
1725 static QEMUMachine ss2_machine
= {
1727 .desc
= "Sun4c platform, SPARCstation 2",
1732 static void ss2_machine_init(void)
1734 qemu_register_machine(&ss5_machine
);
1735 qemu_register_machine(&ss10_machine
);
1736 qemu_register_machine(&ss600mp_machine
);
1737 qemu_register_machine(&ss20_machine
);
1738 qemu_register_machine(&voyager_machine
);
1739 qemu_register_machine(&ss_lx_machine
);
1740 qemu_register_machine(&ss4_machine
);
1741 qemu_register_machine(&scls_machine
);
1742 qemu_register_machine(&sbook_machine
);
1743 qemu_register_machine(&ss1000_machine
);
1744 qemu_register_machine(&ss2000_machine
);
1745 qemu_register_machine(&ss2_machine
);
1748 machine_init(ss2_machine_init
);