hw/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef hw_omap_h
  20 #include "memory.h"
  21 # define hw_omap_h              "omap.h"
  22
  23 # define OMAP_EMIFS_BASE        0x00000000
  24 # define OMAP2_Q0_BASE          0x00000000
  25 # define OMAP_CS0_BASE          0x00000000
  26 # define OMAP_CS1_BASE          0x04000000
  27 # define OMAP_CS2_BASE          0x08000000
  28 # define OMAP_CS3_BASE          0x0c000000
  29 # define OMAP_EMIFF_BASE        0x10000000
  30 # define OMAP_IMIF_BASE         0x20000000
  31 # define OMAP_LOCALBUS_BASE     0x30000000
  32 # define OMAP2_Q1_BASE          0x40000000
  33 # define OMAP2_L4_BASE          0x48000000
  34 # define OMAP2_SRAM_BASE        0x40200000
  35 # define OMAP2_L3_BASE          0x68000000
  36 # define OMAP2_Q2_BASE          0x80000000
  37 # define OMAP2_Q3_BASE          0xc0000000
  38 # define OMAP_MPUI_BASE         0xe1000000
  39
  40 # define OMAP730_SRAM_SIZE      0x00032000
  41 # define OMAP15XX_SRAM_SIZE     0x00030000
  42 # define OMAP16XX_SRAM_SIZE     0x00004000
  43 # define OMAP1611_SRAM_SIZE     0x0003e800
  44 # define OMAP242X_SRAM_SIZE     0x000a0000
  45 # define OMAP243X_SRAM_SIZE     0x00010000
  46 # define OMAP_CS0_SIZE          0x04000000
  47 # define OMAP_CS1_SIZE          0x04000000
  48 # define OMAP_CS2_SIZE          0x04000000
  49 # define OMAP_CS3_SIZE          0x04000000
  50
  51 /* omap_clk.c */
  52 struct omap_mpu_state_s;
  53 typedef struct clk *omap_clk;
  54 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  55 void omap_clk_init(struct omap_mpu_state_s *mpu);
  56 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  57 void omap_clk_get(omap_clk clk);
  58 void omap_clk_put(omap_clk clk);
  59 void omap_clk_onoff(omap_clk clk, int on);
  60 void omap_clk_canidle(omap_clk clk, int can);
  61 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  62 int64_t omap_clk_getrate(omap_clk clk);
  63 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  64
  65 /* OMAP2 l4 Interconnect */
  66 struct omap_l4_s;
  67 struct omap_l4_region_s {
  68     target_phys_addr_t offset;
  69     size_t size;
  70     int access;
  71 };
  72 struct omap_l4_agent_info_s {
  73     int ta;
  74     int region;
  75     int regions;
  76     int ta_region;
  77 };
  78 struct omap_target_agent_s {
  79     MemoryRegion iomem;
  80     struct omap_l4_s *bus;
  81     int regions;
  82     const struct omap_l4_region_s *start;
  83     target_phys_addr_t base;
  84     uint32_t component;
  85     uint32_t control;
  86     uint32_t status;
  87 };
  88 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
  89                                target_phys_addr_t base, int ta_num);
  90
  91 struct omap_target_agent_s;
  92 struct omap_target_agent_s *omap_l4ta_get(
  93     struct omap_l4_s *bus,
  94     const struct omap_l4_region_s *regions,
  95     const struct omap_l4_agent_info_s *agents,
  96     int cs);
  97 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
  98                                          int region, MemoryRegion *mr);
  99 target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
 100                                        int region);
 101 target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
 102                                        int region);
 103
 104 /* OMAP2 SDRAM controller */
 105 struct omap_sdrc_s;
 106 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
 107                                    target_phys_addr_t base);
 108 void omap_sdrc_reset(struct omap_sdrc_s *s);
 109
 110 /* OMAP2 general purpose memory controller */
 111 struct omap_gpmc_s;
 112 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 113                                    target_phys_addr_t base,
 114                                    qemu_irq irq, qemu_irq drq);
 115 void omap_gpmc_reset(struct omap_gpmc_s *s);
 116 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
 117 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
 118
 119 /*
 120  * Common IRQ numbers for level 1 interrupt handler
 121  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 122  */
 123 # define OMAP_INT_CAMERA                1
 124 # define OMAP_INT_FIQ                   3
 125 # define OMAP_INT_RTDX                  6
 126 # define OMAP_INT_DSP_MMU_ABORT         7
 127 # define OMAP_INT_HOST                  8
 128 # define OMAP_INT_ABORT                 9
 129 # define OMAP_INT_BRIDGE_PRIV           13
 130 # define OMAP_INT_GPIO_BANK1            14
 131 # define OMAP_INT_UART3                 15
 132 # define OMAP_INT_TIMER3                16
 133 # define OMAP_INT_DMA_CH0_6             19
 134 # define OMAP_INT_DMA_CH1_7             20
 135 # define OMAP_INT_DMA_CH2_8             21
 136 # define OMAP_INT_DMA_CH3               22
 137 # define OMAP_INT_DMA_CH4               23
 138 # define OMAP_INT_DMA_CH5               24
 139 # define OMAP_INT_DMA_LCD               25
 140 # define OMAP_INT_TIMER1                26
 141 # define OMAP_INT_WD_TIMER              27
 142 # define OMAP_INT_BRIDGE_PUB            28
 143 # define OMAP_INT_TIMER2                30
 144 # define OMAP_INT_LCD_CTRL              31
 145
 146 /*
 147  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 148  */
 149 # define OMAP_INT_15XX_IH2_IRQ          0
 150 # define OMAP_INT_15XX_LB_MMU           17
 151 # define OMAP_INT_15XX_LOCAL_BUS        29
 152
 153 /*
 154  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 155  */
 156 # define OMAP_INT_1510_SPI_TX           4
 157 # define OMAP_INT_1510_SPI_RX           5
 158 # define OMAP_INT_1510_DSP_MAILBOX1     10
 159 # define OMAP_INT_1510_DSP_MAILBOX2     11
 160
 161 /*
 162  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 163  */
 164 # define OMAP_INT_310_McBSP2_TX         4
 165 # define OMAP_INT_310_McBSP2_RX         5
 166 # define OMAP_INT_310_HSB_MAILBOX1      12
 167 # define OMAP_INT_310_HSAB_MMU          18
 168
 169 /*
 170  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 171  */
 172 # define OMAP_INT_1610_IH2_IRQ          0
 173 # define OMAP_INT_1610_IH2_FIQ          2
 174 # define OMAP_INT_1610_McBSP2_TX        4
 175 # define OMAP_INT_1610_McBSP2_RX        5
 176 # define OMAP_INT_1610_DSP_MAILBOX1     10
 177 # define OMAP_INT_1610_DSP_MAILBOX2     11
 178 # define OMAP_INT_1610_LCD_LINE         12
 179 # define OMAP_INT_1610_GPTIMER1         17
 180 # define OMAP_INT_1610_GPTIMER2         18
 181 # define OMAP_INT_1610_SSR_FIFO_0       29
 182
 183 /*
 184  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 185  */
 186 # define OMAP_INT_730_IH2_FIQ           0
 187 # define OMAP_INT_730_IH2_IRQ           1
 188 # define OMAP_INT_730_USB_NON_ISO       2
 189 # define OMAP_INT_730_USB_ISO           3
 190 # define OMAP_INT_730_ICR               4
 191 # define OMAP_INT_730_EAC               5
 192 # define OMAP_INT_730_GPIO_BANK1        6
 193 # define OMAP_INT_730_GPIO_BANK2        7
 194 # define OMAP_INT_730_GPIO_BANK3        8
 195 # define OMAP_INT_730_McBSP2TX          10
 196 # define OMAP_INT_730_McBSP2RX          11
 197 # define OMAP_INT_730_McBSP2RX_OVF      12
 198 # define OMAP_INT_730_LCD_LINE          14
 199 # define OMAP_INT_730_GSM_PROTECT       15
 200 # define OMAP_INT_730_TIMER3            16
 201 # define OMAP_INT_730_GPIO_BANK5        17
 202 # define OMAP_INT_730_GPIO_BANK6        18
 203 # define OMAP_INT_730_SPGIO_WR          29
 204
 205 /*
 206  * Common IRQ numbers for level 2 interrupt handler
 207  */
 208 # define OMAP_INT_KEYBOARD              1
 209 # define OMAP_INT_uWireTX               2
 210 # define OMAP_INT_uWireRX               3
 211 # define OMAP_INT_I2C                   4
 212 # define OMAP_INT_MPUIO                 5
 213 # define OMAP_INT_USB_HHC_1             6
 214 # define OMAP_INT_McBSP3TX              10
 215 # define OMAP_INT_McBSP3RX              11
 216 # define OMAP_INT_McBSP1TX              12
 217 # define OMAP_INT_McBSP1RX              13
 218 # define OMAP_INT_UART1                 14
 219 # define OMAP_INT_UART2                 15
 220 # define OMAP_INT_USB_W2FC              20
 221 # define OMAP_INT_1WIRE                 21
 222 # define OMAP_INT_OS_TIMER              22
 223 # define OMAP_INT_OQN                   23
 224 # define OMAP_INT_GAUGE_32K             24
 225 # define OMAP_INT_RTC_TIMER             25
 226 # define OMAP_INT_RTC_ALARM             26
 227 # define OMAP_INT_DSP_MMU               28
 228
 229 /*
 230  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 231  */
 232 # define OMAP_INT_1510_BT_MCSI1TX       16
 233 # define OMAP_INT_1510_BT_MCSI1RX       17
 234 # define OMAP_INT_1510_SoSSI_MATCH      19
 235 # define OMAP_INT_1510_MEM_STICK        27
 236 # define OMAP_INT_1510_COM_SPI_RO       31
 237
 238 /*
 239  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 240  */
 241 # define OMAP_INT_310_FAC               0
 242 # define OMAP_INT_310_USB_HHC_2         7
 243 # define OMAP_INT_310_MCSI1_FE          16
 244 # define OMAP_INT_310_MCSI2_FE          17
 245 # define OMAP_INT_310_USB_W2FC_ISO      29
 246 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 247 # define OMAP_INT_310_McBSP2RX_OF       31
 248
 249 /*
 250  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 251  */
 252 # define OMAP_INT_1610_FAC              0
 253 # define OMAP_INT_1610_USB_HHC_2        7
 254 # define OMAP_INT_1610_USB_OTG          8
 255 # define OMAP_INT_1610_SoSSI            9
 256 # define OMAP_INT_1610_BT_MCSI1TX       16
 257 # define OMAP_INT_1610_BT_MCSI1RX       17
 258 # define OMAP_INT_1610_SoSSI_MATCH      19
 259 # define OMAP_INT_1610_MEM_STICK        27
 260 # define OMAP_INT_1610_McBSP2RX_OF      31
 261 # define OMAP_INT_1610_STI              32
 262 # define OMAP_INT_1610_STI_WAKEUP       33
 263 # define OMAP_INT_1610_GPTIMER3         34
 264 # define OMAP_INT_1610_GPTIMER4         35
 265 # define OMAP_INT_1610_GPTIMER5         36
 266 # define OMAP_INT_1610_GPTIMER6         37
 267 # define OMAP_INT_1610_GPTIMER7         38
 268 # define OMAP_INT_1610_GPTIMER8         39
 269 # define OMAP_INT_1610_GPIO_BANK2       40
 270 # define OMAP_INT_1610_GPIO_BANK3       41
 271 # define OMAP_INT_1610_MMC2             42
 272 # define OMAP_INT_1610_CF               43
 273 # define OMAP_INT_1610_WAKE_UP_REQ      46
 274 # define OMAP_INT_1610_GPIO_BANK4       48
 275 # define OMAP_INT_1610_SPI              49
 276 # define OMAP_INT_1610_DMA_CH6          53
 277 # define OMAP_INT_1610_DMA_CH7          54
 278 # define OMAP_INT_1610_DMA_CH8          55
 279 # define OMAP_INT_1610_DMA_CH9          56
 280 # define OMAP_INT_1610_DMA_CH10         57
 281 # define OMAP_INT_1610_DMA_CH11         58
 282 # define OMAP_INT_1610_DMA_CH12         59
 283 # define OMAP_INT_1610_DMA_CH13         60
 284 # define OMAP_INT_1610_DMA_CH14         61
 285 # define OMAP_INT_1610_DMA_CH15         62
 286 # define OMAP_INT_1610_NAND             63
 287
 288 /*
 289  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 290  */
 291 # define OMAP_INT_730_HW_ERRORS         0
 292 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 293 # define OMAP_INT_730_CFCD              2
 294 # define OMAP_INT_730_CFIREQ            3
 295 # define OMAP_INT_730_I2C               4
 296 # define OMAP_INT_730_PCC               5
 297 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 298 # define OMAP_INT_730_SPI_100K_1        7
 299 # define OMAP_INT_730_SYREN_SPI         8
 300 # define OMAP_INT_730_VLYNQ             9
 301 # define OMAP_INT_730_GPIO_BANK4        10
 302 # define OMAP_INT_730_McBSP1TX          11
 303 # define OMAP_INT_730_McBSP1RX          12
 304 # define OMAP_INT_730_McBSP1RX_OF       13
 305 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 306 # define OMAP_INT_730_UART_MODEM_1      15
 307 # define OMAP_INT_730_MCSI              16
 308 # define OMAP_INT_730_uWireTX           17
 309 # define OMAP_INT_730_uWireRX           18
 310 # define OMAP_INT_730_SMC_CD            19
 311 # define OMAP_INT_730_SMC_IREQ          20
 312 # define OMAP_INT_730_HDQ_1WIRE         21
 313 # define OMAP_INT_730_TIMER32K          22
 314 # define OMAP_INT_730_MMC_SDIO          23
 315 # define OMAP_INT_730_UPLD              24
 316 # define OMAP_INT_730_USB_HHC_1         27
 317 # define OMAP_INT_730_USB_HHC_2         28
 318 # define OMAP_INT_730_USB_GENI          29
 319 # define OMAP_INT_730_USB_OTG           30
 320 # define OMAP_INT_730_CAMERA_IF         31
 321 # define OMAP_INT_730_RNG               32
 322 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 323 # define OMAP_INT_730_DBB_RF_EN         34
 324 # define OMAP_INT_730_MPUIO_KEYPAD      35
 325 # define OMAP_INT_730_SHA1_MD5          36
 326 # define OMAP_INT_730_SPI_100K_2        37
 327 # define OMAP_INT_730_RNG_IDLE          38
 328 # define OMAP_INT_730_MPUIO             39
 329 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 330 # define OMAP_INT_730_LLPC_OE_FALLING   41
 331 # define OMAP_INT_730_LLPC_OE_RISING    42
 332 # define OMAP_INT_730_LLPC_VSYNC        43
 333 # define OMAP_INT_730_WAKE_UP_REQ       46
 334 # define OMAP_INT_730_DMA_CH6           53
 335 # define OMAP_INT_730_DMA_CH7           54
 336 # define OMAP_INT_730_DMA_CH8           55
 337 # define OMAP_INT_730_DMA_CH9           56
 338 # define OMAP_INT_730_DMA_CH10          57
 339 # define OMAP_INT_730_DMA_CH11          58
 340 # define OMAP_INT_730_DMA_CH12          59
 341 # define OMAP_INT_730_DMA_CH13          60
 342 # define OMAP_INT_730_DMA_CH14          61
 343 # define OMAP_INT_730_DMA_CH15          62
 344 # define OMAP_INT_730_NAND              63
 345
 346 /*
 347  * OMAP-24xx common IRQ numbers
 348  */
 349 # define OMAP_INT_24XX_STI              4
 350 # define OMAP_INT_24XX_SYS_NIRQ         7
 351 # define OMAP_INT_24XX_L3_IRQ           10
 352 # define OMAP_INT_24XX_PRCM_MPU_IRQ     11
 353 # define OMAP_INT_24XX_SDMA_IRQ0        12
 354 # define OMAP_INT_24XX_SDMA_IRQ1        13
 355 # define OMAP_INT_24XX_SDMA_IRQ2        14
 356 # define OMAP_INT_24XX_SDMA_IRQ3        15
 357 # define OMAP_INT_243X_MCBSP2_IRQ       16
 358 # define OMAP_INT_243X_MCBSP3_IRQ       17
 359 # define OMAP_INT_243X_MCBSP4_IRQ       18
 360 # define OMAP_INT_243X_MCBSP5_IRQ       19
 361 # define OMAP_INT_24XX_GPMC_IRQ         20
 362 # define OMAP_INT_24XX_GUFFAW_IRQ       21
 363 # define OMAP_INT_24XX_IVA_IRQ          22
 364 # define OMAP_INT_24XX_EAC_IRQ          23
 365 # define OMAP_INT_24XX_CAM_IRQ          24
 366 # define OMAP_INT_24XX_DSS_IRQ          25
 367 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 368 # define OMAP_INT_24XX_DSP_UMA          27
 369 # define OMAP_INT_24XX_DSP_MMU          28
 370 # define OMAP_INT_24XX_GPIO_BANK1       29
 371 # define OMAP_INT_24XX_GPIO_BANK2       30
 372 # define OMAP_INT_24XX_GPIO_BANK3       31
 373 # define OMAP_INT_24XX_GPIO_BANK4       32
 374 # define OMAP_INT_243X_GPIO_BANK5       33
 375 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 376 # define OMAP_INT_24XX_WDT3             35
 377 # define OMAP_INT_24XX_WDT4             36
 378 # define OMAP_INT_24XX_GPTIMER1         37
 379 # define OMAP_INT_24XX_GPTIMER2         38
 380 # define OMAP_INT_24XX_GPTIMER3         39
 381 # define OMAP_INT_24XX_GPTIMER4         40
 382 # define OMAP_INT_24XX_GPTIMER5         41
 383 # define OMAP_INT_24XX_GPTIMER6         42
 384 # define OMAP_INT_24XX_GPTIMER7         43
 385 # define OMAP_INT_24XX_GPTIMER8         44
 386 # define OMAP_INT_24XX_GPTIMER9         45
 387 # define OMAP_INT_24XX_GPTIMER10        46
 388 # define OMAP_INT_24XX_GPTIMER11        47
 389 # define OMAP_INT_24XX_GPTIMER12        48
 390 # define OMAP_INT_24XX_PKA_IRQ          50
 391 # define OMAP_INT_24XX_SHA1MD5_IRQ      51
 392 # define OMAP_INT_24XX_RNG_IRQ          52
 393 # define OMAP_INT_24XX_MG_IRQ           53
 394 # define OMAP_INT_24XX_I2C1_IRQ         56
 395 # define OMAP_INT_24XX_I2C2_IRQ         57
 396 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 397 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 398 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 399 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 400 # define OMAP_INT_243X_MCBSP1_IRQ       64
 401 # define OMAP_INT_24XX_MCSPI1_IRQ       65
 402 # define OMAP_INT_24XX_MCSPI2_IRQ       66
 403 # define OMAP_INT_24XX_SSI1_IRQ0        67
 404 # define OMAP_INT_24XX_SSI1_IRQ1        68
 405 # define OMAP_INT_24XX_SSI2_IRQ0        69
 406 # define OMAP_INT_24XX_SSI2_IRQ1        70
 407 # define OMAP_INT_24XX_SSI_GDD_IRQ      71
 408 # define OMAP_INT_24XX_UART1_IRQ        72
 409 # define OMAP_INT_24XX_UART2_IRQ        73
 410 # define OMAP_INT_24XX_UART3_IRQ        74
 411 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 412 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 413 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 414 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 415 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 416 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 417 # define OMAP_INT_24XX_VLYNQ_IRQ        81
 418 # define OMAP_INT_24XX_MMC_IRQ          83
 419 # define OMAP_INT_24XX_MS_IRQ           84
 420 # define OMAP_INT_24XX_FAC_IRQ          85
 421 # define OMAP_INT_24XX_MCSPI3_IRQ       91
 422 # define OMAP_INT_243X_HS_USB_MC        92
 423 # define OMAP_INT_243X_HS_USB_DMA       93
 424 # define OMAP_INT_243X_CARKIT           94
 425 # define OMAP_INT_34XX_GPTIMER12        95
 426
 427 /* omap_dma.c */
 428 enum omap_dma_model {
 429     omap_dma_3_0,
 430     omap_dma_3_1,
 431     omap_dma_3_2,
 432     omap_dma_4,
 433 };
 434
 435 struct soc_dma_s;
 436 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
 437                 MemoryRegion *sysmem,
 438                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 439                 enum omap_dma_model model);
 440 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
 441                 MemoryRegion *sysmem,
 442                 struct omap_mpu_state_s *mpu, int fifo,
 443                 int chans, omap_clk iclk, omap_clk fclk);
 444 void omap_dma_reset(struct soc_dma_s *s);
 445
 446 struct dma_irq_map {
 447     int ih;
 448     int intr;
 449 };
 450
 451 /* Only used in OMAP DMA 3.x gigacells */
 452 enum omap_dma_port {
 453     emiff = 0,
 454     emifs,
 455     imif,       /* omap16xx: ocp_t1 */
 456     tipb,
 457     local,      /* omap16xx: ocp_t2 */
 458     tipb_mpui,
 459     __omap_dma_port_last,
 460 };
 461
 462 typedef enum {
 463     constant = 0,
 464     post_incremented,
 465     single_index,
 466     double_index,
 467 } omap_dma_addressing_t;
 468
 469 /* Only used in OMAP DMA 3.x gigacells */
 470 struct omap_dma_lcd_channel_s {
 471     enum omap_dma_port src;
 472     target_phys_addr_t src_f1_top;
 473     target_phys_addr_t src_f1_bottom;
 474     target_phys_addr_t src_f2_top;
 475     target_phys_addr_t src_f2_bottom;
 476
 477     /* Used in OMAP DMA 3.2 gigacell */
 478     unsigned char brust_f1;
 479     unsigned char pack_f1;
 480     unsigned char data_type_f1;
 481     unsigned char brust_f2;
 482     unsigned char pack_f2;
 483     unsigned char data_type_f2;
 484     unsigned char end_prog;
 485     unsigned char repeat;
 486     unsigned char auto_init;
 487     unsigned char priority;
 488     unsigned char fs;
 489     unsigned char running;
 490     unsigned char bs;
 491     unsigned char omap_3_1_compatible_disable;
 492     unsigned char dst;
 493     unsigned char lch_type;
 494     int16_t element_index_f1;
 495     int16_t element_index_f2;
 496     int32_t frame_index_f1;
 497     int32_t frame_index_f2;
 498     uint16_t elements_f1;
 499     uint16_t frames_f1;
 500     uint16_t elements_f2;
 501     uint16_t frames_f2;
 502     omap_dma_addressing_t mode_f1;
 503     omap_dma_addressing_t mode_f2;
 504
 505     /* Destination port is fixed.  */
 506     int interrupts;
 507     int condition;
 508     int dual;
 509
 510     int current_frame;
 511     target_phys_addr_t phys_framebuffer[2];
 512     qemu_irq irq;
 513     struct omap_mpu_state_s *mpu;
 514 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 515
 516 /*
 517  * DMA request numbers for OMAP1
 518  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 519  */
 520 # define OMAP_DMA_NO_DEVICE             0
 521 # define OMAP_DMA_MCSI1_TX              1
 522 # define OMAP_DMA_MCSI1_RX              2
 523 # define OMAP_DMA_I2C_RX                3
 524 # define OMAP_DMA_I2C_TX                4
 525 # define OMAP_DMA_EXT_NDMA_REQ0         5
 526 # define OMAP_DMA_EXT_NDMA_REQ1         6
 527 # define OMAP_DMA_UWIRE_TX              7
 528 # define OMAP_DMA_MCBSP1_TX             8
 529 # define OMAP_DMA_MCBSP1_RX             9
 530 # define OMAP_DMA_MCBSP3_TX             10
 531 # define OMAP_DMA_MCBSP3_RX             11
 532 # define OMAP_DMA_UART1_TX              12
 533 # define OMAP_DMA_UART1_RX              13
 534 # define OMAP_DMA_UART2_TX              14
 535 # define OMAP_DMA_UART2_RX              15
 536 # define OMAP_DMA_MCBSP2_TX             16
 537 # define OMAP_DMA_MCBSP2_RX             17
 538 # define OMAP_DMA_UART3_TX              18
 539 # define OMAP_DMA_UART3_RX              19
 540 # define OMAP_DMA_CAMERA_IF_RX          20
 541 # define OMAP_DMA_MMC_TX                21
 542 # define OMAP_DMA_MMC_RX                22
 543 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 544 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 545 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 546 # define OMAP_DMA_USB_W2FC_RX0          26
 547 # define OMAP_DMA_USB_W2FC_RX1          27
 548 # define OMAP_DMA_USB_W2FC_RX2          28
 549 # define OMAP_DMA_USB_W2FC_TX0          29
 550 # define OMAP_DMA_USB_W2FC_TX1          30
 551 # define OMAP_DMA_USB_W2FC_TX2          31
 552
 553 /* These are only for 1610 */
 554 # define OMAP_DMA_CRYPTO_DES_IN         32
 555 # define OMAP_DMA_SPI_TX                33
 556 # define OMAP_DMA_SPI_RX                34
 557 # define OMAP_DMA_CRYPTO_HASH           35
 558 # define OMAP_DMA_CCP_ATTN              36
 559 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 560 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 561 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 562 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 563 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 564 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 565 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 566 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 567 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 568 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 569 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 570 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 571 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 572 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 573 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 574 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 575 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 576 # define OMAP_DMA_MMC2_TX               54
 577 # define OMAP_DMA_MMC2_RX               55
 578 # define OMAP_DMA_CRYPTO_DES_OUT        56
 579
 580 /*
 581  * DMA request numbers for the OMAP2
 582  */
 583 # define OMAP24XX_DMA_NO_DEVICE         0
 584 # define OMAP24XX_DMA_XTI_DMA           1       /* Not in OMAP2420 */
 585 # define OMAP24XX_DMA_EXT_DMAREQ0       2
 586 # define OMAP24XX_DMA_EXT_DMAREQ1       3
 587 # define OMAP24XX_DMA_GPMC              4
 588 # define OMAP24XX_DMA_GFX               5       /* Not in OMAP2420 */
 589 # define OMAP24XX_DMA_DSS               6
 590 # define OMAP24XX_DMA_VLYNQ_TX          7       /* Not in OMAP2420 */
 591 # define OMAP24XX_DMA_CWT               8       /* Not in OMAP2420 */
 592 # define OMAP24XX_DMA_AES_TX            9       /* Not in OMAP2420 */
 593 # define OMAP24XX_DMA_AES_RX            10      /* Not in OMAP2420 */
 594 # define OMAP24XX_DMA_DES_TX            11      /* Not in OMAP2420 */
 595 # define OMAP24XX_DMA_DES_RX            12      /* Not in OMAP2420 */
 596 # define OMAP24XX_DMA_SHA1MD5_RX        13      /* Not in OMAP2420 */
 597 # define OMAP24XX_DMA_EXT_DMAREQ2       14
 598 # define OMAP24XX_DMA_EXT_DMAREQ3       15
 599 # define OMAP24XX_DMA_EXT_DMAREQ4       16
 600 # define OMAP24XX_DMA_EAC_AC_RD         17
 601 # define OMAP24XX_DMA_EAC_AC_WR         18
 602 # define OMAP24XX_DMA_EAC_MD_UL_RD      19
 603 # define OMAP24XX_DMA_EAC_MD_UL_WR      20
 604 # define OMAP24XX_DMA_EAC_MD_DL_RD      21
 605 # define OMAP24XX_DMA_EAC_MD_DL_WR      22
 606 # define OMAP24XX_DMA_EAC_BT_UL_RD      23
 607 # define OMAP24XX_DMA_EAC_BT_UL_WR      24
 608 # define OMAP24XX_DMA_EAC_BT_DL_RD      25
 609 # define OMAP24XX_DMA_EAC_BT_DL_WR      26
 610 # define OMAP24XX_DMA_I2C1_TX           27
 611 # define OMAP24XX_DMA_I2C1_RX           28
 612 # define OMAP24XX_DMA_I2C2_TX           29
 613 # define OMAP24XX_DMA_I2C2_RX           30
 614 # define OMAP24XX_DMA_MCBSP1_TX         31
 615 # define OMAP24XX_DMA_MCBSP1_RX         32
 616 # define OMAP24XX_DMA_MCBSP2_TX         33
 617 # define OMAP24XX_DMA_MCBSP2_RX         34
 618 # define OMAP24XX_DMA_SPI1_TX0          35
 619 # define OMAP24XX_DMA_SPI1_RX0          36
 620 # define OMAP24XX_DMA_SPI1_TX1          37
 621 # define OMAP24XX_DMA_SPI1_RX1          38
 622 # define OMAP24XX_DMA_SPI1_TX2          39
 623 # define OMAP24XX_DMA_SPI1_RX2          40
 624 # define OMAP24XX_DMA_SPI1_TX3          41
 625 # define OMAP24XX_DMA_SPI1_RX3          42
 626 # define OMAP24XX_DMA_SPI2_TX0          43
 627 # define OMAP24XX_DMA_SPI2_RX0          44
 628 # define OMAP24XX_DMA_SPI2_TX1          45
 629 # define OMAP24XX_DMA_SPI2_RX1          46
 630
 631 # define OMAP24XX_DMA_UART1_TX          49
 632 # define OMAP24XX_DMA_UART1_RX          50
 633 # define OMAP24XX_DMA_UART2_TX          51
 634 # define OMAP24XX_DMA_UART2_RX          52
 635 # define OMAP24XX_DMA_UART3_TX          53
 636 # define OMAP24XX_DMA_UART3_RX          54
 637 # define OMAP24XX_DMA_USB_W2FC_TX0      55
 638 # define OMAP24XX_DMA_USB_W2FC_RX0      56
 639 # define OMAP24XX_DMA_USB_W2FC_TX1      57
 640 # define OMAP24XX_DMA_USB_W2FC_RX1      58
 641 # define OMAP24XX_DMA_USB_W2FC_TX2      59
 642 # define OMAP24XX_DMA_USB_W2FC_RX2      60
 643 # define OMAP24XX_DMA_MMC1_TX           61
 644 # define OMAP24XX_DMA_MMC1_RX           62
 645 # define OMAP24XX_DMA_MS                63      /* Not in OMAP2420 */
 646 # define OMAP24XX_DMA_EXT_DMAREQ5       64
 647
 648 /* omap[123].c */
 649 /* OMAP2 gp timer */
 650 struct omap_gp_timer_s;
 651 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
 652                 qemu_irq irq, omap_clk fclk, omap_clk iclk);
 653 void omap_gp_timer_reset(struct omap_gp_timer_s *s);
 654
 655 /* OMAP2 sysctimer */
 656 struct omap_synctimer_s;
 657 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
 658                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
 659 void omap_synctimer_reset(struct omap_synctimer_s *s);
 660
 661 struct omap_uart_s;
 662 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
 663                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 664                 qemu_irq txdma, qemu_irq rxdma,
 665                 const char *label, CharDriverState *chr);
 666 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
 667                 struct omap_target_agent_s *ta,
 668                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 669                 qemu_irq txdma, qemu_irq rxdma,
 670                 const char *label, CharDriverState *chr);
 671 void omap_uart_reset(struct omap_uart_s *s);
 672 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
 673
 674 struct omap_mpuio_s;
 675 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 676 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 677 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 678
 679 struct uWireSlave {
 680     uint16_t (*receive)(void *opaque);
 681     void (*send)(void *opaque, uint16_t data);
 682     void *opaque;
 683 };
 684 struct omap_uwire_s;
 685 void omap_uwire_attach(struct omap_uwire_s *s,
 686                 uWireSlave *slave, int chipselect);
 687
 688 /* OMAP2 spi */
 689 struct omap_mcspi_s;
 690 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
 691                 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
 692 void omap_mcspi_attach(struct omap_mcspi_s *s,
 693                 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
 694                 int chipselect);
 695 void omap_mcspi_reset(struct omap_mcspi_s *s);
 696
 697 struct I2SCodec {
 698     void *opaque;
 699
 700     /* The CPU can call this if it is generating the clock signal on the
 701      * i2s port.  The CODEC can ignore it if it is set up as a clock
 702      * master and generates its own clock.  */
 703     void (*set_rate)(void *opaque, int in, int out);
 704
 705     void (*tx_swallow)(void *opaque);
 706     qemu_irq rx_swallow;
 707     qemu_irq tx_start;
 708
 709     int tx_rate;
 710     int cts;
 711     int rx_rate;
 712     int rts;
 713
 714     struct i2s_fifo_s {
 715         uint8_t *fifo;
 716         int len;
 717         int start;
 718         int size;
 719     } in, out;
 720 };
 721 struct omap_mcbsp_s;
 722 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 723
 724 void omap_tap_init(struct omap_target_agent_s *ta,
 725                 struct omap_mpu_state_s *mpu);
 726
 727 /* omap_lcdc.c */
 728 struct omap_lcd_panel_s;
 729 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 730 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
 731                                         target_phys_addr_t base,
 732                                         qemu_irq irq,
 733                                         struct omap_dma_lcd_channel_s *dma,
 734                                         omap_clk clk);
 735
 736 /* omap_dss.c */
 737 struct rfbi_chip_s {
 738     void *opaque;
 739     void (*write)(void *opaque, int dc, uint16_t value);
 740     void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
 741     uint16_t (*read)(void *opaque, int dc);
 742 };
 743 struct omap_dss_s;
 744 void omap_dss_reset(struct omap_dss_s *s);
 745 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 746                 MemoryRegion *sysmem,
 747                 target_phys_addr_t l3_base,
 748                 qemu_irq irq, qemu_irq drq,
 749                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
 750                 omap_clk ick1, omap_clk ick2);
 751 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
 752
 753 /* omap_mmc.c */
 754 struct omap_mmc_s;
 755 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 756                 MemoryRegion *sysmem,
 757                 BlockDriverState *bd,
 758                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 759 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 760                 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
 761                 omap_clk fclk, omap_clk iclk);
 762 void omap_mmc_reset(struct omap_mmc_s *s);
 763 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 764 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
 765
 766 /* omap_i2c.c */
 767 i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
 768
 769 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 770 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 771 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 772 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 773 # define cpu_is_omap2410(cpu)           (cpu->mpu_model == omap2410)
 774 # define cpu_is_omap2420(cpu)           (cpu->mpu_model == omap2420)
 775 # define cpu_is_omap2430(cpu)           (cpu->mpu_model == omap2430)
 776 # define cpu_is_omap3430(cpu)           (cpu->mpu_model == omap3430)
 777 # define cpu_is_omap3630(cpu)           (cpu->mpu_model == omap3630)
 778
 779 # define cpu_is_omap15xx(cpu)           \
 780         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 781 # define cpu_is_omap16xx(cpu)           \
 782         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 783 # define cpu_is_omap24xx(cpu)           \
 784         (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
 785
 786 # define cpu_class_omap1(cpu)           \
 787         (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
 788 # define cpu_class_omap2(cpu)           cpu_is_omap24xx(cpu)
 789 # define cpu_class_omap3(cpu) \
 790         (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
 791
 792 struct omap_mpu_state_s {
 793     enum omap_mpu_model {
 794         omap310,
 795         omap1510,
 796         omap1610,
 797         omap1710,
 798         omap2410,
 799         omap2420,
 800         omap2422,
 801         omap2423,
 802         omap2430,
 803         omap3430,
 804         omap3630,
 805     } mpu_model;
 806
 807     CPUARMState *env;
 808
 809     qemu_irq *drq;
 810
 811     qemu_irq wakeup;
 812
 813     MemoryRegion ulpd_pm_iomem;
 814     MemoryRegion pin_cfg_iomem;
 815     MemoryRegion id_iomem;
 816     MemoryRegion id_iomem_e18;
 817     MemoryRegion id_iomem_ed4;
 818     MemoryRegion id_iomem_e20;
 819     MemoryRegion mpui_iomem;
 820     MemoryRegion tcmi_iomem;
 821     MemoryRegion clkm_iomem;
 822     MemoryRegion clkdsp_iomem;
 823     MemoryRegion mpui_io_iomem;
 824     MemoryRegion tap_iomem;
 825     MemoryRegion imif_ram;
 826     MemoryRegion emiff_ram;
 827     MemoryRegion sdram;
 828     MemoryRegion sram;
 829
 830     struct omap_dma_port_if_s {
 831         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 832                         target_phys_addr_t offset);
 833         void (*write[3])(struct omap_mpu_state_s *s,
 834                         target_phys_addr_t offset, uint32_t value);
 835         int (*addr_valid)(struct omap_mpu_state_s *s,
 836                         target_phys_addr_t addr);
 837     } port[__omap_dma_port_last];
 838
 839     unsigned long sdram_size;
 840     unsigned long sram_size;
 841
 842     /* MPUI-TIPB peripherals */
 843     struct omap_uart_s *uart[3];
 844
 845     DeviceState *gpio;
 846
 847     struct omap_mcbsp_s *mcbsp1;
 848     struct omap_mcbsp_s *mcbsp3;
 849
 850     /* MPU public TIPB peripherals */
 851     struct omap_32khz_timer_s *os_timer;
 852
 853     struct omap_mmc_s *mmc;
 854
 855     struct omap_mpuio_s *mpuio;
 856
 857     struct omap_uwire_s *microwire;
 858
 859     struct omap_pwl_s *pwl;
 860     struct omap_pwt_s *pwt;
 861     DeviceState *i2c[2];
 862
 863     struct omap_rtc_s *rtc;
 864
 865     struct omap_mcbsp_s *mcbsp2;
 866
 867     struct omap_lpg_s *led[2];
 868
 869     /* MPU private TIPB peripherals */
 870     DeviceState *ih[2];
 871
 872     struct soc_dma_s *dma;
 873
 874     struct omap_mpu_timer_s *timer[3];
 875     struct omap_watchdog_timer_s *wdt;
 876
 877     struct omap_lcd_panel_s *lcd;
 878
 879     uint32_t ulpd_pm_regs[21];
 880     int64_t ulpd_gauge_start;
 881
 882     uint32_t func_mux_ctrl[14];
 883     uint32_t comp_mode_ctrl[1];
 884     uint32_t pull_dwn_ctrl[4];
 885     uint32_t gate_inh_ctrl[1];
 886     uint32_t voltage_ctrl[1];
 887     uint32_t test_dbg_ctrl[1];
 888     uint32_t mod_conf_ctrl[1];
 889     int compat1509;
 890
 891     uint32_t mpui_ctrl;
 892
 893     struct omap_tipb_bridge_s *private_tipb;
 894     struct omap_tipb_bridge_s *public_tipb;
 895
 896     uint32_t tcmi_regs[17];
 897
 898     struct dpll_ctl_s *dpll[3];
 899
 900     omap_clk clks;
 901     struct {
 902         int cold_start;
 903         int clocking_scheme;
 904         uint16_t arm_ckctl;
 905         uint16_t arm_idlect1;
 906         uint16_t arm_idlect2;
 907         uint16_t arm_ewupct;
 908         uint16_t arm_rstct1;
 909         uint16_t arm_rstct2;
 910         uint16_t arm_ckout1;
 911         int dpll1_mode;
 912         uint16_t dsp_idlect1;
 913         uint16_t dsp_idlect2;
 914         uint16_t dsp_rstct2;
 915     } clkm;
 916
 917     /* OMAP2-only peripherals */
 918     struct omap_l4_s *l4;
 919
 920     struct omap_gp_timer_s *gptimer[12];
 921     struct omap_synctimer_s *synctimer;
 922
 923     struct omap_prcm_s *prcm;
 924     struct omap_sdrc_s *sdrc;
 925     struct omap_gpmc_s *gpmc;
 926     struct omap_sysctl_s *sysc;
 927
 928     struct omap_mcspi_s *mcspi[2];
 929
 930     struct omap_dss_s *dss;
 931
 932     struct omap_eac_s *eac;
 933 };
 934
 935 /* omap1.c */
 936 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
 937                 unsigned long sdram_size,
 938                 const char *core);
 939
 940 /* omap2.c */
 941 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
 942                 unsigned long sdram_size,
 943                 const char *core);
 944
 945 # if TARGET_PHYS_ADDR_BITS == 32
 946 #  define OMAP_FMT_plx "%#08x"
 947 # elif TARGET_PHYS_ADDR_BITS == 64
 948 #  define OMAP_FMT_plx "%#08" PRIx64
 949 # else
 950 #  error TARGET_PHYS_ADDR_BITS undefined
 951 # endif
 952
 953 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
 954 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
 955                 uint32_t value);
 956 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
 957 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
 958                 uint32_t value);
 959 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
 960 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
 961                 uint32_t value);
 962
 963 void omap_mpu_wakeup(void *opaque, int irq, int req);
 964
 965 # define OMAP_BAD_REG(paddr)            \
 966         fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n",  \
 967                         __FUNCTION__, paddr)
 968 # define OMAP_RO_REG(paddr)             \
 969         fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n",    \
 970                         __FUNCTION__, paddr)
 971
 972 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
 973    (Board-specifc tags are not here)  */
 974 #define OMAP_TAG_CLOCK          0x4f01
 975 #define OMAP_TAG_MMC            0x4f02
 976 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 977 #define OMAP_TAG_USB            0x4f04
 978 #define OMAP_TAG_LCD            0x4f05
 979 #define OMAP_TAG_GPIO_SWITCH    0x4f06
 980 #define OMAP_TAG_UART           0x4f07
 981 #define OMAP_TAG_FBMEM          0x4f08
 982 #define OMAP_TAG_STI_CONSOLE    0x4f09
 983 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
 984 #define OMAP_TAG_PARTITION      0x4f0b
 985 #define OMAP_TAG_TEA5761        0x4f10
 986 #define OMAP_TAG_TMP105         0x4f11
 987 #define OMAP_TAG_BOOT_REASON    0x4f80
 988 #define OMAP_TAG_FLASH_PART_STR 0x4f81
 989 #define OMAP_TAG_VERSION_STR    0x4f82
 990
 991 enum {
 992     OMAP_GPIOSW_TYPE_COVER      = 0 << 4,
 993     OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
 994     OMAP_GPIOSW_TYPE_ACTIVITY   = 2 << 4,
 995 };
 996
 997 #define OMAP_GPIOSW_INVERTED    0x0001
 998 #define OMAP_GPIOSW_OUTPUT      0x0002
 999
1000 # define TCMI_VERBOSE                   1
1001 //# define MEM_VERBOSE                  1
1002
1003 # ifdef TCMI_VERBOSE
1004 #  define OMAP_8B_REG(paddr)            \
1005         fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n",        \
1006                         __FUNCTION__, paddr)
1007 #  define OMAP_16B_REG(paddr)           \
1008         fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n",       \
1009                         __FUNCTION__, paddr)
1010 #  define OMAP_32B_REG(paddr)           \
1011         fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n",       \
1012                         __FUNCTION__, paddr)
1013 # else
1014 #  define OMAP_8B_REG(paddr)
1015 #  define OMAP_16B_REG(paddr)
1016 #  define OMAP_32B_REG(paddr)
1017 # endif
1018
1019 # define OMAP_MPUI_REG_MASK             0x000007ff
1020
1021 # ifdef MEM_VERBOSE
1022 struct io_fn {
1023     CPUReadMemoryFunc * const *mem_read;
1024     CPUWriteMemoryFunc * const *mem_write;
1025     void *opaque;
1026     int in;
1027 };
1028
1029 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1030 {
1031     struct io_fn *s = opaque;
1032     uint32_t ret;
1033
1034     s->in ++;
1035     ret = s->mem_read[0](s->opaque, addr);
1036     s->in --;
1037     if (!s->in)
1038         fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1039     return ret;
1040 }
1041 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1042 {
1043     struct io_fn *s = opaque;
1044     uint32_t ret;
1045
1046     s->in ++;
1047     ret = s->mem_read[1](s->opaque, addr);
1048     s->in --;
1049     if (!s->in)
1050         fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1051     return ret;
1052 }
1053 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1054 {
1055     struct io_fn *s = opaque;
1056     uint32_t ret;
1057
1058     s->in ++;
1059     ret = s->mem_read[2](s->opaque, addr);
1060     s->in --;
1061     if (!s->in)
1062         fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1063     return ret;
1064 }
1065 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1066 {
1067     struct io_fn *s = opaque;
1068
1069     if (!s->in)
1070         fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1071     s->in ++;
1072     s->mem_write[0](s->opaque, addr, value);
1073     s->in --;
1074 }
1075 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1076 {
1077     struct io_fn *s = opaque;
1078
1079     if (!s->in)
1080         fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1081     s->in ++;
1082     s->mem_write[1](s->opaque, addr, value);
1083     s->in --;
1084 }
1085 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1086 {
1087     struct io_fn *s = opaque;
1088
1089     if (!s->in)
1090         fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1091     s->in ++;
1092     s->mem_write[2](s->opaque, addr, value);
1093     s->in --;
1094 }
1095
1096 static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, };
1097 static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, };
1098
1099 inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
1100                                            CPUWriteMemoryFunc * const *mem_write,
1101                                            void *opaque)
1102 {
1103     struct io_fn *s = g_malloc(sizeof(struct io_fn));
1104
1105     s->mem_read = mem_read;
1106     s->mem_write = mem_write;
1107     s->opaque = opaque;
1108     s->in = 0;
1109     return cpu_register_io_memory(io_readfn, io_writefn, s,
1110                                   DEVICE_NATIVE_ENDIAN);
1111 }
1112 #  define cpu_register_io_memory        debug_register_io_memory
1113 # endif
1114
1115 #endif /* hw_omap_h */