?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ehci: drop old stuff
[qemu/wangdongxu.git] / hw / usb-ehci.c
blobafc8ccf458cd21fb300306a2895f04f53dd13256
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw.h"
26 #include "qemu-timer.h"
27 #include "usb.h"
28 #include "pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_FETCHSITD,
153 EST_ADVANCEQUEUE,
154 EST_FETCHQTD,
155 EST_EXECUTE,
156 EST_WRITEBACK,
157 EST_HORIZONTALQH
158 } EHCI_STATES;
159
160 /* macros for accessing fields within next link pointer entry */
161 #define NLPTR_GET(x) ((x) & 0xffffffe0)
162 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
163 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164
165 /* link pointer types */
166 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
167 #define NLPTR_TYPE_QH 1 // queue head
168 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
169 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
170
171
172 /* EHCI spec version 1.0 Section 3.3
173 */
174 typedef struct EHCIitd {
175 uint32_t next;
176
177 uint32_t transact[8];
178 #define ITD_XACT_ACTIVE (1 << 31)
179 #define ITD_XACT_DBERROR (1 << 30)
180 #define ITD_XACT_BABBLE (1 << 29)
181 #define ITD_XACT_XACTERR (1 << 28)
182 #define ITD_XACT_LENGTH_MASK 0x0fff0000
183 #define ITD_XACT_LENGTH_SH 16
184 #define ITD_XACT_IOC (1 << 15)
185 #define ITD_XACT_PGSEL_MASK 0x00007000
186 #define ITD_XACT_PGSEL_SH 12
187 #define ITD_XACT_OFFSET_MASK 0x00000fff
188
189 uint32_t bufptr[7];
190 #define ITD_BUFPTR_MASK 0xfffff000
191 #define ITD_BUFPTR_SH 12
192 #define ITD_BUFPTR_EP_MASK 0x00000f00
193 #define ITD_BUFPTR_EP_SH 8
194 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
195 #define ITD_BUFPTR_DEVADDR_SH 0
196 #define ITD_BUFPTR_DIRECTION (1 << 11)
197 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
198 #define ITD_BUFPTR_MAXPKT_SH 0
199 #define ITD_BUFPTR_MULT_MASK 0x00000003
200 #define ITD_BUFPTR_MULT_SH 0
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 #define QTD_BUFPTR_SH 12
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 bool async_schedule;
351 uint32_t seen;
352 uint64_t ts;
353
354 /* cached data from guest - needs to be flushed
355 * when guest removes an entry (doorbell, handshake sequence)
356 */
357 EHCIqh qh; // copy of current QH (being worked on)
358 uint32_t qhaddr; // address QH read from
359 EHCIqtd qtd; // copy of current QTD (being worked on)
360 uint32_t qtdaddr; // address QTD read from
361
362 USBPacket packet;
363 QEMUSGList sgl;
364 int pid;
365 uint32_t tbytes;
366 enum async_state async;
367 int usb_status;
368 };
369
370 struct EHCIState {
371 PCIDevice dev;
372 USBBus bus;
373 qemu_irq irq;
374 MemoryRegion mem;
375 int companion_count;
376
377 /* properties */
378 uint32_t freq;
379 uint32_t maxframes;
380
381 /*
382 * EHCI spec version 1.0 Section 2.3
383 * Host Controller Operational Registers
384 */
385 union {
386 uint8_t mmio[MMIO_SIZE];
387 struct {
388 uint8_t cap[OPREGBASE];
389 uint32_t usbcmd;
390 uint32_t usbsts;
391 uint32_t usbintr;
392 uint32_t frindex;
393 uint32_t ctrldssegment;
394 uint32_t periodiclistbase;
395 uint32_t asynclistaddr;
396 uint32_t notused[9];
397 uint32_t configflag;
398 uint32_t portsc[NB_PORTS];
399 };
400 };
401
402 /*
403 * Internal states, shadow registers, etc
404 */
405 uint32_t sofv;
406 QEMUTimer *frame_timer;
407 int attach_poll_counter;
408 int astate; // Current state in asynchronous schedule
409 int pstate; // Current state in periodic schedule
410 USBPort ports[NB_PORTS];
411 USBPort *companion_ports[NB_PORTS];
412 uint32_t usbsts_pending;
413 QTAILQ_HEAD(, EHCIQueue) queues;
414
415 uint32_t a_fetch_addr; // which address to look at next
416 uint32_t p_fetch_addr; // which address to look at next
417
418 USBPacket ipacket;
419 QEMUSGList isgl;
420 int isoch_pause;
421
422 uint64_t last_run_ns;
423 };
424
425 #define SET_LAST_RUN_CLOCK(s) \
426 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
427
428 /* nifty macros from Arnon's EHCI version */
429 #define get_field(data, field) \
430 (((data) & field##_MASK) >> field##_SH)
431
432 #define set_field(data, newval, field) do { \
433 uint32_t val = *data; \
434 val &= ~ field##_MASK; \
435 val |= ((newval) << field##_SH) & field##_MASK; \
436 *data = val; \
437 } while(0)
438
439 static const char *ehci_state_names[] = {
440 [EST_INACTIVE] = "INACTIVE",
441 [EST_ACTIVE] = "ACTIVE",
442 [EST_EXECUTING] = "EXECUTING",
443 [EST_SLEEPING] = "SLEEPING",
444 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
445 [EST_FETCHENTRY] = "FETCH ENTRY",
446 [EST_FETCHQH] = "FETCH QH",
447 [EST_FETCHITD] = "FETCH ITD",
448 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
449 [EST_FETCHQTD] = "FETCH QTD",
450 [EST_EXECUTE] = "EXECUTE",
451 [EST_WRITEBACK] = "WRITEBACK",
452 [EST_HORIZONTALQH] = "HORIZONTALQH",
453 };
454
455 static const char *ehci_mmio_names[] = {
456 [CAPLENGTH] = "CAPLENGTH",
457 [HCIVERSION] = "HCIVERSION",
458 [HCSPARAMS] = "HCSPARAMS",
459 [HCCPARAMS] = "HCCPARAMS",
460 [USBCMD] = "USBCMD",
461 [USBSTS] = "USBSTS",
462 [USBINTR] = "USBINTR",
463 [FRINDEX] = "FRINDEX",
464 [PERIODICLISTBASE] = "P-LIST BASE",
465 [ASYNCLISTADDR] = "A-LIST ADDR",
466 [PORTSC_BEGIN] = "PORTSC #0",
467 [PORTSC_BEGIN + 4] = "PORTSC #1",
468 [PORTSC_BEGIN + 8] = "PORTSC #2",
469 [PORTSC_BEGIN + 12] = "PORTSC #3",
470 [PORTSC_BEGIN + 16] = "PORTSC #4",
471 [PORTSC_BEGIN + 20] = "PORTSC #5",
472 [CONFIGFLAG] = "CONFIGFLAG",
473 };
474
475 static const char *nr2str(const char **n, size_t len, uint32_t nr)
476 {
477 if (nr < len && n[nr] != NULL) {
478 return n[nr];
479 } else {
480 return "unknown";
481 }
482 }
483
484 static const char *state2str(uint32_t state)
485 {
486 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
487 }
488
489 static const char *addr2str(target_phys_addr_t addr)
490 {
491 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
492 }
493
494 static void ehci_trace_usbsts(uint32_t mask, int state)
495 {
496 /* interrupts */
497 if (mask & USBSTS_INT) {
498 trace_usb_ehci_usbsts("INT", state);
499 }
500 if (mask & USBSTS_ERRINT) {
501 trace_usb_ehci_usbsts("ERRINT", state);
502 }
503 if (mask & USBSTS_PCD) {
504 trace_usb_ehci_usbsts("PCD", state);
505 }
506 if (mask & USBSTS_FLR) {
507 trace_usb_ehci_usbsts("FLR", state);
508 }
509 if (mask & USBSTS_HSE) {
510 trace_usb_ehci_usbsts("HSE", state);
511 }
512 if (mask & USBSTS_IAA) {
513 trace_usb_ehci_usbsts("IAA", state);
514 }
515
516 /* status */
517 if (mask & USBSTS_HALT) {
518 trace_usb_ehci_usbsts("HALT", state);
519 }
520 if (mask & USBSTS_REC) {
521 trace_usb_ehci_usbsts("REC", state);
522 }
523 if (mask & USBSTS_PSS) {
524 trace_usb_ehci_usbsts("PSS", state);
525 }
526 if (mask & USBSTS_ASS) {
527 trace_usb_ehci_usbsts("ASS", state);
528 }
529 }
530
531 static inline void ehci_set_usbsts(EHCIState *s, int mask)
532 {
533 if ((s->usbsts & mask) == mask) {
534 return;
535 }
536 ehci_trace_usbsts(mask, 1);
537 s->usbsts |= mask;
538 }
539
540 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
541 {
542 if ((s->usbsts & mask) == 0) {
543 return;
544 }
545 ehci_trace_usbsts(mask, 0);
546 s->usbsts &= ~mask;
547 }
548
549 static inline void ehci_set_interrupt(EHCIState *s, int intr)
550 {
551 int level = 0;
552
553 // TODO honour interrupt threshold requests
554
555 ehci_set_usbsts(s, intr);
556
557 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
558 level = 1;
559 }
560
561 qemu_set_irq(s->irq, level);
562 }
563
564 static inline void ehci_record_interrupt(EHCIState *s, int intr)
565 {
566 s->usbsts_pending |= intr;
567 }
568
569 static inline void ehci_commit_interrupt(EHCIState *s)
570 {
571 if (!s->usbsts_pending) {
572 return;
573 }
574 ehci_set_interrupt(s, s->usbsts_pending);
575 s->usbsts_pending = 0;
576 }
577
578 static void ehci_set_state(EHCIState *s, int async, int state)
579 {
580 if (async) {
581 trace_usb_ehci_state("async", state2str(state));
582 s->astate = state;
583 } else {
584 trace_usb_ehci_state("periodic", state2str(state));
585 s->pstate = state;
586 }
587 }
588
589 static int ehci_get_state(EHCIState *s, int async)
590 {
591 return async ? s->astate : s->pstate;
592 }
593
594 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
595 {
596 if (async) {
597 s->a_fetch_addr = addr;
598 } else {
599 s->p_fetch_addr = addr;
600 }
601 }
602
603 static int ehci_get_fetch_addr(EHCIState *s, int async)
604 {
605 return async ? s->a_fetch_addr : s->p_fetch_addr;
606 }
607
608 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
609 {
610 /* need three here due to argument count limits */
611 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
612 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
613 trace_usb_ehci_qh_fields(addr,
614 get_field(qh->epchar, QH_EPCHAR_RL),
615 get_field(qh->epchar, QH_EPCHAR_MPLEN),
616 get_field(qh->epchar, QH_EPCHAR_EPS),
617 get_field(qh->epchar, QH_EPCHAR_EP),
618 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
619 trace_usb_ehci_qh_bits(addr,
620 (bool)(qh->epchar & QH_EPCHAR_C),
621 (bool)(qh->epchar & QH_EPCHAR_H),
622 (bool)(qh->epchar & QH_EPCHAR_DTC),
623 (bool)(qh->epchar & QH_EPCHAR_I));
624 }
625
626 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
627 {
628 /* need three here due to argument count limits */
629 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
630 trace_usb_ehci_qtd_fields(addr,
631 get_field(qtd->token, QTD_TOKEN_TBYTES),
632 get_field(qtd->token, QTD_TOKEN_CPAGE),
633 get_field(qtd->token, QTD_TOKEN_CERR),
634 get_field(qtd->token, QTD_TOKEN_PID));
635 trace_usb_ehci_qtd_bits(addr,
636 (bool)(qtd->token & QTD_TOKEN_IOC),
637 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
638 (bool)(qtd->token & QTD_TOKEN_HALT),
639 (bool)(qtd->token & QTD_TOKEN_BABBLE),
640 (bool)(qtd->token & QTD_TOKEN_XACTERR));
641 }
642
643 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
644 {
645 trace_usb_ehci_itd(addr, itd->next,
646 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
647 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
648 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
649 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
650 }
651
652 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
653 EHCIsitd *sitd)
654 {
655 trace_usb_ehci_sitd(addr, sitd->next,
656 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
657 }
658
659 /* queue management */
660
661 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
662 {
663 EHCIQueue *q;
664
665 q = g_malloc0(sizeof(*q));
666 q->ehci = ehci;
667 q->async_schedule = async;
668 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
669 trace_usb_ehci_queue_action(q, "alloc");
670 return q;
671 }
672
673 static void ehci_free_queue(EHCIQueue *q)
674 {
675 trace_usb_ehci_queue_action(q, "free");
676 if (q->async == EHCI_ASYNC_INFLIGHT) {
677 usb_cancel_packet(&q->packet);
678 }
679 QTAILQ_REMOVE(&q->ehci->queues, q, next);
680 g_free(q);
681 }
682
683 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
684 {
685 EHCIQueue *q;
686
687 QTAILQ_FOREACH(q, &ehci->queues, next) {
688 if (addr == q->qhaddr) {
689 return q;
690 }
691 }
692 return NULL;
693 }
694
695 static void ehci_queues_rip_unused(EHCIState *ehci)
696 {
697 EHCIQueue *q, *tmp;
698
699 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
700 if (q->seen) {
701 q->seen = 0;
702 q->ts = ehci->last_run_ns;
703 continue;
704 }
705 if (ehci->last_run_ns < q->ts + 250000000) {
706 /* allow 0.25 sec idle */
707 continue;
708 }
709 ehci_free_queue(q);
710 }
711 }
712
713 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
714 {
715 EHCIQueue *q, *tmp;
716
717 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
718 if (!usb_packet_is_inflight(&q->packet) ||
719 q->packet.ep->dev != dev) {
720 continue;
721 }
722 ehci_free_queue(q);
723 }
724 }
725
726 static void ehci_queues_rip_all(EHCIState *ehci)
727 {
728 EHCIQueue *q, *tmp;
729
730 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
731 ehci_free_queue(q);
732 }
733 }
734
735 /* Attach or detach a device on root hub */
736
737 static void ehci_attach(USBPort *port)
738 {
739 EHCIState *s = port->opaque;
740 uint32_t *portsc = &s->portsc[port->index];
741
742 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
743
744 if (*portsc & PORTSC_POWNER) {
745 USBPort *companion = s->companion_ports[port->index];
746 companion->dev = port->dev;
747 companion->ops->attach(companion);
748 return;
749 }
750
751 *portsc |= PORTSC_CONNECT;
752 *portsc |= PORTSC_CSC;
753
754 ehci_set_interrupt(s, USBSTS_PCD);
755 }
756
757 static void ehci_detach(USBPort *port)
758 {
759 EHCIState *s = port->opaque;
760 uint32_t *portsc = &s->portsc[port->index];
761
762 trace_usb_ehci_port_detach(port->index);
763
764 if (*portsc & PORTSC_POWNER) {
765 USBPort *companion = s->companion_ports[port->index];
766 companion->ops->detach(companion);
767 companion->dev = NULL;
768 /*
769 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
770 * the port ownership is returned immediately to the EHCI controller."
771 */
772 *portsc &= ~PORTSC_POWNER;
773 return;
774 }
775
776 ehci_queues_rip_device(s, port->dev);
777
778 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
779 *portsc |= PORTSC_CSC;
780
781 ehci_set_interrupt(s, USBSTS_PCD);
782 }
783
784 static void ehci_child_detach(USBPort *port, USBDevice *child)
785 {
786 EHCIState *s = port->opaque;
787 uint32_t portsc = s->portsc[port->index];
788
789 if (portsc & PORTSC_POWNER) {
790 USBPort *companion = s->companion_ports[port->index];
791 companion->ops->child_detach(companion, child);
792 companion->dev = NULL;
793 return;
794 }
795
796 ehci_queues_rip_device(s, child);
797 }
798
799 static void ehci_wakeup(USBPort *port)
800 {
801 EHCIState *s = port->opaque;
802 uint32_t portsc = s->portsc[port->index];
803
804 if (portsc & PORTSC_POWNER) {
805 USBPort *companion = s->companion_ports[port->index];
806 if (companion->ops->wakeup) {
807 companion->ops->wakeup(companion);
808 }
809 }
810 }
811
812 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
813 uint32_t portcount, uint32_t firstport)
814 {
815 EHCIState *s = container_of(bus, EHCIState, bus);
816 uint32_t i;
817
818 if (firstport + portcount > NB_PORTS) {
819 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
820 "firstport on masterbus");
821 error_printf_unless_qmp(
822 "firstport value of %u makes companion take ports %u - %u, which "
823 "is outside of the valid range of 0 - %u\n", firstport, firstport,
824 firstport + portcount - 1, NB_PORTS - 1);
825 return -1;
826 }
827
828 for (i = 0; i < portcount; i++) {
829 if (s->companion_ports[firstport + i]) {
830 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
831 "an USB masterbus");
832 error_printf_unless_qmp(
833 "port %u on masterbus %s already has a companion assigned\n",
834 firstport + i, bus->qbus.name);
835 return -1;
836 }
837 }
838
839 for (i = 0; i < portcount; i++) {
840 s->companion_ports[firstport + i] = ports[i];
841 s->ports[firstport + i].speedmask |=
842 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
843 /* Ensure devs attached before the initial reset go to the companion */
844 s->portsc[firstport + i] = PORTSC_POWNER;
845 }
846
847 s->companion_count++;
848 s->mmio[0x05] = (s->companion_count << 4) | portcount;
849
850 return 0;
851 }
852
853 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
854 {
855 USBDevice *dev;
856 USBPort *port;
857 int i;
858
859 for (i = 0; i < NB_PORTS; i++) {
860 port = &ehci->ports[i];
861 if (!(ehci->portsc[i] & PORTSC_PED)) {
862 DPRINTF("Port %d not enabled\n", i);
863 continue;
864 }
865 dev = usb_find_device(port, addr);
866 if (dev != NULL) {
867 return dev;
868 }
869 }
870 return NULL;
871 }
872
873 /* 4.1 host controller initialization */
874 static void ehci_reset(void *opaque)
875 {
876 EHCIState *s = opaque;
877 int i;
878 USBDevice *devs[NB_PORTS];
879
880 trace_usb_ehci_reset();
881
882 /*
883 * Do the detach before touching portsc, so that it correctly gets send to
884 * us or to our companion based on PORTSC_POWNER before the reset.
885 */
886 for(i = 0; i < NB_PORTS; i++) {
887 devs[i] = s->ports[i].dev;
888 if (devs[i] && devs[i]->attached) {
889 usb_detach(&s->ports[i]);
890 }
891 }
892
893 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
894
895 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
896 s->usbsts = USBSTS_HALT;
897
898 s->astate = EST_INACTIVE;
899 s->pstate = EST_INACTIVE;
900 s->isoch_pause = -1;
901 s->attach_poll_counter = 0;
902
903 for(i = 0; i < NB_PORTS; i++) {
904 if (s->companion_ports[i]) {
905 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
906 } else {
907 s->portsc[i] = PORTSC_PPOWER;
908 }
909 if (devs[i] && devs[i]->attached) {
910 usb_attach(&s->ports[i]);
911 usb_device_reset(devs[i]);
912 }
913 }
914 ehci_queues_rip_all(s);
915 qemu_del_timer(s->frame_timer);
916 }
917
918 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
919 {
920 EHCIState *s = ptr;
921 uint32_t val;
922
923 val = s->mmio[addr];
924
925 return val;
926 }
927
928 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
929 {
930 EHCIState *s = ptr;
931 uint32_t val;
932
933 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
934
935 return val;
936 }
937
938 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
939 {
940 EHCIState *s = ptr;
941 uint32_t val;
942
943 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
944 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
945
946 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
947 return val;
948 }
949
950 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
951 {
952 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
953 exit(1);
954 }
955
956 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
957 {
958 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
959 exit(1);
960 }
961
962 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
963 {
964 USBDevice *dev = s->ports[port].dev;
965 uint32_t *portsc = &s->portsc[port];
966 uint32_t orig;
967
968 if (s->companion_ports[port] == NULL)
969 return;
970
971 owner = owner & PORTSC_POWNER;
972 orig = *portsc & PORTSC_POWNER;
973
974 if (!(owner ^ orig)) {
975 return;
976 }
977
978 if (dev && dev->attached) {
979 usb_detach(&s->ports[port]);
980 }
981
982 *portsc &= ~PORTSC_POWNER;
983 *portsc |= owner;
984
985 if (dev && dev->attached) {
986 usb_attach(&s->ports[port]);
987 }
988 }
989
990 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
991 {
992 uint32_t *portsc = &s->portsc[port];
993 USBDevice *dev = s->ports[port].dev;
994
995 /* Clear rwc bits */
996 *portsc &= ~(val & PORTSC_RWC_MASK);
997 /* The guest may clear, but not set the PED bit */
998 *portsc &= val | ~PORTSC_PED;
999 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1000 handle_port_owner_write(s, port, val);
1001 /* And finally apply RO_MASK */
1002 val &= PORTSC_RO_MASK;
1003
1004 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1005 trace_usb_ehci_port_reset(port, 1);
1006 }
1007
1008 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1009 trace_usb_ehci_port_reset(port, 0);
1010 if (dev && dev->attached) {
1011 usb_port_reset(&s->ports[port]);
1012 *portsc &= ~PORTSC_CSC;
1013 }
1014
1015 /*
1016 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1017 * to SW that this port has a high speed device attached
1018 */
1019 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1020 val |= PORTSC_PED;
1021 }
1022 }
1023
1024 *portsc &= ~PORTSC_RO_MASK;
1025 *portsc |= val;
1026 }
1027
1028 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1029 {
1030 EHCIState *s = ptr;
1031 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1032 uint32_t old = *mmio;
1033 int i;
1034
1035 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1036
1037 /* Only aligned reads are allowed on OHCI */
1038 if (addr & 3) {
1039 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1040 TARGET_FMT_plx "\n", addr);
1041 return;
1042 }
1043
1044 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1045 handle_port_status_write(s, (addr-PORTSC)/4, val);
1046 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1047 return;
1048 }
1049
1050 if (addr < OPREGBASE) {
1051 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1052 TARGET_FMT_plx "\n", addr);
1053 return;
1054 }
1055
1056
1057 /* Do any register specific pre-write processing here. */
1058 switch(addr) {
1059 case USBCMD:
1060 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1061 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1062 SET_LAST_RUN_CLOCK(s);
1063 ehci_clear_usbsts(s, USBSTS_HALT);
1064 }
1065
1066 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1067 qemu_del_timer(s->frame_timer);
1068 // TODO - should finish out some stuff before setting halt
1069 ehci_set_usbsts(s, USBSTS_HALT);
1070 }
1071
1072 if (val & USBCMD_HCRESET) {
1073 ehci_reset(s);
1074 val = s->usbcmd;
1075 }
1076
1077 /* not supporting dynamic frame list size at the moment */
1078 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1079 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1080 val & USBCMD_FLS);
1081 val &= ~USBCMD_FLS;
1082 }
1083 break;
1084
1085 case USBSTS:
1086 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1087 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1088 val = s->usbsts;
1089 ehci_set_interrupt(s, 0);
1090 break;
1091
1092 case USBINTR:
1093 val &= USBINTR_MASK;
1094 break;
1095
1096 case FRINDEX:
1097 s->sofv = val >> 3;
1098 break;
1099
1100 case CONFIGFLAG:
1101 val &= 0x1;
1102 if (val) {
1103 for(i = 0; i < NB_PORTS; i++)
1104 handle_port_owner_write(s, i, 0);
1105 }
1106 break;
1107
1108 case PERIODICLISTBASE:
1109 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1110 fprintf(stderr,
1111 "ehci: PERIODIC list base register set while periodic schedule\n"
1112 " is enabled and HC is enabled\n");
1113 }
1114 break;
1115
1116 case ASYNCLISTADDR:
1117 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1118 fprintf(stderr,
1119 "ehci: ASYNC list address register set while async schedule\n"
1120 " is enabled and HC is enabled\n");
1121 }
1122 break;
1123 }
1124
1125 *mmio = val;
1126 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1127 }
1128
1129
1130 // TODO : Put in common header file, duplication from usb-ohci.c
1131
1132 /* Get an array of dwords from main memory */
1133 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1134 uint32_t *buf, int num)
1135 {
1136 int i;
1137
1138 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1139 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1140 *buf = le32_to_cpu(*buf);
1141 }
1142
1143 return 1;
1144 }
1145
1146 /* Put an array of dwords in to main memory */
1147 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1148 uint32_t *buf, int num)
1149 {
1150 int i;
1151
1152 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1153 uint32_t tmp = cpu_to_le32(*buf);
1154 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1155 }
1156
1157 return 1;
1158 }
1159
1160 // 4.10.2
1161
1162 static int ehci_qh_do_overlay(EHCIQueue *q)
1163 {
1164 int i;
1165 int dtoggle;
1166 int ping;
1167 int eps;
1168 int reload;
1169
1170 // remember values in fields to preserve in qh after overlay
1171
1172 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1173 ping = q->qh.token & QTD_TOKEN_PING;
1174
1175 q->qh.current_qtd = q->qtdaddr;
1176 q->qh.next_qtd = q->qtd.next;
1177 q->qh.altnext_qtd = q->qtd.altnext;
1178 q->qh.token = q->qtd.token;
1179
1180
1181 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1182 if (eps == EHCI_QH_EPS_HIGH) {
1183 q->qh.token &= ~QTD_TOKEN_PING;
1184 q->qh.token |= ping;
1185 }
1186
1187 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1188 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1189
1190 for (i = 0; i < 5; i++) {
1191 q->qh.bufptr[i] = q->qtd.bufptr[i];
1192 }
1193
1194 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1195 // preserve QH DT bit
1196 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1197 q->qh.token |= dtoggle;
1198 }
1199
1200 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1201 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1202
1203 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1204 sizeof(EHCIqh) >> 2);
1205
1206 return 0;
1207 }
1208
1209 static int ehci_init_transfer(EHCIQueue *q)
1210 {
1211 uint32_t cpage, offset, bytes, plen;
1212 dma_addr_t page;
1213
1214 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1215 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1216 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1217 pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5);
1218
1219 while (bytes > 0) {
1220 if (cpage > 4) {
1221 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1222 return USB_RET_PROCERR;
1223 }
1224
1225 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1226 page += offset;
1227 plen = bytes;
1228 if (plen > 4096 - offset) {
1229 plen = 4096 - offset;
1230 offset = 0;
1231 cpage++;
1232 }
1233
1234 qemu_sglist_add(&q->sgl, page, plen);
1235 bytes -= plen;
1236 }
1237 return 0;
1238 }
1239
1240 static void ehci_finish_transfer(EHCIQueue *q, int status)
1241 {
1242 uint32_t cpage, offset;
1243
1244 qemu_sglist_destroy(&q->sgl);
1245
1246 if (status > 0) {
1247 /* update cpage & offset */
1248 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1249 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1250
1251 offset += status;
1252 cpage += offset >> QTD_BUFPTR_SH;
1253 offset &= ~QTD_BUFPTR_MASK;
1254
1255 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1256 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1257 q->qh.bufptr[0] |= offset;
1258 }
1259 }
1260
1261 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1262 {
1263 EHCIQueue *q;
1264 EHCIState *s = port->opaque;
1265 uint32_t portsc = s->portsc[port->index];
1266
1267 if (portsc & PORTSC_POWNER) {
1268 USBPort *companion = s->companion_ports[port->index];
1269 companion->ops->complete(companion, packet);
1270 return;
1271 }
1272
1273 q = container_of(packet, EHCIQueue, packet);
1274 trace_usb_ehci_queue_action(q, "wakeup");
1275 assert(q->async == EHCI_ASYNC_INFLIGHT);
1276 q->async = EHCI_ASYNC_FINISHED;
1277 q->usb_status = packet->result;
1278 }
1279
1280 static void ehci_execute_complete(EHCIQueue *q)
1281 {
1282 int c_err, reload;
1283
1284 assert(q->async != EHCI_ASYNC_INFLIGHT);
1285 q->async = EHCI_ASYNC_NONE;
1286
1287 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1288 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1289
1290 if (q->usb_status < 0) {
1291 err:
1292 /* TO-DO: put this is in a function that can be invoked below as well */
1293 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1294 c_err--;
1295 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1296
1297 switch(q->usb_status) {
1298 case USB_RET_NODEV:
1299 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1300 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1301 break;
1302 case USB_RET_STALL:
1303 q->qh.token |= QTD_TOKEN_HALT;
1304 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1305 break;
1306 case USB_RET_NAK:
1307 /* 4.10.3 */
1308 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1309 if ((q->pid == USB_TOKEN_IN) && reload) {
1310 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1311 nakcnt--;
1312 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1313 } else if (!reload) {
1314 return;
1315 }
1316 break;
1317 case USB_RET_BABBLE:
1318 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1319 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1320 break;
1321 default:
1322 /* should not be triggerable */
1323 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1324 assert(0);
1325 break;
1326 }
1327 } else {
1328 // DPRINTF("Short packet condition\n");
1329 // TODO check 4.12 for splits
1330
1331 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1332 q->usb_status = USB_RET_BABBLE;
1333 goto err;
1334 }
1335
1336 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1337 q->tbytes -= q->usb_status;
1338 } else {
1339 q->tbytes = 0;
1340 }
1341
1342 DPRINTF("updating tbytes to %d\n", q->tbytes);
1343 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1344 }
1345 ehci_finish_transfer(q, q->usb_status);
1346 usb_packet_unmap(&q->packet);
1347
1348 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1349 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1350
1351 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1352 ehci_record_interrupt(q->ehci, USBSTS_INT);
1353 }
1354 }
1355
1356 // 4.10.3
1357
1358 static int ehci_execute(EHCIQueue *q)
1359 {
1360 USBDevice *dev;
1361 USBEndpoint *ep;
1362 int ret;
1363 int endp;
1364 int devadr;
1365
1366 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1367 fprintf(stderr, "Attempting to execute inactive QH\n");
1368 return USB_RET_PROCERR;
1369 }
1370
1371 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1372 if (q->tbytes > BUFF_SIZE) {
1373 fprintf(stderr, "Request for more bytes than allowed\n");
1374 return USB_RET_PROCERR;
1375 }
1376
1377 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1378 switch(q->pid) {
1379 case 0: q->pid = USB_TOKEN_OUT; break;
1380 case 1: q->pid = USB_TOKEN_IN; break;
1381 case 2: q->pid = USB_TOKEN_SETUP; break;
1382 default: fprintf(stderr, "bad token\n"); break;
1383 }
1384
1385 if (ehci_init_transfer(q) != 0) {
1386 return USB_RET_PROCERR;
1387 }
1388
1389 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1390 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1391
1392 /* TODO: associating device with ehci port */
1393 dev = ehci_find_device(q->ehci, devadr);
1394 ep = usb_ep_get(dev, q->pid, endp);
1395
1396 usb_packet_setup(&q->packet, q->pid, ep);
1397 usb_packet_map(&q->packet, &q->sgl);
1398
1399 ret = usb_handle_packet(dev, &q->packet);
1400 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1401 "(total %d) endp %x ret %d\n",
1402 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1403 q->packet.iov.size, q->tbytes, endp, ret);
1404
1405 if (ret > BUFF_SIZE) {
1406 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1407 return USB_RET_PROCERR;
1408 }
1409
1410 return ret;
1411 }
1412
1413 /* 4.7.2
1414 */
1415
1416 static int ehci_process_itd(EHCIState *ehci,
1417 EHCIitd *itd)
1418 {
1419 USBDevice *dev;
1420 USBEndpoint *ep;
1421 int ret;
1422 uint32_t i, len, pid, dir, devaddr, endp;
1423 uint32_t pg, off, ptr1, ptr2, max, mult;
1424
1425 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1426 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1427 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1428 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1429 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1430
1431 for(i = 0; i < 8; i++) {
1432 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1433 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1434 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1435 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1436 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1437 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1438
1439 if (len > max * mult) {
1440 len = max * mult;
1441 }
1442
1443 if (len > BUFF_SIZE) {
1444 return USB_RET_PROCERR;
1445 }
1446
1447 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1448 if (off + len > 4096) {
1449 /* transfer crosses page border */
1450 uint32_t len2 = off + len - 4096;
1451 uint32_t len1 = len - len2;
1452 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1453 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1454 } else {
1455 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1456 }
1457
1458 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1459
1460 dev = ehci_find_device(ehci, devaddr);
1461 ep = usb_ep_get(dev, pid, endp);
1462 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1463 usb_packet_setup(&ehci->ipacket, pid, ep);
1464 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1465 ret = usb_handle_packet(dev, &ehci->ipacket);
1466 assert(ret != USB_RET_ASYNC);
1467 usb_packet_unmap(&ehci->ipacket);
1468 } else {
1469 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1470 ret = USB_RET_NAK;
1471 }
1472 qemu_sglist_destroy(&ehci->isgl);
1473
1474 if (ret == USB_RET_NAK) {
1475 /* no data for us, so do a zero-length transfer */
1476 ret = 0;
1477 }
1478
1479 if (ret >= 0) {
1480 if (!dir) {
1481 /* OUT */
1482 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1483 } else {
1484 /* IN */
1485 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1486 }
1487 } else {
1488 switch (ret) {
1489 default:
1490 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1491 /* Fall through */
1492 case USB_RET_NODEV:
1493 /* 3.3.2: XACTERR is only allowed on IN transactions */
1494 if (dir) {
1495 itd->transact[i] |= ITD_XACT_XACTERR;
1496 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1497 }
1498 break;
1499 case USB_RET_BABBLE:
1500 itd->transact[i] |= ITD_XACT_BABBLE;
1501 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1502 break;
1503 }
1504 }
1505 if (itd->transact[i] & ITD_XACT_IOC) {
1506 ehci_record_interrupt(ehci, USBSTS_INT);
1507 }
1508 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1509 }
1510 }
1511 return 0;
1512 }
1513
1514 /* This state is the entry point for asynchronous schedule
1515 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1516 */
1517 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1518 {
1519 EHCIqh qh;
1520 int i = 0;
1521 int again = 0;
1522 uint32_t entry = ehci->asynclistaddr;
1523
1524 /* set reclamation flag at start event (4.8.6) */
1525 if (async) {
1526 ehci_set_usbsts(ehci, USBSTS_REC);
1527 }
1528
1529 ehci_queues_rip_unused(ehci);
1530
1531 /* Find the head of the list (4.9.1.1) */
1532 for(i = 0; i < MAX_QH; i++) {
1533 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1534 sizeof(EHCIqh) >> 2);
1535 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1536
1537 if (qh.epchar & QH_EPCHAR_H) {
1538 if (async) {
1539 entry |= (NLPTR_TYPE_QH << 1);
1540 }
1541
1542 ehci_set_fetch_addr(ehci, async, entry);
1543 ehci_set_state(ehci, async, EST_FETCHENTRY);
1544 again = 1;
1545 goto out;
1546 }
1547
1548 entry = qh.next;
1549 if (entry == ehci->asynclistaddr) {
1550 break;
1551 }
1552 }
1553
1554 /* no head found for list. */
1555
1556 ehci_set_state(ehci, async, EST_ACTIVE);
1557
1558 out:
1559 return again;
1560 }
1561
1562
1563 /* This state is the entry point for periodic schedule processing as
1564 * well as being a continuation state for async processing.
1565 */
1566 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1567 {
1568 int again = 0;
1569 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1570
1571 if (entry < 0x1000) {
1572 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1573 ehci_set_state(ehci, async, EST_ACTIVE);
1574 goto out;
1575 }
1576
1577 /* section 4.8, only QH in async schedule */
1578 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1579 fprintf(stderr, "non queue head request in async schedule\n");
1580 return -1;
1581 }
1582
1583 switch (NLPTR_TYPE_GET(entry)) {
1584 case NLPTR_TYPE_QH:
1585 ehci_set_state(ehci, async, EST_FETCHQH);
1586 again = 1;
1587 break;
1588
1589 case NLPTR_TYPE_ITD:
1590 ehci_set_state(ehci, async, EST_FETCHITD);
1591 again = 1;
1592 break;
1593
1594 case NLPTR_TYPE_STITD:
1595 ehci_set_state(ehci, async, EST_FETCHSITD);
1596 again = 1;
1597 break;
1598
1599 default:
1600 /* TODO: handle FSTN type */
1601 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1602 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1603 return -1;
1604 }
1605
1606 out:
1607 return again;
1608 }
1609
1610 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1611 {
1612 uint32_t entry;
1613 EHCIQueue *q;
1614 int reload;
1615
1616 entry = ehci_get_fetch_addr(ehci, async);
1617 q = ehci_find_queue_by_qh(ehci, entry);
1618 if (NULL == q) {
1619 q = ehci_alloc_queue(ehci, async);
1620 }
1621 q->qhaddr = entry;
1622 q->seen++;
1623
1624 if (q->seen > 1) {
1625 /* we are going in circles -- stop processing */
1626 ehci_set_state(ehci, async, EST_ACTIVE);
1627 q = NULL;
1628 goto out;
1629 }
1630
1631 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1632 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1633 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1634
1635 if (q->async == EHCI_ASYNC_INFLIGHT) {
1636 /* I/O still in progress -- skip queue */
1637 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1638 goto out;
1639 }
1640 if (q->async == EHCI_ASYNC_FINISHED) {
1641 /* I/O finished -- continue processing queue */
1642 trace_usb_ehci_queue_action(q, "resume");
1643 ehci_set_state(ehci, async, EST_EXECUTING);
1644 goto out;
1645 }
1646
1647 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1648
1649 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1650 if (ehci->usbsts & USBSTS_REC) {
1651 ehci_clear_usbsts(ehci, USBSTS_REC);
1652 } else {
1653 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1654 " - done processing\n", q->qhaddr);
1655 ehci_set_state(ehci, async, EST_ACTIVE);
1656 q = NULL;
1657 goto out;
1658 }
1659 }
1660
1661 #if EHCI_DEBUG
1662 if (q->qhaddr != q->qh.next) {
1663 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1664 q->qhaddr,
1665 q->qh.epchar & QH_EPCHAR_H,
1666 q->qh.token & QTD_TOKEN_HALT,
1667 q->qh.token & QTD_TOKEN_ACTIVE,
1668 q->qh.next);
1669 }
1670 #endif
1671
1672 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1673 if (reload) {
1674 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1675 }
1676
1677 if (q->qh.token & QTD_TOKEN_HALT) {
1678 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1679
1680 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1681 q->qtdaddr = q->qh.current_qtd;
1682 ehci_set_state(ehci, async, EST_FETCHQTD);
1683
1684 } else {
1685 /* EHCI spec version 1.0 Section 4.10.2 */
1686 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1687 }
1688
1689 out:
1690 return q;
1691 }
1692
1693 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1694 {
1695 uint32_t entry;
1696 EHCIitd itd;
1697
1698 assert(!async);
1699 entry = ehci_get_fetch_addr(ehci, async);
1700
1701 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1702 sizeof(EHCIitd) >> 2);
1703 ehci_trace_itd(ehci, entry, &itd);
1704
1705 if (ehci_process_itd(ehci, &itd) != 0) {
1706 return -1;
1707 }
1708
1709 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1710 sizeof(EHCIitd) >> 2);
1711 ehci_set_fetch_addr(ehci, async, itd.next);
1712 ehci_set_state(ehci, async, EST_FETCHENTRY);
1713
1714 return 1;
1715 }
1716
1717 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1718 {
1719 uint32_t entry;
1720 EHCIsitd sitd;
1721
1722 assert(!async);
1723 entry = ehci_get_fetch_addr(ehci, async);
1724
1725 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1726 sizeof(EHCIsitd) >> 2);
1727 ehci_trace_sitd(ehci, entry, &sitd);
1728
1729 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1730 /* siTD is not active, nothing to do */;
1731 } else {
1732 /* TODO: split transfers are not implemented */
1733 fprintf(stderr, "WARNING: Skipping active siTD\n");
1734 }
1735
1736 ehci_set_fetch_addr(ehci, async, sitd.next);
1737 ehci_set_state(ehci, async, EST_FETCHENTRY);
1738 return 1;
1739 }
1740
1741 /* Section 4.10.2 - paragraph 3 */
1742 static int ehci_state_advqueue(EHCIQueue *q, int async)
1743 {
1744 #if 0
1745 /* TO-DO: 4.10.2 - paragraph 2
1746 * if I-bit is set to 1 and QH is not active
1747 * go to horizontal QH
1748 */
1749 if (I-bit set) {
1750 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1751 goto out;
1752 }
1753 #endif
1754
1755 /*
1756 * want data and alt-next qTD is valid
1757 */
1758 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1759 (q->qh.altnext_qtd > 0x1000) &&
1760 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1761 q->qtdaddr = q->qh.altnext_qtd;
1762 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1763
1764 /*
1765 * next qTD is valid
1766 */
1767 } else if ((q->qh.next_qtd > 0x1000) &&
1768 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1769 q->qtdaddr = q->qh.next_qtd;
1770 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1771
1772 /*
1773 * no valid qTD, try next QH
1774 */
1775 } else {
1776 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1777 }
1778
1779 return 1;
1780 }
1781
1782 /* Section 4.10.2 - paragraph 4 */
1783 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1784 {
1785 int again = 0;
1786
1787 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd,
1788 sizeof(EHCIqtd) >> 2);
1789 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1790
1791 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1792 ehci_set_state(q->ehci, async, EST_EXECUTE);
1793 again = 1;
1794 } else {
1795 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1796 again = 1;
1797 }
1798
1799 return again;
1800 }
1801
1802 static int ehci_state_horizqh(EHCIQueue *q, int async)
1803 {
1804 int again = 0;
1805
1806 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1807 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1808 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1809 again = 1;
1810 } else {
1811 ehci_set_state(q->ehci, async, EST_ACTIVE);
1812 }
1813
1814 return again;
1815 }
1816
1817 /*
1818 * Write the qh back to guest physical memory. This step isn't
1819 * in the EHCI spec but we need to do it since we don't share
1820 * physical memory with our guest VM.
1821 *
1822 * The first three dwords are read-only for the EHCI, so skip them
1823 * when writing back the qh.
1824 */
1825 static void ehci_flush_qh(EHCIQueue *q)
1826 {
1827 uint32_t *qh = (uint32_t *) &q->qh;
1828 uint32_t dwords = sizeof(EHCIqh) >> 2;
1829 uint32_t addr = NLPTR_GET(q->qhaddr);
1830
1831 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1832 }
1833
1834 static int ehci_state_execute(EHCIQueue *q, int async)
1835 {
1836 int again = 0;
1837 int reload, nakcnt;
1838 int smask;
1839
1840 if (ehci_qh_do_overlay(q) != 0) {
1841 return -1;
1842 }
1843
1844 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1845
1846 if (!smask) {
1847 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1848 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1849 if (reload && !nakcnt) {
1850 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1851 again = 1;
1852 goto out;
1853 }
1854 }
1855
1856 // TODO verify enough time remains in the uframe as in 4.4.1.1
1857 // TODO write back ptr to async list when done or out of time
1858 // TODO Windows does not seem to ever set the MULT field
1859
1860 if (!async) {
1861 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1862 if (!transactCtr) {
1863 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1864 again = 1;
1865 goto out;
1866 }
1867 }
1868
1869 if (async) {
1870 ehci_set_usbsts(q->ehci, USBSTS_REC);
1871 }
1872
1873 q->usb_status = ehci_execute(q);
1874 if (q->usb_status == USB_RET_PROCERR) {
1875 again = -1;
1876 goto out;
1877 }
1878 if (q->usb_status == USB_RET_ASYNC) {
1879 ehci_flush_qh(q);
1880 trace_usb_ehci_queue_action(q, "suspend");
1881 q->async = EHCI_ASYNC_INFLIGHT;
1882 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1883 again = 1;
1884 goto out;
1885 }
1886
1887 ehci_set_state(q->ehci, async, EST_EXECUTING);
1888 again = 1;
1889
1890 out:
1891 return again;
1892 }
1893
1894 static int ehci_state_executing(EHCIQueue *q, int async)
1895 {
1896 int again = 0;
1897 int reload, nakcnt;
1898
1899 ehci_execute_complete(q);
1900 if (q->usb_status == USB_RET_ASYNC) {
1901 goto out;
1902 }
1903 if (q->usb_status == USB_RET_PROCERR) {
1904 again = -1;
1905 goto out;
1906 }
1907
1908 // 4.10.3
1909 if (!async) {
1910 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1911 transactCtr--;
1912 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1913 // 4.10.3, bottom of page 82, should exit this state when transaction
1914 // counter decrements to 0
1915 }
1916
1917 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1918 if (reload) {
1919 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1920 if (q->usb_status == USB_RET_NAK) {
1921 if (nakcnt) {
1922 nakcnt--;
1923 }
1924 } else {
1925 nakcnt = reload;
1926 }
1927 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1928 }
1929
1930 /* 4.10.5 */
1931 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1932 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1933 } else {
1934 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1935 }
1936
1937 again = 1;
1938
1939 out:
1940 ehci_flush_qh(q);
1941 return again;
1942 }
1943
1944
1945 static int ehci_state_writeback(EHCIQueue *q, int async)
1946 {
1947 int again = 0;
1948
1949 /* Write back the QTD from the QH area */
1950 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1951 put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd,
1952 sizeof(EHCIqtd) >> 2);
1953
1954 /*
1955 * EHCI specs say go horizontal here.
1956 *
1957 * We can also advance the queue here for performance reasons. We
1958 * need to take care to only take that shortcut in case we've
1959 * processed the qtd just written back without errors, i.e. halt
1960 * bit is clear.
1961 */
1962 if (q->qh.token & QTD_TOKEN_HALT) {
1963 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1964 again = 1;
1965 } else {
1966 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1967 again = 1;
1968 }
1969 return again;
1970 }
1971
1972 /*
1973 * This is the state machine that is common to both async and periodic
1974 */
1975
1976 static void ehci_advance_state(EHCIState *ehci,
1977 int async)
1978 {
1979 EHCIQueue *q = NULL;
1980 int again;
1981 int iter = 0;
1982
1983 do {
1984 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1985 iter++;
1986 /* if we are roaming a lot of QH without executing a qTD
1987 * something is wrong with the linked list. TO-DO: why is
1988 * this hack needed?
1989 */
1990 assert(iter < MAX_ITERATIONS);
1991 #if 0
1992 if (iter > MAX_ITERATIONS) {
1993 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1994 ehci_set_state(ehci, async, EST_ACTIVE);
1995 break;
1996 }
1997 #endif
1998 }
1999 switch(ehci_get_state(ehci, async)) {
2000 case EST_WAITLISTHEAD:
2001 again = ehci_state_waitlisthead(ehci, async);
2002 break;
2003
2004 case EST_FETCHENTRY:
2005 again = ehci_state_fetchentry(ehci, async);
2006 break;
2007
2008 case EST_FETCHQH:
2009 q = ehci_state_fetchqh(ehci, async);
2010 again = q ? 1 : 0;
2011 break;
2012
2013 case EST_FETCHITD:
2014 again = ehci_state_fetchitd(ehci, async);
2015 break;
2016
2017 case EST_FETCHSITD:
2018 again = ehci_state_fetchsitd(ehci, async);
2019 break;
2020
2021 case EST_ADVANCEQUEUE:
2022 again = ehci_state_advqueue(q, async);
2023 break;
2024
2025 case EST_FETCHQTD:
2026 again = ehci_state_fetchqtd(q, async);
2027 break;
2028
2029 case EST_HORIZONTALQH:
2030 again = ehci_state_horizqh(q, async);
2031 break;
2032
2033 case EST_EXECUTE:
2034 iter = 0;
2035 again = ehci_state_execute(q, async);
2036 break;
2037
2038 case EST_EXECUTING:
2039 assert(q != NULL);
2040 again = ehci_state_executing(q, async);
2041 break;
2042
2043 case EST_WRITEBACK:
2044 assert(q != NULL);
2045 again = ehci_state_writeback(q, async);
2046 break;
2047
2048 default:
2049 fprintf(stderr, "Bad state!\n");
2050 again = -1;
2051 assert(0);
2052 break;
2053 }
2054
2055 if (again < 0) {
2056 fprintf(stderr, "processing error - resetting ehci HC\n");
2057 ehci_reset(ehci);
2058 again = 0;
2059 assert(0);
2060 }
2061 }
2062 while (again);
2063
2064 ehci_commit_interrupt(ehci);
2065 }
2066
2067 static void ehci_advance_async_state(EHCIState *ehci)
2068 {
2069 int async = 1;
2070
2071 switch(ehci_get_state(ehci, async)) {
2072 case EST_INACTIVE:
2073 if (!(ehci->usbcmd & USBCMD_ASE)) {
2074 break;
2075 }
2076 ehci_set_usbsts(ehci, USBSTS_ASS);
2077 ehci_set_state(ehci, async, EST_ACTIVE);
2078 // No break, fall through to ACTIVE
2079
2080 case EST_ACTIVE:
2081 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2082 ehci_clear_usbsts(ehci, USBSTS_ASS);
2083 ehci_set_state(ehci, async, EST_INACTIVE);
2084 break;
2085 }
2086
2087 /* If the doorbell is set, the guest wants to make a change to the
2088 * schedule. The host controller needs to release cached data.
2089 * (section 4.8.2)
2090 */
2091 if (ehci->usbcmd & USBCMD_IAAD) {
2092 DPRINTF("ASYNC: doorbell request acknowledged\n");
2093 ehci->usbcmd &= ~USBCMD_IAAD;
2094 ehci_set_interrupt(ehci, USBSTS_IAA);
2095 break;
2096 }
2097
2098 /* make sure guest has acknowledged */
2099 /* TO-DO: is this really needed? */
2100 if (ehci->usbsts & USBSTS_IAA) {
2101 DPRINTF("IAA status bit still set.\n");
2102 break;
2103 }
2104
2105 /* check that address register has been set */
2106 if (ehci->asynclistaddr == 0) {
2107 break;
2108 }
2109
2110 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2111 ehci_advance_state(ehci, async);
2112 break;
2113
2114 default:
2115 /* this should only be due to a developer mistake */
2116 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2117 "Resetting to active\n", ehci->astate);
2118 assert(0);
2119 }
2120 }
2121
2122 static void ehci_advance_periodic_state(EHCIState *ehci)
2123 {
2124 uint32_t entry;
2125 uint32_t list;
2126 int async = 0;
2127
2128 // 4.6
2129
2130 switch(ehci_get_state(ehci, async)) {
2131 case EST_INACTIVE:
2132 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2133 ehci_set_usbsts(ehci, USBSTS_PSS);
2134 ehci_set_state(ehci, async, EST_ACTIVE);
2135 // No break, fall through to ACTIVE
2136 } else
2137 break;
2138
2139 case EST_ACTIVE:
2140 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2141 ehci_clear_usbsts(ehci, USBSTS_PSS);
2142 ehci_set_state(ehci, async, EST_INACTIVE);
2143 break;
2144 }
2145
2146 list = ehci->periodiclistbase & 0xfffff000;
2147 /* check that register has been set */
2148 if (list == 0) {
2149 break;
2150 }
2151 list |= ((ehci->frindex & 0x1ff8) >> 1);
2152
2153 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2154 entry = le32_to_cpu(entry);
2155
2156 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2157 ehci->frindex / 8, list, entry);
2158 ehci_set_fetch_addr(ehci, async,entry);
2159 ehci_set_state(ehci, async, EST_FETCHENTRY);
2160 ehci_advance_state(ehci, async);
2161 break;
2162
2163 default:
2164 /* this should only be due to a developer mistake */
2165 fprintf(stderr, "ehci: Bad periodic state %d. "
2166 "Resetting to active\n", ehci->pstate);
2167 assert(0);
2168 }
2169 }
2170
2171 static void ehci_frame_timer(void *opaque)
2172 {
2173 EHCIState *ehci = opaque;
2174 int64_t expire_time, t_now;
2175 uint64_t ns_elapsed;
2176 int frames;
2177 int i;
2178 int skipped_frames = 0;
2179
2180 t_now = qemu_get_clock_ns(vm_clock);
2181 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2182
2183 ns_elapsed = t_now - ehci->last_run_ns;
2184 frames = ns_elapsed / FRAME_TIMER_NS;
2185
2186 for (i = 0; i < frames; i++) {
2187 if ( !(ehci->usbsts & USBSTS_HALT)) {
2188 if (ehci->isoch_pause <= 0) {
2189 ehci->frindex += 8;
2190 }
2191
2192 if (ehci->frindex > 0x00001fff) {
2193 ehci->frindex = 0;
2194 ehci_set_interrupt(ehci, USBSTS_FLR);
2195 }
2196
2197 ehci->sofv = (ehci->frindex - 1) >> 3;
2198 ehci->sofv &= 0x000003ff;
2199 }
2200
2201 if (frames - i > ehci->maxframes) {
2202 skipped_frames++;
2203 } else {
2204 ehci_advance_periodic_state(ehci);
2205 }
2206
2207 ehci->last_run_ns += FRAME_TIMER_NS;
2208 }
2209
2210 #if 0
2211 if (skipped_frames) {
2212 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2213 }
2214 #endif
2215
2216 /* Async is not inside loop since it executes everything it can once
2217 * called
2218 */
2219 ehci_advance_async_state(ehci);
2220
2221 qemu_mod_timer(ehci->frame_timer, expire_time);
2222 }
2223
2224
2225 static const MemoryRegionOps ehci_mem_ops = {
2226 .old_mmio = {
2227 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2228 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2229 },
2230 .endianness = DEVICE_LITTLE_ENDIAN,
2231 };
2232
2233 static int usb_ehci_initfn(PCIDevice *dev);
2234
2235 static USBPortOps ehci_port_ops = {
2236 .attach = ehci_attach,
2237 .detach = ehci_detach,
2238 .child_detach = ehci_child_detach,
2239 .wakeup = ehci_wakeup,
2240 .complete = ehci_async_complete_packet,
2241 };
2242
2243 static USBBusOps ehci_bus_ops = {
2244 .register_companion = ehci_register_companion,
2245 };
2246
2247 static const VMStateDescription vmstate_ehci = {
2248 .name = "ehci",
2249 .unmigratable = 1,
2250 };
2251
2252 static Property ehci_properties[] = {
2253 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2254 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2255 DEFINE_PROP_END_OF_LIST(),
2256 };
2257
2258 static void ehci_class_init(ObjectClass *klass, void *data)
2259 {
2260 DeviceClass *dc = DEVICE_CLASS(klass);
2261 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2262
2263 k->init = usb_ehci_initfn;
2264 k->vendor_id = PCI_VENDOR_ID_INTEL;
2265 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2266 k->revision = 0x10;
2267 k->class_id = PCI_CLASS_SERIAL_USB;
2268 dc->vmsd = &vmstate_ehci;
2269 dc->props = ehci_properties;
2270 }
2271
2272 static TypeInfo ehci_info = {
2273 .name = "usb-ehci",
2274 .parent = TYPE_PCI_DEVICE,
2275 .instance_size = sizeof(EHCIState),
2276 .class_init = ehci_class_init,
2277 };
2278
2279 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2280 {
2281 DeviceClass *dc = DEVICE_CLASS(klass);
2282 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2283
2284 k->init = usb_ehci_initfn;
2285 k->vendor_id = PCI_VENDOR_ID_INTEL;
2286 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2287 k->revision = 0x03;
2288 k->class_id = PCI_CLASS_SERIAL_USB;
2289 dc->vmsd = &vmstate_ehci;
2290 dc->props = ehci_properties;
2291 }
2292
2293 static TypeInfo ich9_ehci_info = {
2294 .name = "ich9-usb-ehci1",
2295 .parent = TYPE_PCI_DEVICE,
2296 .instance_size = sizeof(EHCIState),
2297 .class_init = ich9_ehci_class_init,
2298 };
2299
2300 static int usb_ehci_initfn(PCIDevice *dev)
2301 {
2302 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2303 uint8_t *pci_conf = s->dev.config;
2304 int i;
2305
2306 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2307
2308 /* capabilities pointer */
2309 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2310 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2311
2312 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2313 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2314 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2315
2316 // pci_conf[0x50] = 0x01; // power management caps
2317
2318 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2319 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2320 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2321
2322 pci_conf[0x64] = 0x00;
2323 pci_conf[0x65] = 0x00;
2324 pci_conf[0x66] = 0x00;
2325 pci_conf[0x67] = 0x00;
2326 pci_conf[0x68] = 0x01;
2327 pci_conf[0x69] = 0x00;
2328 pci_conf[0x6a] = 0x00;
2329 pci_conf[0x6b] = 0x00; // USBLEGSUP
2330 pci_conf[0x6c] = 0x00;
2331 pci_conf[0x6d] = 0x00;
2332 pci_conf[0x6e] = 0x00;
2333 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2334
2335 // 2.2 host controller interface version
2336 s->mmio[0x00] = (uint8_t) OPREGBASE;
2337 s->mmio[0x01] = 0x00;
2338 s->mmio[0x02] = 0x00;
2339 s->mmio[0x03] = 0x01; // HC version
2340 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2341 s->mmio[0x05] = 0x00; // No companion ports at present
2342 s->mmio[0x06] = 0x00;
2343 s->mmio[0x07] = 0x00;
2344 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2345 s->mmio[0x09] = 0x68; // EECP
2346 s->mmio[0x0a] = 0x00;
2347 s->mmio[0x0b] = 0x00;
2348
2349 s->irq = s->dev.irq[3];
2350
2351 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2352 for(i = 0; i < NB_PORTS; i++) {
2353 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2354 USB_SPEED_MASK_HIGH);
2355 s->ports[i].dev = 0;
2356 }
2357
2358 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2359 QTAILQ_INIT(&s->queues);
2360
2361 qemu_register_reset(ehci_reset, s);
2362
2363 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2364 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2365
2366 return 0;
2367 }
2368
2369 static void ehci_register_types(void)
2370 {
2371 type_register_static(&ehci_info);
2372 type_register_static(&ich9_ehci_info);
2373 }
2374
2375 type_init(ehci_register_types)
2376
2377 /*
2378 * vim: expandtab ts=4
2379 */