hw/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 #include "hw.h"
  11 #include "pc.h"
  12 #include "vt82c686.h"
  13 #include "i2c.h"
  14 #include "smbus.h"
  15 #include "pci.h"
  16 #include "isa.h"
  17 #include "sysbus.h"
  18 #include "mips.h"
  19 #include "apm.h"
  20 #include "acpi.h"
  21 #include "pm_smbus.h"
  22 #include "sysemu.h"
  23 #include "qemu-timer.h"
  24
  25 typedef uint32_t pci_addr_t;
  26 #include "pci_host.h"
  27 //#define DEBUG_VT82C686B
  28
  29 #ifdef DEBUG_VT82C686B
  30 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  31 #else
  32 #define DPRINTF(fmt, ...)
  33 #endif
  34
  35 typedef struct SuperIOConfig
  36 {
  37     uint8_t config[0xff];
  38     uint8_t index;
  39     uint8_t data;
  40 } SuperIOConfig;
  41
  42 typedef struct VT82C686BState {
  43     PCIDevice dev;
  44     SuperIOConfig superio_conf;
  45 } VT82C686BState;
  46
  47 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
  48 {
  49     int can_write;
  50     SuperIOConfig *superio_conf = opaque;
  51
  52     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x  \n", addr, data);
  53     if (addr == 0x3f0) {
  54         superio_conf->index = data & 0xff;
  55     } else {
  56         /* 0x3f1 */
  57         switch (superio_conf->index) {
  58         case 0x00 ... 0xdf:
  59         case 0xe4:
  60         case 0xe5:
  61         case 0xe9 ... 0xed:
  62         case 0xf3:
  63         case 0xf5:
  64         case 0xf7:
  65         case 0xf9 ... 0xfb:
  66         case 0xfd ... 0xff:
  67             can_write = 0;
  68             break;
  69         default:
  70             can_write = 1;
  71
  72             if (can_write) {
  73                 switch (superio_conf->index) {
  74                 case 0xe7:
  75                     if ((data & 0xff) != 0xfe) {
  76                         DPRINTF("chage uart 1 base. unsupported yet \n");
  77                     }
  78                     break;
  79                 case 0xe8:
  80                     if ((data & 0xff) != 0xbe) {
  81                         DPRINTF("chage uart 2 base. unsupported yet \n");
  82                     }
  83                     break;
  84
  85                 default:
  86                     superio_conf->config[superio_conf->index] = data & 0xff;
  87                 }
  88             }
  89         }
  90         superio_conf->config[superio_conf->index] = data & 0xff;
  91     }
  92 }
  93
  94 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
  95 {
  96     SuperIOConfig *superio_conf = opaque;
  97
  98     DPRINTF("superio_ioport_readb  address 0x%x   \n", addr);
  99     return (superio_conf->config[superio_conf->index]);
 100 }
 101
 102 static void vt82c686b_reset(void * opaque)
 103 {
 104     PCIDevice *d = opaque;
 105     uint8_t *pci_conf = d->config;
 106     VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 107
 108     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 109     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 110                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 111     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 112
 113     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 114     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 115     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 116     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 117     pci_conf[0x59] = 0x04;
 118     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 119     pci_conf[0x5f] = 0x04;
 120     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 121
 122     vt82c->superio_conf.config[0xe0] = 0x3c;
 123     vt82c->superio_conf.config[0xe2] = 0x03;
 124     vt82c->superio_conf.config[0xe3] = 0xfc;
 125     vt82c->superio_conf.config[0xe6] = 0xde;
 126     vt82c->superio_conf.config[0xe7] = 0xfe;
 127     vt82c->superio_conf.config[0xe8] = 0xbe;
 128 }
 129
 130 /* write config pci function0 registers. PCI-ISA bridge */
 131 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
 132                                    uint32_t val, int len)
 133 {
 134     VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
 135
 136     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x \n",
 137            address, val, len);
 138
 139     pci_default_write_config(d, address, val, len);
 140     if (address == 0x85) {  /* enable or disable super IO configure */
 141         if (val & 0x2) {
 142             /* floppy also uses 0x3f0 and 0x3f1.
 143              * But we do not emulate flopy,so just set it here. */
 144             isa_unassign_ioport(0x3f0, 2);
 145             register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
 146                                  &vt686->superio_conf);
 147             register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
 148                                   &vt686->superio_conf);
 149         } else {
 150             isa_unassign_ioport(0x3f0, 2);
 151         }
 152     }
 153 }
 154
 155 #define ACPI_DBG_IO_ADDR  0xb044
 156
 157 typedef struct VT686PMState {
 158     PCIDevice dev;
 159     uint16_t pmsts;
 160     uint16_t pmen;
 161     uint16_t pmcntrl;
 162     APMState apm;
 163     QEMUTimer *tmr_timer;
 164     int64_t tmr_overflow_time;
 165     PMSMBus smb;
 166     uint32_t smb_io_base;
 167 } VT686PMState;
 168
 169 typedef struct VT686AC97State {
 170     PCIDevice dev;
 171 } VT686AC97State;
 172
 173 typedef struct VT686MC97State {
 174     PCIDevice dev;
 175 } VT686MC97State;
 176
 177 #define RTC_EN    (1 << 10)
 178 #define PWRBTN_EN (1 << 8)
 179 #define GBL_EN    (1 << 5)
 180 #define TMROF_EN  (1 << 0)
 181 #define SUS_EN    (1 << 13)
 182
 183 #define ACPI_ENABLE  0xf1
 184 #define ACPI_DISABLE 0xf0
 185
 186 static uint32_t get_pmtmr(VT686PMState *s)
 187 {
 188     uint32_t d;
 189     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
 190     return d & 0xffffff;
 191 }
 192
 193 static int get_pmsts(VT686PMState *s)
 194 {
 195     int64_t d;
 196     int pmsts;
 197     pmsts = s->pmsts;
 198     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
 199     if (d >= s->tmr_overflow_time)
 200         s->pmsts |= TMROF_EN;
 201     return pmsts;
 202 }
 203
 204 static void pm_update_sci(VT686PMState *s)
 205 {
 206     int sci_level, pmsts;
 207     int64_t expire_time;
 208
 209     pmsts = get_pmsts(s);
 210     sci_level = (((pmsts & s->pmen) &
 211                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 212     qemu_set_irq(s->dev.irq[0], sci_level);
 213     /* schedule a timer interruption if needed */
 214     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 215         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_TIMER_FREQUENCY);
 216         qemu_mod_timer(s->tmr_timer, expire_time);
 217     } else {
 218         qemu_del_timer(s->tmr_timer);
 219     }
 220 }
 221
 222 static void pm_tmr_timer(void *opaque)
 223 {
 224     VT686PMState *s = opaque;
 225     pm_update_sci(s);
 226 }
 227
 228 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 229 {
 230     VT686PMState *s = opaque;
 231
 232     addr &= 0x0f;
 233     switch (addr) {
 234     case 0x00:
 235         {
 236             int64_t d;
 237             int pmsts;
 238             pmsts = get_pmsts(s);
 239             if (pmsts & val & TMROF_EN) {
 240                 /* if TMRSTS is reset, then compute the new overflow time */
 241                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
 242                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 243             }
 244             s->pmsts &= ~val;
 245             pm_update_sci(s);
 246         }
 247         break;
 248     case 0x02:
 249         s->pmen = val;
 250         pm_update_sci(s);
 251         break;
 252     case 0x04:
 253         {
 254             int sus_typ;
 255             s->pmcntrl = val & ~(SUS_EN);
 256             if (val & SUS_EN) {
 257                 /* change suspend type */
 258                 sus_typ = (val >> 10) & 3;
 259                 switch (sus_typ) {
 260                 case 0: /* soft power off */
 261                     qemu_system_shutdown_request();
 262                     break;
 263                 default:
 264                     break;
 265                 }
 266             }
 267         }
 268         break;
 269     default:
 270         break;
 271     }
 272     DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
 273 }
 274
 275 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 276 {
 277     VT686PMState *s = opaque;
 278     uint32_t val;
 279
 280     addr &= 0x0f;
 281     switch (addr) {
 282     case 0x00:
 283         val = get_pmsts(s);
 284         break;
 285     case 0x02:
 286         val = s->pmen;
 287         break;
 288     case 0x04:
 289         val = s->pmcntrl;
 290         break;
 291     default:
 292         val = 0;
 293         break;
 294     }
 295     DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
 296     return val;
 297 }
 298
 299 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 300 {
 301     addr &= 0x0f;
 302     DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
 303 }
 304
 305 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 306 {
 307     VT686PMState *s = opaque;
 308     uint32_t val;
 309
 310     addr &= 0x0f;
 311     switch (addr) {
 312     case 0x08:
 313         val = get_pmtmr(s);
 314         break;
 315     default:
 316         val = 0;
 317         break;
 318     }
 319     DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 320     return val;
 321 }
 322
 323 static void pm_io_space_update(VT686PMState *s)
 324 {
 325     uint32_t pm_io_base;
 326
 327     if (s->dev.config[0x80] & 1) {
 328         pm_io_base = pci_get_long(s->dev.config + 0x40);
 329         pm_io_base &= 0xffc0;
 330
 331         /* XXX: need to improve memory and ioport allocation */
 332         DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 333         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 334         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 335         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 336         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 337     }
 338 }
 339
 340 static void pm_write_config(PCIDevice *d,
 341                             uint32_t address, uint32_t val, int len)
 342 {
 343     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x \n",
 344            address, val, len);
 345     pci_default_write_config(d, address, val, len);
 346 }
 347
 348 static int vmstate_acpi_post_load(void *opaque, int version_id)
 349 {
 350     VT686PMState *s = opaque;
 351
 352     pm_io_space_update(s);
 353     return 0;
 354 }
 355
 356 static const VMStateDescription vmstate_acpi = {
 357     .name = "vt82c686b_pm",
 358     .version_id = 1,
 359     .minimum_version_id = 1,
 360     .minimum_version_id_old = 1,
 361     .post_load = vmstate_acpi_post_load,
 362     .fields      = (VMStateField []) {
 363         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 364         VMSTATE_UINT16(pmsts, VT686PMState),
 365         VMSTATE_UINT16(pmen, VT686PMState),
 366         VMSTATE_UINT16(pmcntrl, VT686PMState),
 367         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 368         VMSTATE_TIMER(tmr_timer, VT686PMState),
 369         VMSTATE_INT64(tmr_overflow_time, VT686PMState),
 370         VMSTATE_END_OF_LIST()
 371     }
 372 };
 373
 374 /*
 375  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 376  * just register a PCI device now, functionalities will be implemented later.
 377  */
 378
 379 static int vt82c686b_ac97_initfn(PCIDevice *dev)
 380 {
 381     VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
 382     uint8_t *pci_conf = s->dev.config;
 383
 384     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 385     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
 386     pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
 387     pci_config_set_revision(pci_conf, 0x50);
 388
 389     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 390                  PCI_COMMAND_PARITY);
 391     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 392                  PCI_STATUS_DEVSEL_MEDIUM);
 393     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 394
 395     return 0;
 396 }
 397
 398 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 399 {
 400     PCIDevice *dev;
 401
 402     dev = pci_create(bus, devfn, "VT82C686B_AC97");
 403     qdev_init_nofail(&dev->qdev);
 404 }
 405
 406 static PCIDeviceInfo via_ac97_info = {
 407     .qdev.name          = "VT82C686B_AC97",
 408     .qdev.desc          = "AC97",
 409     .qdev.size          = sizeof(VT686AC97State),
 410     .init               = vt82c686b_ac97_initfn,
 411 };
 412
 413 static void vt82c686b_ac97_register(void)
 414 {
 415     pci_qdev_register(&via_ac97_info);
 416 }
 417
 418 device_init(vt82c686b_ac97_register);
 419
 420 static int vt82c686b_mc97_initfn(PCIDevice *dev)
 421 {
 422     VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
 423     uint8_t *pci_conf = s->dev.config;
 424
 425     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 426     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
 427     pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
 428     pci_config_set_revision(pci_conf, 0x30);
 429
 430     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 431                  PCI_COMMAND_VGA_PALETTE);
 432     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 433     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 434
 435     return 0;
 436 }
 437
 438 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 439 {
 440     PCIDevice *dev;
 441
 442     dev = pci_create(bus, devfn, "VT82C686B_MC97");
 443     qdev_init_nofail(&dev->qdev);
 444 }
 445
 446 static PCIDeviceInfo via_mc97_info = {
 447     .qdev.name          = "VT82C686B_MC97",
 448     .qdev.desc          = "MC97",
 449     .qdev.size          = sizeof(VT686MC97State),
 450     .init               = vt82c686b_mc97_initfn,
 451 };
 452
 453 static void vt82c686b_mc97_register(void)
 454 {
 455     pci_qdev_register(&via_mc97_info);
 456 }
 457
 458 device_init(vt82c686b_mc97_register);
 459
 460 /* vt82c686 pm init */
 461 static int vt82c686b_pm_initfn(PCIDevice *dev)
 462 {
 463     VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
 464     uint8_t *pci_conf;
 465
 466     pci_conf = s->dev.config;
 467     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 468     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
 469     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 470     pci_config_set_revision(pci_conf, 0x40);
 471
 472     pci_set_word(pci_conf + PCI_COMMAND, 0);
 473     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 474                  PCI_STATUS_DEVSEL_MEDIUM);
 475
 476     /* 0x48-0x4B is Power Management I/O Base */
 477     pci_set_long(pci_conf + 0x48, 0x00000001);
 478
 479     /* SMB ports:0xeee0~0xeeef */
 480     s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
 481     pci_conf[0x90] = s->smb_io_base | 1;
 482     pci_conf[0x91] = s->smb_io_base >> 8;
 483     pci_conf[0xd2] = 0x90;
 484     register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
 485     register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
 486
 487     apm_init(&s->apm, NULL, s);
 488
 489     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 490
 491     pm_smbus_init(&s->dev.qdev, &s->smb);
 492
 493     return 0;
 494 }
 495
 496 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 497                        qemu_irq sci_irq)
 498 {
 499     PCIDevice *dev;
 500     VT686PMState *s;
 501
 502     dev = pci_create(bus, devfn, "VT82C686B_PM");
 503     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 504
 505     s = DO_UPCAST(VT686PMState, dev, dev);
 506
 507     qdev_init_nofail(&dev->qdev);
 508
 509     return s->smb.smbus;
 510 }
 511
 512 static PCIDeviceInfo via_pm_info = {
 513     .qdev.name          = "VT82C686B_PM",
 514     .qdev.desc          = "PM",
 515     .qdev.size          = sizeof(VT686PMState),
 516     .qdev.vmsd          = &vmstate_acpi,
 517     .init               = vt82c686b_pm_initfn,
 518     .config_write       = pm_write_config,
 519     .qdev.props         = (Property[]) {
 520         DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 521         DEFINE_PROP_END_OF_LIST(),
 522     }
 523 };
 524
 525 static void vt82c686b_pm_register(void)
 526 {
 527     pci_qdev_register(&via_pm_info);
 528 }
 529
 530 device_init(vt82c686b_pm_register);
 531
 532 static const VMStateDescription vmstate_via = {
 533     .name = "vt82c686b",
 534     .version_id = 1,
 535     .minimum_version_id = 1,
 536     .minimum_version_id_old = 1,
 537     .fields      = (VMStateField []) {
 538         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 539         VMSTATE_END_OF_LIST()
 540     }
 541 };
 542
 543 /* init the PCI-to-ISA bridge */
 544 static int vt82c686b_initfn(PCIDevice *d)
 545 {
 546     uint8_t *pci_conf;
 547     uint8_t *wmask;
 548     int i;
 549
 550     isa_bus_new(&d->qdev);
 551
 552     pci_conf = d->config;
 553     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 554     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
 555     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 556     pci_config_set_prog_interface(pci_conf, 0x0);
 557     pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
 558
 559     wmask = d->wmask;
 560     for (i = 0x00; i < 0xff; i++) {
 561        if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
 562            wmask[i] = 0x00;
 563        }
 564     }
 565
 566     qemu_register_reset(vt82c686b_reset, d);
 567
 568     return 0;
 569 }
 570
 571 int vt82c686b_init(PCIBus *bus, int devfn)
 572 {
 573     PCIDevice *d;
 574
 575     d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
 576
 577     return d->devfn;
 578 }
 579
 580 static PCIDeviceInfo via_info = {
 581     .qdev.name    = "VT82C686B",
 582     .qdev.desc    = "ISA bridge",
 583     .qdev.size    = sizeof(VT82C686BState),
 584     .qdev.vmsd    = &vmstate_via,
 585     .qdev.no_user = 1,
 586     .init         = vt82c686b_initfn,
 587     .config_write = vt82c686b_write_config,
 588 };
 589
 590 static void vt82c686b_register(void)
 591 {
 592     pci_qdev_register(&via_info);
 593 }
 594 device_init(vt82c686b_register);