hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30 #include "sysemu.h"
  31
  32 //#define DEBUG_SERIAL
  33
  34 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  35
  36 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  37 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  38 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  39 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  40
  41 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  42 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  43
  44 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  45 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  46 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  47 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  48 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  49
  50 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  51 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  52
  53 /*
  54  * These are the definitions for the Modem Control Register
  55  */
  56 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  57 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  58 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  59 #define UART_MCR_RTS    0x02    /* RTS complement */
  60 #define UART_MCR_DTR    0x01    /* DTR complement */
  61
  62 /*
  63  * These are the definitions for the Modem Status Register
  64  */
  65 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  66 #define UART_MSR_RI     0x40    /* Ring Indicator */
  67 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  68 #define UART_MSR_CTS    0x10    /* Clear to Send */
  69 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  70 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  71 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  72 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  74
  75 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  76 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  77 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  78 #define UART_LSR_FE     0x08    /* Frame error indicator */
  79 #define UART_LSR_PE     0x04    /* Parity error indicator */
  80 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  81 #define UART_LSR_DR     0x01    /* Receiver data ready */
  82 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  83
  84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  85
  86 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  87 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  88 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  89 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  90
  91 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  92 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  93 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  94 #define UART_FCR_FE         0x01    /* FIFO Enable */
  95
  96 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  97
  98 #define XMIT_FIFO           0
  99 #define RECV_FIFO           1
 100 #define MAX_XMIT_RETRY      4
 101
 102 typedef struct SerialFIFO {
 103     uint8_t data[UART_FIFO_LENGTH];
 104     uint8_t count;
 105     uint8_t itl;                        /* Interrupt Trigger Level */
 106     uint8_t tail;
 107     uint8_t head;
 108 } SerialFIFO;
 109
 110 struct SerialState {
 111     uint16_t divider;
 112     uint8_t rbr; /* receive register */
 113     uint8_t thr; /* transmit holding register */
 114     uint8_t tsr; /* transmit shift register */
 115     uint8_t ier;
 116     uint8_t iir; /* read only */
 117     uint8_t lcr;
 118     uint8_t mcr;
 119     uint8_t lsr; /* read only */
 120     uint8_t msr; /* read only */
 121     uint8_t scr;
 122     uint8_t fcr;
 123     uint8_t fcr_vmstate; /* we can't write directly this value
 124                             it has side effects */
 125     /* NOTE: this hidden state is necessary for tx irq generation as
 126        it can be reset while reading iir */
 127     int thr_ipending;
 128     qemu_irq irq;
 129     CharDriverState *chr;
 130     int last_break_enable;
 131     int it_shift;
 132     int baudbase;
 133     int tsr_retry;
 134
 135     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 136     SerialFIFO recv_fifo;
 137     SerialFIFO xmit_fifo;
 138
 139     struct QEMUTimer *fifo_timeout_timer;
 140     int timeout_ipending;                   /* timeout interrupt pending state */
 141     struct QEMUTimer *transmit_timer;
 142
 143
 144     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 145     int poll_msl;
 146
 147     struct QEMUTimer *modem_status_poll;
 148 };
 149
 150 typedef struct ISASerialState {
 151     ISADevice dev;
 152     uint32_t index;
 153     uint32_t iobase;
 154     uint32_t isairq;
 155     SerialState state;
 156 } ISASerialState;
 157
 158 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 159
 160 static void fifo_clear(SerialState *s, int fifo)
 161 {
 162     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 163     memset(f->data, 0, UART_FIFO_LENGTH);
 164     f->count = 0;
 165     f->head = 0;
 166     f->tail = 0;
 167 }
 168
 169 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 170 {
 171     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 172
 173     /* Receive overruns do not overwrite FIFO contents. */
 174     if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
 175
 176         f->data[f->head++] = chr;
 177
 178         if (f->head == UART_FIFO_LENGTH)
 179             f->head = 0;
 180     }
 181
 182     if (f->count < UART_FIFO_LENGTH)
 183         f->count++;
 184     else if (fifo == RECV_FIFO)
 185         s->lsr |= UART_LSR_OE;
 186
 187     return 1;
 188 }
 189
 190 static uint8_t fifo_get(SerialState *s, int fifo)
 191 {
 192     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 193     uint8_t c;
 194
 195     if(f->count == 0)
 196         return 0;
 197
 198     c = f->data[f->tail++];
 199     if (f->tail == UART_FIFO_LENGTH)
 200         f->tail = 0;
 201     f->count--;
 202
 203     return c;
 204 }
 205
 206 static void serial_update_irq(SerialState *s)
 207 {
 208     uint8_t tmp_iir = UART_IIR_NO_INT;
 209
 210     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 211         tmp_iir = UART_IIR_RLSI;
 212     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 213         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 214          * this is not in the specification but is observed on existing
 215          * hardware.  */
 216         tmp_iir = UART_IIR_CTI;
 217     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 218                (!(s->fcr & UART_FCR_FE) ||
 219                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 220         tmp_iir = UART_IIR_RDI;
 221     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 222         tmp_iir = UART_IIR_THRI;
 223     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 224         tmp_iir = UART_IIR_MSI;
 225     }
 226
 227     s->iir = tmp_iir | (s->iir & 0xF0);
 228
 229     if (tmp_iir != UART_IIR_NO_INT) {
 230         qemu_irq_raise(s->irq);
 231     } else {
 232         qemu_irq_lower(s->irq);
 233     }
 234 }
 235
 236 static void serial_update_parameters(SerialState *s)
 237 {
 238     int speed, parity, data_bits, stop_bits, frame_size;
 239     QEMUSerialSetParams ssp;
 240
 241     if (s->divider == 0)
 242         return;
 243
 244     /* Start bit. */
 245     frame_size = 1;
 246     if (s->lcr & 0x08) {
 247         /* Parity bit. */
 248         frame_size++;
 249         if (s->lcr & 0x10)
 250             parity = 'E';
 251         else
 252             parity = 'O';
 253     } else {
 254             parity = 'N';
 255     }
 256     if (s->lcr & 0x04)
 257         stop_bits = 2;
 258     else
 259         stop_bits = 1;
 260
 261     data_bits = (s->lcr & 0x03) + 5;
 262     frame_size += data_bits + stop_bits;
 263     speed = s->baudbase / s->divider;
 264     ssp.speed = speed;
 265     ssp.parity = parity;
 266     ssp.data_bits = data_bits;
 267     ssp.stop_bits = stop_bits;
 268     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 269     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 270 #if 0
 271     printf("speed=%d parity=%c data=%d stop=%d\n",
 272            speed, parity, data_bits, stop_bits);
 273 #endif
 274 }
 275
 276 static void serial_update_msl(SerialState *s)
 277 {
 278     uint8_t omsr;
 279     int flags;
 280
 281     qemu_del_timer(s->modem_status_poll);
 282
 283     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 284         s->poll_msl = -1;
 285         return;
 286     }
 287
 288     omsr = s->msr;
 289
 290     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 291     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 292     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 293     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 294
 295     if (s->msr != omsr) {
 296          /* Set delta bits */
 297          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 298          /* UART_MSR_TERI only if change was from 1 -> 0 */
 299          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 300              s->msr &= ~UART_MSR_TERI;
 301          serial_update_irq(s);
 302     }
 303
 304     /* The real 16550A apparently has a 250ns response latency to line status changes.
 305        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 306
 307     if (s->poll_msl)
 308         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
 309 }
 310
 311 static void serial_xmit(void *opaque)
 312 {
 313     SerialState *s = opaque;
 314     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 315
 316     if (s->tsr_retry <= 0) {
 317         if (s->fcr & UART_FCR_FE) {
 318             s->tsr = fifo_get(s,XMIT_FIFO);
 319             if (!s->xmit_fifo.count)
 320                 s->lsr |= UART_LSR_THRE;
 321         } else {
 322             s->tsr = s->thr;
 323             s->lsr |= UART_LSR_THRE;
 324         }
 325     }
 326
 327     if (s->mcr & UART_MCR_LOOP) {
 328         /* in loopback mode, say that we just received a char */
 329         serial_receive1(s, &s->tsr, 1);
 330     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 331         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 332             s->tsr_retry++;
 333             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 334             return;
 335         } else if (s->poll_msl < 0) {
 336             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 337             drop any further failed writes instantly, until we get one that goes through.
 338             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 339             s->tsr_retry = -1;
 340         }
 341     }
 342     else {
 343         s->tsr_retry = 0;
 344     }
 345
 346     s->last_xmit_ts = qemu_get_clock(vm_clock);
 347     if (!(s->lsr & UART_LSR_THRE))
 348         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 349
 350     if (s->lsr & UART_LSR_THRE) {
 351         s->lsr |= UART_LSR_TEMT;
 352         s->thr_ipending = 1;
 353         serial_update_irq(s);
 354     }
 355 }
 356
 357
 358 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 359 {
 360     SerialState *s = opaque;
 361
 362     addr &= 7;
 363 #ifdef DEBUG_SERIAL
 364     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 365 #endif
 366     switch(addr) {
 367     default:
 368     case 0:
 369         if (s->lcr & UART_LCR_DLAB) {
 370             s->divider = (s->divider & 0xff00) | val;
 371             serial_update_parameters(s);
 372         } else {
 373             s->thr = (uint8_t) val;
 374             if(s->fcr & UART_FCR_FE) {
 375                 fifo_put(s, XMIT_FIFO, s->thr);
 376                 s->thr_ipending = 0;
 377                 s->lsr &= ~UART_LSR_TEMT;
 378                 s->lsr &= ~UART_LSR_THRE;
 379                 serial_update_irq(s);
 380             } else {
 381                 s->thr_ipending = 0;
 382                 s->lsr &= ~UART_LSR_THRE;
 383                 serial_update_irq(s);
 384             }
 385             serial_xmit(s);
 386         }
 387         break;
 388     case 1:
 389         if (s->lcr & UART_LCR_DLAB) {
 390             s->divider = (s->divider & 0x00ff) | (val << 8);
 391             serial_update_parameters(s);
 392         } else {
 393             s->ier = val & 0x0f;
 394             /* If the backend device is a real serial port, turn polling of the modem
 395                status lines on physical port on or off depending on UART_IER_MSI state */
 396             if (s->poll_msl >= 0) {
 397                 if (s->ier & UART_IER_MSI) {
 398                      s->poll_msl = 1;
 399                      serial_update_msl(s);
 400                 } else {
 401                      qemu_del_timer(s->modem_status_poll);
 402                      s->poll_msl = 0;
 403                 }
 404             }
 405             if (s->lsr & UART_LSR_THRE) {
 406                 s->thr_ipending = 1;
 407                 serial_update_irq(s);
 408             }
 409         }
 410         break;
 411     case 2:
 412         val = val & 0xFF;
 413
 414         if (s->fcr == val)
 415             break;
 416
 417         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 418         if ((val ^ s->fcr) & UART_FCR_FE)
 419             val |= UART_FCR_XFR | UART_FCR_RFR;
 420
 421         /* FIFO clear */
 422
 423         if (val & UART_FCR_RFR) {
 424             qemu_del_timer(s->fifo_timeout_timer);
 425             s->timeout_ipending=0;
 426             fifo_clear(s,RECV_FIFO);
 427         }
 428
 429         if (val & UART_FCR_XFR) {
 430             fifo_clear(s,XMIT_FIFO);
 431         }
 432
 433         if (val & UART_FCR_FE) {
 434             s->iir |= UART_IIR_FE;
 435             /* Set RECV_FIFO trigger Level */
 436             switch (val & 0xC0) {
 437             case UART_FCR_ITL_1:
 438                 s->recv_fifo.itl = 1;
 439                 break;
 440             case UART_FCR_ITL_2:
 441                 s->recv_fifo.itl = 4;
 442                 break;
 443             case UART_FCR_ITL_3:
 444                 s->recv_fifo.itl = 8;
 445                 break;
 446             case UART_FCR_ITL_4:
 447                 s->recv_fifo.itl = 14;
 448                 break;
 449             }
 450         } else
 451             s->iir &= ~UART_IIR_FE;
 452
 453         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 454         s->fcr = val & 0xC9;
 455         serial_update_irq(s);
 456         break;
 457     case 3:
 458         {
 459             int break_enable;
 460             s->lcr = val;
 461             serial_update_parameters(s);
 462             break_enable = (val >> 6) & 1;
 463             if (break_enable != s->last_break_enable) {
 464                 s->last_break_enable = break_enable;
 465                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 466                                &break_enable);
 467             }
 468         }
 469         break;
 470     case 4:
 471         {
 472             int flags;
 473             int old_mcr = s->mcr;
 474             s->mcr = val & 0x1f;
 475             if (val & UART_MCR_LOOP)
 476                 break;
 477
 478             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 479
 480                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 481
 482                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 483
 484                 if (val & UART_MCR_RTS)
 485                     flags |= CHR_TIOCM_RTS;
 486                 if (val & UART_MCR_DTR)
 487                     flags |= CHR_TIOCM_DTR;
 488
 489                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 490                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 491                    from the device/computer at the other end of the serial line */
 492                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 493             }
 494         }
 495         break;
 496     case 5:
 497         break;
 498     case 6:
 499         break;
 500     case 7:
 501         s->scr = val;
 502         break;
 503     }
 504 }
 505
 506 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 507 {
 508     SerialState *s = opaque;
 509     uint32_t ret;
 510
 511     addr &= 7;
 512     switch(addr) {
 513     default:
 514     case 0:
 515         if (s->lcr & UART_LCR_DLAB) {
 516             ret = s->divider & 0xff;
 517         } else {
 518             if(s->fcr & UART_FCR_FE) {
 519                 ret = fifo_get(s,RECV_FIFO);
 520                 if (s->recv_fifo.count == 0)
 521                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 522                 else
 523                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 524                 s->timeout_ipending = 0;
 525             } else {
 526                 ret = s->rbr;
 527                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 528             }
 529             serial_update_irq(s);
 530             if (!(s->mcr & UART_MCR_LOOP)) {
 531                 /* in loopback mode, don't receive any data */
 532                 qemu_chr_accept_input(s->chr);
 533             }
 534         }
 535         break;
 536     case 1:
 537         if (s->lcr & UART_LCR_DLAB) {
 538             ret = (s->divider >> 8) & 0xff;
 539         } else {
 540             ret = s->ier;
 541         }
 542         break;
 543     case 2:
 544         ret = s->iir;
 545         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 546             s->thr_ipending = 0;
 547             serial_update_irq(s);
 548         }
 549         break;
 550     case 3:
 551         ret = s->lcr;
 552         break;
 553     case 4:
 554         ret = s->mcr;
 555         break;
 556     case 5:
 557         ret = s->lsr;
 558         /* Clear break and overrun interrupts */
 559         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 560             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 561             serial_update_irq(s);
 562         }
 563         break;
 564     case 6:
 565         if (s->mcr & UART_MCR_LOOP) {
 566             /* in loopback, the modem output pins are connected to the
 567                inputs */
 568             ret = (s->mcr & 0x0c) << 4;
 569             ret |= (s->mcr & 0x02) << 3;
 570             ret |= (s->mcr & 0x01) << 5;
 571         } else {
 572             if (s->poll_msl >= 0)
 573                 serial_update_msl(s);
 574             ret = s->msr;
 575             /* Clear delta bits & msr int after read, if they were set */
 576             if (s->msr & UART_MSR_ANY_DELTA) {
 577                 s->msr &= 0xF0;
 578                 serial_update_irq(s);
 579             }
 580         }
 581         break;
 582     case 7:
 583         ret = s->scr;
 584         break;
 585     }
 586 #ifdef DEBUG_SERIAL
 587     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 588 #endif
 589     return ret;
 590 }
 591
 592 static int serial_can_receive(SerialState *s)
 593 {
 594     if(s->fcr & UART_FCR_FE) {
 595         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 596         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 597         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 598         effectively overriding the ITL that the guest has set. */
 599              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 600         else
 601              return 0;
 602     } else {
 603     return !(s->lsr & UART_LSR_DR);
 604     }
 605 }
 606
 607 static void serial_receive_break(SerialState *s)
 608 {
 609     s->rbr = 0;
 610     /* When the LSR_DR is set a null byte is pushed into the fifo */
 611     fifo_put(s, RECV_FIFO, '\0');
 612     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 613     serial_update_irq(s);
 614 }
 615
 616 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 617 static void fifo_timeout_int (void *opaque) {
 618     SerialState *s = opaque;
 619     if (s->recv_fifo.count) {
 620         s->timeout_ipending = 1;
 621         serial_update_irq(s);
 622     }
 623 }
 624
 625 static int serial_can_receive1(void *opaque)
 626 {
 627     SerialState *s = opaque;
 628     return serial_can_receive(s);
 629 }
 630
 631 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 632 {
 633     SerialState *s = opaque;
 634     if(s->fcr & UART_FCR_FE) {
 635         int i;
 636         for (i = 0; i < size; i++) {
 637             fifo_put(s, RECV_FIFO, buf[i]);
 638         }
 639         s->lsr |= UART_LSR_DR;
 640         /* call the timeout receive callback in 4 char transmit time */
 641         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 642     } else {
 643         if (s->lsr & UART_LSR_DR)
 644             s->lsr |= UART_LSR_OE;
 645         s->rbr = buf[0];
 646         s->lsr |= UART_LSR_DR;
 647     }
 648     serial_update_irq(s);
 649 }
 650
 651 static void serial_event(void *opaque, int event)
 652 {
 653     SerialState *s = opaque;
 654 #ifdef DEBUG_SERIAL
 655     printf("serial: event %x\n", event);
 656 #endif
 657     if (event == CHR_EVENT_BREAK)
 658         serial_receive_break(s);
 659 }
 660
 661 static void serial_pre_save(void *opaque)
 662 {
 663     SerialState *s = opaque;
 664     s->fcr_vmstate = s->fcr;
 665 }
 666
 667 static int serial_post_load(void *opaque, int version_id)
 668 {
 669     SerialState *s = opaque;
 670
 671     if (version_id < 3) {
 672         s->fcr_vmstate = 0;
 673     }
 674     /* Initialize fcr via setter to perform essential side-effects */
 675     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 676     return 0;
 677 }
 678
 679 static const VMStateDescription vmstate_serial = {
 680     .name = "serial",
 681     .version_id = 3,
 682     .minimum_version_id = 2,
 683     .pre_save = serial_pre_save,
 684     .post_load = serial_post_load,
 685     .fields      = (VMStateField []) {
 686         VMSTATE_UINT16_V(divider, SerialState, 2),
 687         VMSTATE_UINT8(rbr, SerialState),
 688         VMSTATE_UINT8(ier, SerialState),
 689         VMSTATE_UINT8(iir, SerialState),
 690         VMSTATE_UINT8(lcr, SerialState),
 691         VMSTATE_UINT8(mcr, SerialState),
 692         VMSTATE_UINT8(lsr, SerialState),
 693         VMSTATE_UINT8(msr, SerialState),
 694         VMSTATE_UINT8(scr, SerialState),
 695         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 696         VMSTATE_END_OF_LIST()
 697     }
 698 };
 699
 700 static void serial_reset(void *opaque)
 701 {
 702     SerialState *s = opaque;
 703
 704     s->rbr = 0;
 705     s->ier = 0;
 706     s->iir = UART_IIR_NO_INT;
 707     s->lcr = 0;
 708     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 709     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 710     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 711     s->divider = 0x0C;
 712     s->mcr = UART_MCR_OUT2;
 713     s->scr = 0;
 714     s->tsr_retry = 0;
 715     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 716     s->poll_msl = 0;
 717
 718     fifo_clear(s,RECV_FIFO);
 719     fifo_clear(s,XMIT_FIFO);
 720
 721     s->last_xmit_ts = qemu_get_clock(vm_clock);
 722
 723     s->thr_ipending = 0;
 724     s->last_break_enable = 0;
 725     qemu_irq_lower(s->irq);
 726 }
 727
 728 static void serial_init_core(SerialState *s)
 729 {
 730     if (!s->chr) {
 731         fprintf(stderr, "Can't create serial device, empty char device\n");
 732         exit(1);
 733     }
 734
 735     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 736
 737     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 738     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 739
 740     qemu_register_reset(serial_reset, s);
 741
 742     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 743                           serial_event, s);
 744 }
 745
 746 /* Change the main reference oscillator frequency. */
 747 void serial_set_frequency(SerialState *s, uint32_t frequency)
 748 {
 749     s->baudbase = frequency;
 750     serial_update_parameters(s);
 751 }
 752
 753 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 754 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 755
 756 static int serial_isa_initfn(ISADevice *dev)
 757 {
 758     static int index;
 759     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 760     SerialState *s = &isa->state;
 761
 762     if (isa->index == -1)
 763         isa->index = index;
 764     if (isa->index >= MAX_SERIAL_PORTS)
 765         return -1;
 766     if (isa->iobase == -1)
 767         isa->iobase = isa_serial_io[isa->index];
 768     if (isa->isairq == -1)
 769         isa->isairq = isa_serial_irq[isa->index];
 770     index++;
 771
 772     s->baudbase = 115200;
 773     isa_init_irq(dev, &s->irq, isa->isairq);
 774     serial_init_core(s);
 775     qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
 776
 777     register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
 778     register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
 779     return 0;
 780 }
 781
 782 SerialState *serial_isa_init(int index, CharDriverState *chr)
 783 {
 784     ISADevice *dev;
 785
 786     dev = isa_create("isa-serial");
 787     qdev_prop_set_uint32(&dev->qdev, "index", index);
 788     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
 789     if (qdev_init(&dev->qdev) < 0)
 790         return NULL;
 791     return &DO_UPCAST(ISASerialState, dev, dev)->state;
 792 }
 793
 794 static const VMStateDescription vmstate_isa_serial = {
 795     .name = "serial",
 796     .version_id = 3,
 797     .minimum_version_id = 2,
 798     .fields      = (VMStateField []) {
 799         VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
 800         VMSTATE_END_OF_LIST()
 801     }
 802 };
 803
 804 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 805                          CharDriverState *chr)
 806 {
 807     SerialState *s;
 808
 809     s = qemu_mallocz(sizeof(SerialState));
 810
 811     s->irq = irq;
 812     s->baudbase = baudbase;
 813     s->chr = chr;
 814     serial_init_core(s);
 815
 816     vmstate_register(NULL, base, &vmstate_serial, s);
 817
 818     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 819     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 820     return s;
 821 }
 822
 823 /* Memory mapped interface */
 824 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 825 {
 826     SerialState *s = opaque;
 827
 828     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 829 }
 830
 831 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 832                              uint32_t value)
 833 {
 834     SerialState *s = opaque;
 835
 836     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 837 }
 838
 839 static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
 840 {
 841     SerialState *s = opaque;
 842     uint32_t val;
 843
 844     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 845     val = bswap16(val);
 846     return val;
 847 }
 848
 849 static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
 850 {
 851     SerialState *s = opaque;
 852     uint32_t val;
 853
 854     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 855     return val;
 856 }
 857
 858 static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
 859                                 uint32_t value)
 860 {
 861     SerialState *s = opaque;
 862
 863     value = bswap16(value);
 864     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 865 }
 866
 867 static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
 868                                 uint32_t value)
 869 {
 870     SerialState *s = opaque;
 871
 872     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 873 }
 874
 875 static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
 876 {
 877     SerialState *s = opaque;
 878     uint32_t val;
 879
 880     val = serial_ioport_read(s, addr >> s->it_shift);
 881     val = bswap32(val);
 882     return val;
 883 }
 884
 885 static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
 886 {
 887     SerialState *s = opaque;
 888     uint32_t val;
 889
 890     val = serial_ioport_read(s, addr >> s->it_shift);
 891     return val;
 892 }
 893
 894 static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
 895                                 uint32_t value)
 896 {
 897     SerialState *s = opaque;
 898
 899     value = bswap32(value);
 900     serial_ioport_write(s, addr >> s->it_shift, value);
 901 }
 902
 903 static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
 904                                 uint32_t value)
 905 {
 906     SerialState *s = opaque;
 907
 908     serial_ioport_write(s, addr >> s->it_shift, value);
 909 }
 910
 911 static CPUReadMemoryFunc * const serial_mm_read_be[] = {
 912     &serial_mm_readb,
 913     &serial_mm_readw_be,
 914     &serial_mm_readl_be,
 915 };
 916
 917 static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
 918     &serial_mm_writeb,
 919     &serial_mm_writew_be,
 920     &serial_mm_writel_be,
 921 };
 922
 923 static CPUReadMemoryFunc * const serial_mm_read_le[] = {
 924     &serial_mm_readb,
 925     &serial_mm_readw_le,
 926     &serial_mm_readl_le,
 927 };
 928
 929 static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
 930     &serial_mm_writeb,
 931     &serial_mm_writew_le,
 932     &serial_mm_writel_le,
 933 };
 934
 935 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 936                              qemu_irq irq, int baudbase,
 937                              CharDriverState *chr, int ioregister,
 938                              int be)
 939 {
 940     SerialState *s;
 941     int s_io_memory;
 942
 943     s = qemu_mallocz(sizeof(SerialState));
 944
 945     s->it_shift = it_shift;
 946     s->irq = irq;
 947     s->baudbase = baudbase;
 948     s->chr = chr;
 949
 950     serial_init_core(s);
 951     vmstate_register(NULL, base, &vmstate_serial, s);
 952
 953     if (ioregister) {
 954         if (be) {
 955             s_io_memory = cpu_register_io_memory(serial_mm_read_be,
 956                                                  serial_mm_write_be, s);
 957         } else {
 958             s_io_memory = cpu_register_io_memory(serial_mm_read_le,
 959                                                  serial_mm_write_le, s);
 960         }
 961         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 962     }
 963     serial_update_msl(s);
 964     return s;
 965 }
 966
 967 static ISADeviceInfo serial_isa_info = {
 968     .qdev.name  = "isa-serial",
 969     .qdev.size  = sizeof(ISASerialState),
 970     .qdev.vmsd  = &vmstate_isa_serial,
 971     .init       = serial_isa_initfn,
 972     .qdev.props = (Property[]) {
 973         DEFINE_PROP_UINT32("index", ISASerialState, index,   -1),
 974         DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  -1),
 975         DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  -1),
 976         DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 977         DEFINE_PROP_END_OF_LIST(),
 978     },
 979 };
 980
 981 static void serial_register_devices(void)
 982 {
 983     isa_qdev_register(&serial_isa_info);
 984 }
 985
 986 device_init(serial_register_devices)