hw/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 #include "hw.h"
  11 #include "pc.h"
  12 #include "vt82c686.h"
  13 #include "i2c.h"
  14 #include "smbus.h"
  15 #include "pci.h"
  16 #include "isa.h"
  17 #include "sysbus.h"
  18 #include "mips.h"
  19 #include "apm.h"
  20 #include "acpi.h"
  21 #include "pm_smbus.h"
  22 #include "sysemu.h"
  23 #include "qemu-timer.h"
  24
  25 typedef uint32_t pci_addr_t;
  26 #include "pci_host.h"
  27 //#define DEBUG_VT82C686B
  28
  29 #ifdef DEBUG_VT82C686B
  30 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  31 #else
  32 #define DPRINTF(fmt, ...)
  33 #endif
  34
  35 typedef struct SuperIOConfig
  36 {
  37     uint8_t config[0xff];
  38     uint8_t index;
  39     uint8_t data;
  40 } SuperIOConfig;
  41
  42 typedef struct VT82C686BState {
  43     PCIDevice dev;
  44     SuperIOConfig superio_conf;
  45 } VT82C686BState;
  46
  47 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
  48 {
  49     int can_write;
  50     SuperIOConfig *superio_conf = opaque;
  51
  52     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x  \n", addr, data);
  53     if (addr == 0x3f0) {
  54         superio_conf->index = data & 0xff;
  55     } else {
  56         /* 0x3f1 */
  57         switch (superio_conf->index) {
  58         case 0x00 ... 0xdf:
  59         case 0xe4:
  60         case 0xe5:
  61         case 0xe9 ... 0xed:
  62         case 0xf3:
  63         case 0xf5:
  64         case 0xf7:
  65         case 0xf9 ... 0xfb:
  66         case 0xfd ... 0xff:
  67             can_write = 0;
  68             break;
  69         default:
  70             can_write = 1;
  71
  72             if (can_write) {
  73                 switch (superio_conf->index) {
  74                 case 0xe7:
  75                     if ((data & 0xff) != 0xfe) {
  76                         DPRINTF("chage uart 1 base. unsupported yet \n");
  77                     }
  78                     break;
  79                 case 0xe8:
  80                     if ((data & 0xff) != 0xbe) {
  81                         DPRINTF("chage uart 2 base. unsupported yet \n");
  82                     }
  83                     break;
  84
  85                 default:
  86                     superio_conf->config[superio_conf->index] = data & 0xff;
  87                 }
  88             }
  89         }
  90         superio_conf->config[superio_conf->index] = data & 0xff;
  91     }
  92 }
  93
  94 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
  95 {
  96     SuperIOConfig *superio_conf = opaque;
  97
  98     DPRINTF("superio_ioport_readb  address 0x%x   \n", addr);
  99     return (superio_conf->config[superio_conf->index]);
 100 }
 101
 102 static void vt82c686b_reset(void * opaque)
 103 {
 104     PCIDevice *d = opaque;
 105     uint8_t *pci_conf = d->config;
 106     VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 107
 108     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 109     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 110                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 111     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 112
 113     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 114     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 115     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 116     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 117     pci_conf[0x59] = 0x04;
 118     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 119     pci_conf[0x5f] = 0x04;
 120     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 121
 122     vt82c->superio_conf.config[0xe0] = 0x3c;
 123     vt82c->superio_conf.config[0xe2] = 0x03;
 124     vt82c->superio_conf.config[0xe3] = 0xfc;
 125     vt82c->superio_conf.config[0xe6] = 0xde;
 126     vt82c->superio_conf.config[0xe7] = 0xfe;
 127     vt82c->superio_conf.config[0xe8] = 0xbe;
 128 }
 129
 130 /* write config pci function0 registers. PCI-ISA bridge */
 131 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
 132                                    uint32_t val, int len)
 133 {
 134     VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
 135
 136     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x \n",
 137            address, val, len);
 138
 139     pci_default_write_config(d, address, val, len);
 140     if (address == 0x85) {  /* enable or disable super IO configure */
 141         if (val & 0x2) {
 142             /* floppy also uses 0x3f0 and 0x3f1.
 143              * But we do not emulate flopy,so just set it here. */
 144             isa_unassign_ioport(0x3f0, 2);
 145             register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
 146                                  &vt686->superio_conf);
 147             register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
 148                                   &vt686->superio_conf);
 149         } else {
 150             isa_unassign_ioport(0x3f0, 2);
 151         }
 152     }
 153 }
 154
 155 #define ACPI_DBG_IO_ADDR  0xb044
 156
 157 typedef struct VT686PMState {
 158     PCIDevice dev;
 159     ACPIPM1EVT pm1a;
 160     ACPIPM1CNT pm1_cnt;
 161     APMState apm;
 162     ACPIPMTimer tmr;
 163     PMSMBus smb;
 164     uint32_t smb_io_base;
 165 } VT686PMState;
 166
 167 typedef struct VT686AC97State {
 168     PCIDevice dev;
 169 } VT686AC97State;
 170
 171 typedef struct VT686MC97State {
 172     PCIDevice dev;
 173 } VT686MC97State;
 174
 175 static void pm_update_sci(VT686PMState *s)
 176 {
 177     int sci_level, pmsts;
 178
 179     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 180     sci_level = (((pmsts & s->pm1a.en) &
 181                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 182                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 183                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 184                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 185     qemu_set_irq(s->dev.irq[0], sci_level);
 186     /* schedule a timer interruption if needed */
 187     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
 188                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 189 }
 190
 191 static void pm_tmr_timer(ACPIPMTimer *tmr)
 192 {
 193     VT686PMState *s = container_of(tmr, VT686PMState, tmr);
 194     pm_update_sci(s);
 195 }
 196
 197 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     VT686PMState *s = opaque;
 200
 201     addr &= 0x0f;
 202     switch (addr) {
 203     case 0x00:
 204         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 205         pm_update_sci(s);
 206         break;
 207     case 0x02:
 208         s->pm1a.en = val;
 209         pm_update_sci(s);
 210         break;
 211     case 0x04:
 212         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 213         break;
 214     default:
 215         break;
 216     }
 217     DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
 218 }
 219
 220 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 221 {
 222     VT686PMState *s = opaque;
 223     uint32_t val;
 224
 225     addr &= 0x0f;
 226     switch (addr) {
 227     case 0x00:
 228         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 229         break;
 230     case 0x02:
 231         val = s->pm1a.en;
 232         break;
 233     case 0x04:
 234         val = s->pm1_cnt.cnt;
 235         break;
 236     default:
 237         val = 0;
 238         break;
 239     }
 240     DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
 241     return val;
 242 }
 243
 244 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 245 {
 246     addr &= 0x0f;
 247     DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
 248 }
 249
 250 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 251 {
 252     VT686PMState *s = opaque;
 253     uint32_t val;
 254
 255     addr &= 0x0f;
 256     switch (addr) {
 257     case 0x08:
 258         val = acpi_pm_tmr_get(&s->tmr);
 259         break;
 260     default:
 261         val = 0;
 262         break;
 263     }
 264     DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 265     return val;
 266 }
 267
 268 static void pm_io_space_update(VT686PMState *s)
 269 {
 270     uint32_t pm_io_base;
 271
 272     if (s->dev.config[0x80] & 1) {
 273         pm_io_base = pci_get_long(s->dev.config + 0x40);
 274         pm_io_base &= 0xffc0;
 275
 276         /* XXX: need to improve memory and ioport allocation */
 277         DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 278         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 279         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 280         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 281         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 282     }
 283 }
 284
 285 static void pm_write_config(PCIDevice *d,
 286                             uint32_t address, uint32_t val, int len)
 287 {
 288     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x \n",
 289            address, val, len);
 290     pci_default_write_config(d, address, val, len);
 291 }
 292
 293 static int vmstate_acpi_post_load(void *opaque, int version_id)
 294 {
 295     VT686PMState *s = opaque;
 296
 297     pm_io_space_update(s);
 298     return 0;
 299 }
 300
 301 static const VMStateDescription vmstate_acpi = {
 302     .name = "vt82c686b_pm",
 303     .version_id = 1,
 304     .minimum_version_id = 1,
 305     .minimum_version_id_old = 1,
 306     .post_load = vmstate_acpi_post_load,
 307     .fields      = (VMStateField []) {
 308         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 309         VMSTATE_UINT16(pm1a.sts, VT686PMState),
 310         VMSTATE_UINT16(pm1a.en, VT686PMState),
 311         VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
 312         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 313         VMSTATE_TIMER(tmr.timer, VT686PMState),
 314         VMSTATE_INT64(tmr.overflow_time, VT686PMState),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 /*
 320  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 321  * just register a PCI device now, functionalities will be implemented later.
 322  */
 323
 324 static int vt82c686b_ac97_initfn(PCIDevice *dev)
 325 {
 326     VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
 327     uint8_t *pci_conf = s->dev.config;
 328
 329     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 330     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
 331     pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
 332     pci_config_set_revision(pci_conf, 0x50);
 333
 334     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 335                  PCI_COMMAND_PARITY);
 336     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 337                  PCI_STATUS_DEVSEL_MEDIUM);
 338     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 339
 340     return 0;
 341 }
 342
 343 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 344 {
 345     PCIDevice *dev;
 346
 347     dev = pci_create(bus, devfn, "VT82C686B_AC97");
 348     qdev_init_nofail(&dev->qdev);
 349 }
 350
 351 static PCIDeviceInfo via_ac97_info = {
 352     .qdev.name          = "VT82C686B_AC97",
 353     .qdev.desc          = "AC97",
 354     .qdev.size          = sizeof(VT686AC97State),
 355     .init               = vt82c686b_ac97_initfn,
 356 };
 357
 358 static void vt82c686b_ac97_register(void)
 359 {
 360     pci_qdev_register(&via_ac97_info);
 361 }
 362
 363 device_init(vt82c686b_ac97_register);
 364
 365 static int vt82c686b_mc97_initfn(PCIDevice *dev)
 366 {
 367     VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
 368     uint8_t *pci_conf = s->dev.config;
 369
 370     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 371     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
 372     pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
 373     pci_config_set_revision(pci_conf, 0x30);
 374
 375     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 376                  PCI_COMMAND_VGA_PALETTE);
 377     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 378     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 379
 380     return 0;
 381 }
 382
 383 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 384 {
 385     PCIDevice *dev;
 386
 387     dev = pci_create(bus, devfn, "VT82C686B_MC97");
 388     qdev_init_nofail(&dev->qdev);
 389 }
 390
 391 static PCIDeviceInfo via_mc97_info = {
 392     .qdev.name          = "VT82C686B_MC97",
 393     .qdev.desc          = "MC97",
 394     .qdev.size          = sizeof(VT686MC97State),
 395     .init               = vt82c686b_mc97_initfn,
 396 };
 397
 398 static void vt82c686b_mc97_register(void)
 399 {
 400     pci_qdev_register(&via_mc97_info);
 401 }
 402
 403 device_init(vt82c686b_mc97_register);
 404
 405 /* vt82c686 pm init */
 406 static int vt82c686b_pm_initfn(PCIDevice *dev)
 407 {
 408     VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
 409     uint8_t *pci_conf;
 410
 411     pci_conf = s->dev.config;
 412     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 413     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
 414     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 415     pci_config_set_revision(pci_conf, 0x40);
 416
 417     pci_set_word(pci_conf + PCI_COMMAND, 0);
 418     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 419                  PCI_STATUS_DEVSEL_MEDIUM);
 420
 421     /* 0x48-0x4B is Power Management I/O Base */
 422     pci_set_long(pci_conf + 0x48, 0x00000001);
 423
 424     /* SMB ports:0xeee0~0xeeef */
 425     s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
 426     pci_conf[0x90] = s->smb_io_base | 1;
 427     pci_conf[0x91] = s->smb_io_base >> 8;
 428     pci_conf[0xd2] = 0x90;
 429     register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
 430     register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
 431
 432     apm_init(&s->apm, NULL, s);
 433
 434     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 435     acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
 436
 437     pm_smbus_init(&s->dev.qdev, &s->smb);
 438
 439     return 0;
 440 }
 441
 442 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 443                        qemu_irq sci_irq)
 444 {
 445     PCIDevice *dev;
 446     VT686PMState *s;
 447
 448     dev = pci_create(bus, devfn, "VT82C686B_PM");
 449     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 450
 451     s = DO_UPCAST(VT686PMState, dev, dev);
 452
 453     qdev_init_nofail(&dev->qdev);
 454
 455     return s->smb.smbus;
 456 }
 457
 458 static PCIDeviceInfo via_pm_info = {
 459     .qdev.name          = "VT82C686B_PM",
 460     .qdev.desc          = "PM",
 461     .qdev.size          = sizeof(VT686PMState),
 462     .qdev.vmsd          = &vmstate_acpi,
 463     .init               = vt82c686b_pm_initfn,
 464     .config_write       = pm_write_config,
 465     .qdev.props         = (Property[]) {
 466         DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 467         DEFINE_PROP_END_OF_LIST(),
 468     }
 469 };
 470
 471 static void vt82c686b_pm_register(void)
 472 {
 473     pci_qdev_register(&via_pm_info);
 474 }
 475
 476 device_init(vt82c686b_pm_register);
 477
 478 static const VMStateDescription vmstate_via = {
 479     .name = "vt82c686b",
 480     .version_id = 1,
 481     .minimum_version_id = 1,
 482     .minimum_version_id_old = 1,
 483     .fields      = (VMStateField []) {
 484         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 485         VMSTATE_END_OF_LIST()
 486     }
 487 };
 488
 489 /* init the PCI-to-ISA bridge */
 490 static int vt82c686b_initfn(PCIDevice *d)
 491 {
 492     uint8_t *pci_conf;
 493     uint8_t *wmask;
 494     int i;
 495
 496     isa_bus_new(&d->qdev);
 497
 498     pci_conf = d->config;
 499     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 500     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
 501     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 502     pci_config_set_prog_interface(pci_conf, 0x0);
 503     pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
 504
 505     wmask = d->wmask;
 506     for (i = 0x00; i < 0xff; i++) {
 507        if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
 508            wmask[i] = 0x00;
 509        }
 510     }
 511
 512     qemu_register_reset(vt82c686b_reset, d);
 513
 514     return 0;
 515 }
 516
 517 int vt82c686b_init(PCIBus *bus, int devfn)
 518 {
 519     PCIDevice *d;
 520
 521     d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
 522
 523     return d->devfn;
 524 }
 525
 526 static PCIDeviceInfo via_info = {
 527     .qdev.name    = "VT82C686B",
 528     .qdev.desc    = "ISA bridge",
 529     .qdev.size    = sizeof(VT82C686BState),
 530     .qdev.vmsd    = &vmstate_via,
 531     .qdev.no_user = 1,
 532     .init         = vt82c686b_initfn,
 533     .config_write = vt82c686b_write_config,
 534 };
 535
 536 static void vt82c686b_register(void)
 537 {
 538     pci_qdev_register(&via_info);
 539 }
 540 device_init(vt82c686b_register);