sh4-dis.c

   1 /* Disassemble SH instructions.
   2    Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
   3    Free Software Foundation, Inc.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 2 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  17
  18 #include <stdio.h>
  19 #include "dis-asm.h"
  20
  21 #define DEFINE_TABLE
  22
  23 typedef enum
  24   {
  25     HEX_0,
  26     HEX_1,
  27     HEX_2,
  28     HEX_3,
  29     HEX_4,
  30     HEX_5,
  31     HEX_6,
  32     HEX_7,
  33     HEX_8,
  34     HEX_9,
  35     HEX_A,
  36     HEX_B,
  37     HEX_C,
  38     HEX_D,
  39     HEX_E,
  40     HEX_F,
  41     HEX_XX00,
  42     HEX_00YY,
  43     REG_N,
  44     REG_N_D,     /* nnn0 */
  45     REG_N_B01,   /* nn01 */
  46     REG_M,
  47     SDT_REG_N,
  48     REG_NM,
  49     REG_B,
  50     BRANCH_12,
  51     BRANCH_8,
  52     IMM0_4,
  53     IMM0_4BY2,
  54     IMM0_4BY4,
  55     IMM1_4,
  56     IMM1_4BY2,
  57     IMM1_4BY4,
  58     PCRELIMM_8BY2,
  59     PCRELIMM_8BY4,
  60     IMM0_8,
  61     IMM0_8BY2,
  62     IMM0_8BY4,
  63     IMM1_8,
  64     IMM1_8BY2,
  65     IMM1_8BY4,
  66     PPI,
  67     NOPX,
  68     NOPY,
  69     MOVX,
  70     MOVY,
  71     MOVX_NOPY,
  72     MOVY_NOPX,
  73     PSH,
  74     PMUL,
  75     PPI3,
  76     PPI3NC,
  77     PDC,
  78     PPIC,
  79     REPEAT,
  80     IMM0_3c,    /* xxxx 0iii */
  81     IMM0_3s,    /* xxxx 1iii */
  82     IMM0_3Uc,   /* 0iii xxxx */
  83     IMM0_3Us,   /* 1iii xxxx */
  84     IMM0_20_4,
  85     IMM0_20,    /* follows IMM0_20_4 */
  86     IMM0_20BY8, /* follows IMM0_20_4 */
  87     DISP0_12,
  88     DISP0_12BY2,
  89     DISP0_12BY4,
  90     DISP0_12BY8,
  91     DISP1_12,
  92     DISP1_12BY2,
  93     DISP1_12BY4,
  94     DISP1_12BY8
  95   }
  96 sh_nibble_type;
  97
  98 typedef enum
  99   {
 100     A_END,
 101     A_BDISP12,
 102     A_BDISP8,
 103     A_DEC_M,
 104     A_DEC_N,
 105     A_DISP_GBR,
 106     A_PC,
 107     A_DISP_PC,
 108     A_DISP_PC_ABS,
 109     A_DISP_REG_M,
 110     A_DISP_REG_N,
 111     A_GBR,
 112     A_IMM,
 113     A_INC_M,
 114     A_INC_N,
 115     A_IND_M,
 116     A_IND_N,
 117     A_IND_R0_REG_M,
 118     A_IND_R0_REG_N,
 119     A_MACH,
 120     A_MACL,
 121     A_PR,
 122     A_R0,
 123     A_R0_GBR,
 124     A_REG_M,
 125     A_REG_N,
 126     A_REG_B,
 127     A_SR,
 128     A_VBR,
 129     A_TBR,
 130     A_DISP_TBR,
 131     A_DISP2_TBR,
 132     A_DEC_R15,
 133     A_INC_R15,
 134     A_MOD,
 135     A_RE,
 136     A_RS,
 137     A_DSR,
 138     DSP_REG_M,
 139     DSP_REG_N,
 140     DSP_REG_X,
 141     DSP_REG_Y,
 142     DSP_REG_E,
 143     DSP_REG_F,
 144     DSP_REG_G,
 145     DSP_REG_A_M,
 146     DSP_REG_AX,
 147     DSP_REG_XY,
 148     DSP_REG_AY,
 149     DSP_REG_YX,
 150     AX_INC_N,
 151     AY_INC_N,
 152     AXY_INC_N,
 153     AYX_INC_N,
 154     AX_IND_N,
 155     AY_IND_N,
 156     AXY_IND_N,
 157     AYX_IND_N,
 158     AX_PMOD_N,
 159     AXY_PMOD_N,
 160     AY_PMOD_N,
 161     AYX_PMOD_N,
 162     AS_DEC_N,
 163     AS_INC_N,
 164     AS_IND_N,
 165     AS_PMOD_N,
 166     A_A0,
 167     A_X0,
 168     A_X1,
 169     A_Y0,
 170     A_Y1,
 171     A_SSR,
 172     A_SPC,
 173     A_SGR,
 174     A_DBR,
 175     F_REG_N,
 176     F_REG_M,
 177     D_REG_N,
 178     D_REG_M,
 179     X_REG_N, /* Only used for argument parsing.  */
 180     X_REG_M, /* Only used for argument parsing.  */
 181     DX_REG_N,
 182     DX_REG_M,
 183     V_REG_N,
 184     V_REG_M,
 185     XMTRX_M4,
 186     F_FR0,
 187     FPUL_N,
 188     FPUL_M,
 189     FPSCR_N,
 190     FPSCR_M
 191   }
 192 sh_arg_type;
 193
 194 typedef enum
 195   {
 196     A_A1_NUM =   5,
 197     A_A0_NUM =   7,
 198     A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
 199     A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
 200   }
 201 sh_dsp_reg_nums;
 202
 203 #define arch_sh1_base   0x0001
 204 #define arch_sh2_base   0x0002
 205 #define arch_sh3_base   0x0004
 206 #define arch_sh4_base   0x0008
 207 #define arch_sh4a_base  0x0010
 208 #define arch_sh2a_base  0x0020
 209
 210 /* This is an annotation on instruction types, but we abuse the arch
 211    field in instructions to denote it.  */
 212 #define arch_op32       0x00100000 /* This is a 32-bit opcode.  */
 213
 214 #define arch_sh_no_mmu  0x04000000
 215 #define arch_sh_has_mmu 0x08000000
 216 #define arch_sh_no_co   0x10000000 /* neither FPU nor DSP co-processor */
 217 #define arch_sh_sp_fpu  0x20000000 /* single precision FPU */
 218 #define arch_sh_dp_fpu  0x40000000 /* double precision FPU */
 219 #define arch_sh_has_dsp 0x80000000
 220
 221
 222 #define arch_sh_base_mask 0x0000003f
 223 #define arch_opann_mask   0x00100000
 224 #define arch_sh_mmu_mask  0x0c000000
 225 #define arch_sh_co_mask   0xf0000000
 226
 227
 228 #define arch_sh1        (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
 229 #define arch_sh2        (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
 230 #define arch_sh2a       (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
 231 #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
 232 #define arch_sh2e       (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
 233 #define arch_sh_dsp     (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
 234 #define arch_sh3_nommu  (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
 235 #define arch_sh3        (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
 236 #define arch_sh3e       (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
 237 #define arch_sh3_dsp    (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
 238 #define arch_sh4        (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
 239 #define arch_sh4a       (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
 240 #define arch_sh4al_dsp  (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
 241 #define arch_sh4_nofpu  (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
 242 #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
 243 #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
 244
 245 #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
 246 #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
 247 #define SH_VALID_MMU_ARCH_SET(SET)  (((SET) & arch_sh_mmu_mask) != 0)
 248 #define SH_VALID_CO_ARCH_SET(SET)   (((SET) & arch_sh_co_mask) != 0)
 249 #define SH_VALID_ARCH_SET(SET) \
 250   (SH_VALID_BASE_ARCH_SET (SET) \
 251    && SH_VALID_MMU_ARCH_SET (SET) \
 252    && SH_VALID_CO_ARCH_SET (SET))
 253 #define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
 254   SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))
 255
 256 #define SH_ARCH_SET_HAS_FPU(SET) \
 257   (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
 258 #define SH_ARCH_SET_HAS_DSP(SET) \
 259   (((SET) & arch_sh_has_dsp) != 0)
 260
 261 /* This is returned from the functions below when an error occurs
 262    (in addition to a call to BFD_FAIL). The value should allow
 263    the tools to continue to function in most cases - there may
 264    be some confusion between DSP and FPU etc.  */
 265 #define SH_ARCH_UNKNOWN_ARCH 0xffffffff
 266
 267 /* These are defined in bfd/cpu-sh.c .  */
 268 unsigned int sh_get_arch_from_bfd_mach (unsigned long mach);
 269 unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach);
 270 unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set);
 271 /* bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); */
 272
 273 /* Below are the 'architecture sets'.
 274    They describe the following inheritance graph:
 275
 276                 SH1
 277                  |
 278                 SH2
 279    .------------'|`--------------------.
 280   /              |                      \
 281 SH-DSP          SH3-nommu               SH2E
 282  |               |`--------.             |
 283  |               |          \            |
 284  |              SH3     SH4-nommu-nofpu  |
 285  |               |           |           |
 286  | .------------'|`----------+---------. |
 287  |/                         /           \|
 288  |               | .-------'             |
 289  |               |/                      |
 290 SH3-dsp         SH4-nofpu               SH3E
 291  |               |`--------------------. |
 292  |               |                      \|
 293  |              SH4A-nofpu              SH4
 294  | .------------' `--------------------. |
 295  |/                                     \|
 296 SH4AL-dsp                               SH4A
 297
 298 */
 299
 300 /* Central branches */
 301 #define arch_sh1_up       (arch_sh1 | arch_sh2_up)
 302 #define arch_sh2_up       (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
 303 #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
 304 #define arch_sh3_up       (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
 305 #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
 306 #define arch_sh4_nofp_up  (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
 307 #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
 308
 309 /* Right branch */
 310 #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
 311 #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
 312 #define arch_sh4_up  (arch_sh4 | arch_sh4a_up)
 313 #define arch_sh4a_up (arch_sh4a)
 314
 315 /* Left branch */
 316 #define arch_sh_dsp_up    (arch_sh_dsp | arch_sh3_dsp_up)
 317 #define arch_sh3_dsp_up   (arch_sh3_dsp | arch_sh4al_dsp_up)
 318 #define arch_sh4al_dsp_up (arch_sh4al_dsp)
 319
 320 /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a.  */
 321 #define arch_sh2a_up        (arch_sh2a)
 322 #define arch_sh2a_nofpu_up  (arch_sh2a_nofpu | arch_sh2a_up)
 323
 324
 325 typedef struct
 326 {
 327   const char *name;
 328   sh_arg_type arg[4];
 329   sh_nibble_type nibbles[9];
 330   unsigned int arch;
 331 } sh_opcode_info;
 332
 333 #ifdef DEFINE_TABLE
 334
 335 const sh_opcode_info sh_table[] =
 336   {
 337 /* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
 338
 339 /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
 340
 341 /* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up},
 342
 343 /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
 344
 345 /* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
 346
 347 /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
 348
 349 /* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
 350
 351 /* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
 352
 353 /* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up},
 354
 355 /* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up},
 356
 357 /* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up},
 358
 359 /* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
 360
 361 /* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
 362
 363 /* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
 364
 365 /* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
 366
 367 /* 0000000010001000 clrdmxy             */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
 368
 369 /* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
 370
 371 /* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
 372
 373 /* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
 374
 375 /* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
 376
 377 /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
 378
 379 /* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up},
 380
 381 /* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up},
 382
 383 /* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up},
 384
 385 /* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up},
 386
 387 /* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up},
 388
 389 /* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up},
 390
 391 /* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up},
 392
 393 /* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up},
 394
 395 /* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up},
 396
 397 /* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up},
 398
 399 /* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up},
 400
 401 /* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up},
 402
 403 /* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up},
 404
 405 /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
 406
 407 /* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
 408
 409 /* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
 410
 411 /* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
 412
 413 /* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up},
 414
 415 /* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
 416
 417 /* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 418
 419 /* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
 420
 421 /* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
 422
 423 /* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
 424
 425 /* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},
 426
 427 /* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},
 428
 429 /* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},
 430
 431 /* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},
 432
 433 /* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 434
 435 /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},
 436
 437 /* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up},
 438
 439 /* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up},
 440
 441 /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
 442
 443 /* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
 444
 445 /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
 446
 447 /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
 448
 449 /* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},
 450
 451 /* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},
 452
 453 /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},
 454
 455 /* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
 456
 457 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
 458
 459 /* 0100mmmm00110100 ldrc <REG_M>        */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
 460 /* 10001010i8*1.... ldrc #<imm>         */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
 461
 462 /* 10001110i8p2.... ldre @(<disp>,PC)   */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
 463
 464 /* 10001100i8p2.... ldrs @(<disp>,PC)   */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
 465
 466 /* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
 467
 468 /* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up},
 469
 470 /* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up},
 471
 472 /* 0100nnnn01101010 lds <REG_N>,DSR     */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
 473
 474 /* 0100nnnn01111010 lds <REG_N>,A0      */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
 475
 476 /* 0100nnnn10001010 lds <REG_N>,X0      */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
 477
 478 /* 0100nnnn10011010 lds <REG_N>,X1      */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
 479
 480 /* 0100nnnn10101010 lds <REG_N>,Y0      */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
 481
 482 /* 0100nnnn10111010 lds <REG_N>,Y1      */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
 483
 484 /* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
 485
 486 /* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
 487
 488 /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
 489
 490 /* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up},
 491
 492 /* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up},
 493
 494 /* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},
 495
 496 /* 0100nnnn01110110 lds.l @<REG_N>+,A0  */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},
 497
 498 /* 0100nnnn10000110 lds.l @<REG_N>+,X0  */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},
 499
 500 /* 0100nnnn10010110 lds.l @<REG_N>+,X1  */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},
 501
 502 /* 0100nnnn10100110 lds.l @<REG_N>+,Y0  */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},
 503
 504 /* 0100nnnn10110110 lds.l @<REG_N>+,Y1  */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
 505
 506 /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
 507
 508 /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
 509
 510 /* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
 511
 512 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
 513
 514 /* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
 515
 516 /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
 517
 518 /* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up},
 519
 520 /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up},
 521
 522 /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
 523
 524 /* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
 525
 526 /* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
 527
 528 /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
 529
 530 /* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up},
 531
 532 /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
 533
 534 /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
 535
 536 /* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
 537
 538 /* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},
 539 /* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},
 540 /* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */
 541 {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
 542 /* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */
 543 {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
 544 /* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
 545
 546 /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
 547
 548 /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up},
 549
 550 /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
 551
 552 /* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
 553
 554 /* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
 555
 556 /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
 557
 558 /* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up},
 559
 560 /* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up},
 561
 562 /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
 563
 564 /* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
 565
 566 /* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},
 567 /* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up},
 568 /* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */
 569 {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
 570 /* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */
 571 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
 572 /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
 573
 574 /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up},
 575
 576 /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
 577
 578 /* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
 579
 580 /* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
 581
 582 /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
 583
 584 /* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up},
 585
 586 /* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up},
 587
 588 /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
 589
 590 /* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
 591
 592 /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
 593
 594 /* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up},
 595 /* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up},
 596 /* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */
 597 {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
 598 /* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */
 599 {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
 600 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
 601 /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
 602
 603 /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
 604 /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
 605
 606 /* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
 607
 608 /* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
 609 /* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
 610
 611 /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
 612 /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
 613
 614 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up},
 615
 616 /* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
 617 /* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
 618
 619 /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up},
 620
 621 /* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up},
 622
 623 /* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
 624
 625 /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
 626 /* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
 627
 628 /* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
 629
 630 /* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
 631
 632
 633 /* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
 634
 635 /* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
 636
 637 /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
 638
 639 /* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
 640
 641 /* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
 642
 643 /* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
 644
 645 /* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up},
 646
 647 /* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up},
 648
 649 /* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up},
 650
 651 /* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up},
 652
 653 /* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
 654
 655 /* 0000000010011000 setdmx              */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
 656 /* 0000000011001000 setdmy              */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
 657
 658 /* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
 659 /* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
 660
 661 /* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
 662
 663 /* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
 664
 665 /* repeat start end <REG_N>             */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
 666
 667 /* repeat start end #<imm>              */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
 668
 669 /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
 670
 671 /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
 672
 673 /* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
 674
 675 /* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up},
 676
 677 /* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up},
 678
 679 /* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up},
 680
 681 /* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up},
 682
 683 /* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up},
 684
 685 /* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up},
 686
 687 /* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up},
 688
 689 /* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up},
 690
 691 /* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up},
 692
 693 /* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up},
 694
 695 /* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up},
 696
 697 /* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up},
 698
 699 /* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up},
 700
 701 /* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up},
 702
 703 /* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
 704
 705 /* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
 706
 707 /* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up},
 708
 709 /* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up},
 710
 711 /* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 712
 713 /* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 714
 715 /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up},
 716
 717 /* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
 718
 719 /* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up},
 720
 721 /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up},
 722
 723 /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up},
 724
 725 /* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up},
 726
 727 /* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up},
 728
 729 /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up},
 730
 731 /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up},
 732
 733 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
 734
 735 /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
 736
 737 /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
 738
 739 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up},
 740
 741 /* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up},
 742
 743 /* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up},
 744
 745 /* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up},
 746
 747 /* 0000nnnn01101010 sts DSR,<REG_N>     */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
 748
 749 /* 0000nnnn01111010 sts A0,<REG_N>      */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
 750
 751 /* 0000nnnn10001010 sts X0,<REG_N>      */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
 752
 753 /* 0000nnnn10011010 sts X1,<REG_N>      */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
 754
 755 /* 0000nnnn10101010 sts Y0,<REG_N>      */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
 756
 757 /* 0000nnnn10111010 sts Y1,<REG_N>      */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
 758
 759 /* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
 760
 761 /* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
 762
 763 /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
 764
 765 /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up},
 766
 767 /* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up},
 768
 769 /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
 770
 771 /* 0100nnnn01110110 sts.l A0,@-<REG_N>  */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
 772
 773 /* 0100nnnn10000110 sts.l X0,@-<REG_N>  */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up},
 774
 775 /* 0100nnnn10010110 sts.l X1,@-<REG_N>  */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up},
 776
 777 /* 0100nnnn10100110 sts.l Y0,@-<REG_N>  */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up},
 778
 779 /* 0100nnnn10110110 sts.l Y1,@-<REG_N>  */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
 780
 781 /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
 782
 783 /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
 784
 785 /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
 786
 787 /* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up},
 788
 789 /* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up},
 790
 791 /* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up},
 792
 793 /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
 794
 795 /* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
 796
 797 /* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
 798
 799 /* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
 800
 801 /* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
 802
 803 /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
 804
 805 /* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
 806
 807 /* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
 808
 809 /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
 810
 811 /* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
 812
 813 /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
 814
 815 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up},
 816
 817 /* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up},
 818
 819 /* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up},
 820
 821 /* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up},
 822
 823 /* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up},
 824
 825 /* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up},
 826
 827 /* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up},
 828
 829 /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
 830
 831 /* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
 832
 833 /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
 834
 835 /* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
 836
 837 /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
 838
 839 /* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
 840
 841 /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
 842
 843 /* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
 844
 845 /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
 846
 847 /* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
 848
 849 /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
 850
 851 /* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
 852
 853 /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
 854
 855 /* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
 856
 857 /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
 858
 859 /* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
 860
 861 /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
 862 /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
 863 /* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
 864 /* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
 865 /* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
 866 /* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
 867 /* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
 868 /* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
 869
 870 /* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
 871 /* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
 872 /* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
 873 /* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
 874 /* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
 875 /* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
 876
 877 /* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
 878 /* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
 879 /* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
 880 /* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
 881 /* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
 882 /* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
 883
 884 /* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
 885 /* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
 886 /* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
 887 /* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
 888 /* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
 889 /* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
 890
 891 /* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
 892 /* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
 893 /* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
 894 /* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
 895 /* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
 896 /* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
 897
 898 /* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
 899 /* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
 900 /* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
 901 /* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
 902 /* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
 903 /* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
 904
 905 /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
 906 /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 907 {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
 908 /* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 909 {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
 910 /* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */
 911 {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
 912 /* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 913 {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
 914 /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 915 {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
 916 /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
 917 {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
 918 /* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
 919 {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
 920 /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
 921 {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
 922 /* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
 923 {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
 924 /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
 925 {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
 926 /* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
 927 {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
 928 /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
 929 {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
 930 /* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
 931 {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
 932
 933 {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
 934 {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
 935
 936 /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 937 {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
 938 /* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
 939 /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 940 {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
 941 /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
 942 /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 943 {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
 944 /* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
 945 {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
 946 /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 947 {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
 948 /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 949 {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
 950 /* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 951 {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
 952 /* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 953 {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
 954 /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
 955 {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
 956 /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
 957 {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
 958 /* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
 959 {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
 960 /* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
 961 {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
 962 /* 10001101xxyynnnn pclr <DSP_REG_N> */
 963 {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
 964 /* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
 965 {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
 966 /* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
 967 {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
 968 /* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */
 969 {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
 970 /* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */
 971 {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
 972 /* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
 973 {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
 974 /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
 975 {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
 976 /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
 977 {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
 978 /* 11011101xxyynnnn psts MACL,<DSP_REG_N> */
 979 {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
 980 /* 11101101xxyynnnn plds <DSP_REG_N>,MACH */
 981 {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
 982 /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
 983 {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
 984 /* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
 985 {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
 986 /* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
 987 {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
 988
 989 /* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
 990 /* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
 991
 992 /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
 993 /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
 994
 995 /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
 996 /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
 997
 998 /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
 999 /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
1000
1001 /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
1002
1003 /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
1004
1005 /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
1006 /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
1007
1008 /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
1009
1010 /* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
1011
1012 /* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
1013
1014 /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
1015
1016 /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
1017 /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
1018
1019 /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
1020
1021 /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
1022 /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
1023
1024 /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1025 /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1026
1027 /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1028 /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1029
1030 /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1031 /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1032
1033 /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1034 /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1035
1036 /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1037 /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1038
1039 /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1040 /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1041
1042 /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1043
1044 /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1045
1046 /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1047
1048 /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1049
1050 /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1051
1052 /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1053 /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
1054 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1055 /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
1056 {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1057
1058 /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1059
1060 /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1061
1062 /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1063
1064 /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1065
1066 /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1067
1068 /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1069 /* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */
1070 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1071 /* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),F_REG_N */
1072 {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
1073
1074 /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
1075 /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
1076
1077 /* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
1078 /* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
1079
1080 /* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
1081
1082 /* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
1083
1084 /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
1085
1086 /* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
1087
1088 /* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
1089 /* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
1090
1091 /* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
1092
1093 /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
1094
1095 /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
1096 /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
1097
1098 /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
1099 /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
1100
1101 /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
1102
1103   /* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1104   /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */
1105 {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1106   /* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1107   /* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */
1108 {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1109   /* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1110   /* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */
1111 {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1112   /* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1113   /* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */
1114 {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1115   /* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up},
1116   /* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up},
1117   /* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up},
1118   /* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up},
1119   /* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up},
1120   /* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up},
1121   /* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up},
1122   /* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up},
1123   /* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up},
1124   /* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up},
1125   /* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up},
1126   /* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up},
1127   /* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up},
1128   /* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up},
1129   /* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up},
1130   /* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up},
1131   /* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up},
1132   /* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up},
1133   /* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up},
1134   /* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up},
1135
1136 /* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */
1137 {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1138 /* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */
1139 {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1140 /* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */
1141 {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1142 /* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */
1143 {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1144 /* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */
1145 {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1146 /* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */
1147 {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1148 /* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */
1149 {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
1150 /* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */
1151 {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
1152 /* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */
1153 {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
1154 /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
1155 {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
1156
1157 { 0, {0}, {0}, 0 }
1158 };
1159
1160 #endif
1161
1162 #ifdef ARCH_all
1163 #define INCLUDE_SHMEDIA
1164 #endif
1165
1166 static void print_movxy
1167   PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
1168 static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
1169 static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
1170 static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
1171
1172 static void
1173 print_movxy (op, rn, rm, fprintf_fn, stream)
1174      const sh_opcode_info *op;
1175      int rn, rm;
1176      fprintf_ftype fprintf_fn;
1177      void *stream;
1178 {
1179   int n;
1180
1181   fprintf_fn (stream, "%s\t", op->name);
1182   for (n = 0; n < 2; n++)
1183     {
1184       switch (op->arg[n])
1185         {
1186         case A_IND_N:
1187         case AX_IND_N:
1188         case AXY_IND_N:
1189         case AY_IND_N:
1190         case AYX_IND_N:
1191           fprintf_fn (stream, "@r%d", rn);
1192           break;
1193         case A_INC_N:
1194         case AX_INC_N:
1195         case AXY_INC_N:
1196         case AY_INC_N:
1197         case AYX_INC_N:
1198           fprintf_fn (stream, "@r%d+", rn);
1199           break;
1200         case AX_PMOD_N:
1201         case AXY_PMOD_N:
1202           fprintf_fn (stream, "@r%d+r8", rn);
1203           break;
1204         case AY_PMOD_N:
1205         case AYX_PMOD_N:
1206           fprintf_fn (stream, "@r%d+r9", rn);
1207           break;
1208         case DSP_REG_A_M:
1209           fprintf_fn (stream, "a%c", '0' + rm);
1210           break;
1211         case DSP_REG_X:
1212           fprintf_fn (stream, "x%c", '0' + rm);
1213           break;
1214         case DSP_REG_Y:
1215           fprintf_fn (stream, "y%c", '0' + rm);
1216           break;
1217         case DSP_REG_AX:
1218           fprintf_fn (stream, "%c%c",
1219                       (rm & 1) ? 'x' : 'a',
1220                       (rm & 2) ? '1' : '0');
1221           break;
1222         case DSP_REG_XY:
1223           fprintf_fn (stream, "%c%c",
1224                       (rm & 1) ? 'y' : 'x',
1225                       (rm & 2) ? '1' : '0');
1226           break;
1227         case DSP_REG_AY:
1228           fprintf_fn (stream, "%c%c",
1229                       (rm & 2) ? 'y' : 'a',
1230                       (rm & 1) ? '1' : '0');
1231           break;
1232         case DSP_REG_YX:
1233           fprintf_fn (stream, "%c%c",
1234                       (rm & 2) ? 'x' : 'y',
1235                       (rm & 1) ? '1' : '0');
1236           break;
1237         default:
1238           abort ();
1239         }
1240       if (n == 0)
1241         fprintf_fn (stream, ",");
1242     }
1243 }
1244
1245 /* Print a double data transfer insn.  INSN is just the lower three
1246    nibbles of the insn, i.e. field a and the bit that indicates if
1247    a parallel processing insn follows.
1248    Return nonzero if a field b of a parallel processing insns follows.  */
1249
1250 static void
1251 print_insn_ddt (insn, info)
1252      int insn;
1253      struct disassemble_info *info;
1254 {
1255   fprintf_ftype fprintf_fn = info->fprintf_func;
1256   void *stream = info->stream;
1257
1258   /* If this is just a nop, make sure to emit something.  */
1259   if (insn == 0x000)
1260     fprintf_fn (stream, "nopx\tnopy");
1261
1262   /* If a parallel processing insn was printed before,
1263      and we got a non-nop, emit a tab.  */
1264   if ((insn & 0x800) && (insn & 0x3ff))
1265     fprintf_fn (stream, "\t");
1266
1267   /* Check if either the x or y part is invalid.  */
1268   if (((insn & 0xc) == 0 && (insn & 0x2a0))
1269       || ((insn & 3) == 0 && (insn & 0x150)))
1270     if (info->mach != bfd_mach_sh_dsp
1271         && info->mach != bfd_mach_sh3_dsp)
1272       {
1273         static const sh_opcode_info *first_movx, *first_movy;
1274         const sh_opcode_info *op;
1275         int is_movy;
1276
1277         if (! first_movx)
1278           {
1279             for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
1280               first_movx++;
1281             for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
1282               first_movy++;
1283           }
1284
1285         is_movy = ((insn & 3) != 0);
1286
1287         if (is_movy)
1288           op = first_movy;
1289         else
1290           op = first_movx;
1291
1292         while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
1293                || op->nibbles[3] != (unsigned) (insn & 0xf))
1294           op++;
1295
1296         print_movxy (op,
1297                      (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
1298                       + 2 * is_movy
1299                       + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
1300                      (insn >> 6) & 3,
1301                      fprintf_fn, stream);
1302       }
1303     else
1304       fprintf_fn (stream, ".word 0x%x", insn);
1305   else
1306     {
1307       static const sh_opcode_info *first_movx, *first_movy;
1308       const sh_opcode_info *opx, *opy;
1309       unsigned int insn_x, insn_y;
1310
1311       if (! first_movx)
1312         {
1313           for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
1314             first_movx++;
1315           for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
1316             first_movy++;
1317         }
1318       insn_x = (insn >> 2) & 0xb;
1319       if (insn_x)
1320         {
1321           for (opx = first_movx; opx->nibbles[2] != insn_x;)
1322             opx++;
1323           print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
1324                        fprintf_fn, stream);
1325         }
1326       insn_y = (insn & 3) | ((insn >> 1) & 8);
1327       if (insn_y)
1328         {
1329           if (insn_x)
1330             fprintf_fn (stream, "\t");
1331           for (opy = first_movy; opy->nibbles[2] != insn_y;)
1332             opy++;
1333           print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
1334                        fprintf_fn, stream);
1335         }
1336     }
1337 }
1338
1339 static void
1340 print_dsp_reg (rm, fprintf_fn, stream)
1341      int rm;
1342      fprintf_ftype fprintf_fn;
1343      void *stream;
1344 {
1345   switch (rm)
1346     {
1347     case A_A1_NUM:
1348       fprintf_fn (stream, "a1");
1349       break;
1350     case A_A0_NUM:
1351       fprintf_fn (stream, "a0");
1352       break;
1353     case A_X0_NUM:
1354       fprintf_fn (stream, "x0");
1355       break;
1356     case A_X1_NUM:
1357       fprintf_fn (stream, "x1");
1358       break;
1359     case A_Y0_NUM:
1360       fprintf_fn (stream, "y0");
1361       break;
1362     case A_Y1_NUM:
1363       fprintf_fn (stream, "y1");
1364       break;
1365     case A_M0_NUM:
1366       fprintf_fn (stream, "m0");
1367       break;
1368     case A_A1G_NUM:
1369       fprintf_fn (stream, "a1g");
1370       break;
1371     case A_M1_NUM:
1372       fprintf_fn (stream, "m1");
1373       break;
1374     case A_A0G_NUM:
1375       fprintf_fn (stream, "a0g");
1376       break;
1377     default:
1378       fprintf_fn (stream, "0x%x", rm);
1379       break;
1380     }
1381 }
1382
1383 static void
1384 print_insn_ppi (field_b, info)
1385      int field_b;
1386      struct disassemble_info *info;
1387 {
1388   static const char *sx_tab[] = { "x0", "x1", "a0", "a1" };
1389   static const char *sy_tab[] = { "y0", "y1", "m0", "m1" };
1390   fprintf_ftype fprintf_fn = info->fprintf_func;
1391   void *stream = info->stream;
1392   unsigned int nib1, nib2, nib3;
1393   unsigned int altnib1, nib4;
1394   const char *dc = NULL;
1395   const sh_opcode_info *op;
1396
1397   if ((field_b & 0xe800) == 0)
1398     {
1399       fprintf_fn (stream, "psh%c\t#%d,",
1400                   field_b & 0x1000 ? 'a' : 'l',
1401                   (field_b >> 4) & 127);
1402       print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1403       return;
1404     }
1405   if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
1406     {
1407       static const char *du_tab[] = { "x0", "y0", "a0", "a1" };
1408       static const char *se_tab[] = { "x0", "x1", "y0", "a1" };
1409       static const char *sf_tab[] = { "y0", "y1", "x0", "a1" };
1410       static const char *sg_tab[] = { "m0", "m1", "a0", "a1" };
1411
1412       if (field_b & 0x2000)
1413         {
1414           fprintf_fn (stream, "p%s %s,%s,%s\t",
1415                       (field_b & 0x1000) ? "add" : "sub",
1416                       sx_tab[(field_b >> 6) & 3],
1417                       sy_tab[(field_b >> 4) & 3],
1418                       du_tab[(field_b >> 0) & 3]);
1419         }
1420       else if ((field_b & 0xf0) == 0x10
1421                && info->mach != bfd_mach_sh_dsp
1422                && info->mach != bfd_mach_sh3_dsp)
1423         {
1424           fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
1425         }
1426       else if ((field_b & 0xf3) != 0)
1427         {
1428           fprintf_fn (stream, ".word 0x%x\t", field_b);
1429         }
1430       fprintf_fn (stream, "pmuls%c%s,%s,%s",
1431                   field_b & 0x2000 ? ' ' : '\t',
1432                   se_tab[(field_b >> 10) & 3],
1433                   sf_tab[(field_b >>  8) & 3],
1434                   sg_tab[(field_b >>  2) & 3]);
1435       return;
1436     }
1437
1438   nib1 = PPIC;
1439   nib2 = field_b >> 12 & 0xf;
1440   nib3 = field_b >> 8 & 0xf;
1441   nib4 = field_b >> 4 & 0xf;
1442   switch (nib3 & 0x3)
1443     {
1444     case 0:
1445       dc = "";
1446       nib1 = PPI3;
1447       break;
1448     case 1:
1449       dc = "";
1450       break;
1451     case 2:
1452       dc = "dct ";
1453       nib3 -= 1;
1454       break;
1455     case 3:
1456       dc = "dcf ";
1457       nib3 -= 2;
1458       break;
1459     }
1460   if (nib1 == PPI3)
1461     altnib1 = PPI3NC;
1462   else
1463     altnib1 = nib1;
1464   for (op = sh_table; op->name; op++)
1465     {
1466       if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
1467           && op->nibbles[2] == nib2
1468           && op->nibbles[3] == nib3)
1469         {
1470           int n;
1471
1472           switch (op->nibbles[4])
1473             {
1474             case HEX_0:
1475               break;
1476             case HEX_XX00:
1477               if ((nib4 & 3) != 0)
1478                 continue;
1479               break;
1480             case HEX_1:
1481               if ((nib4 & 3) != 1)
1482                 continue;
1483               break;
1484             case HEX_00YY:
1485               if ((nib4 & 0xc) != 0)
1486                 continue;
1487               break;
1488             case HEX_4:
1489               if ((nib4 & 0xc) != 4)
1490                 continue;
1491               break;
1492             default:
1493               abort ();
1494             }
1495           fprintf_fn (stream, "%s%s\t", dc, op->name);
1496           for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1497             {
1498               if (n && op->arg[1] != A_END)
1499                 fprintf_fn (stream, ",");
1500               switch (op->arg[n])
1501                 {
1502                 case DSP_REG_N:
1503                   print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1504                   break;
1505                 case DSP_REG_X:
1506                   fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
1507                   break;
1508                 case DSP_REG_Y:
1509                   fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
1510                   break;
1511                 case A_MACH:
1512                   fprintf_fn (stream, "mach");
1513                   break;
1514                 case A_MACL:
1515                   fprintf_fn (stream, "macl");
1516                   break;
1517                 default:
1518                   abort ();
1519                 }
1520             }
1521           return;
1522         }
1523     }
1524   /* Not found.  */
1525   fprintf_fn (stream, ".word 0x%x", field_b);
1526 }
1527
1528 /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
1529    (ie. the upper nibble is missing).  */
1530 int
1531 print_insn_sh (memaddr, info)
1532      bfd_vma memaddr;
1533      struct disassemble_info *info;
1534 {
1535   fprintf_ftype fprintf_fn = info->fprintf_func;
1536   void *stream = info->stream;
1537   unsigned char insn[4];
1538   unsigned char nibs[8];
1539   int status;
1540   bfd_vma relmask = ~(bfd_vma) 0;
1541   const sh_opcode_info *op;
1542   unsigned int target_arch;
1543   int allow_op32;
1544
1545   switch (info->mach)
1546     {
1547     case bfd_mach_sh:
1548       target_arch = arch_sh1;
1549       break;
1550     case bfd_mach_sh4:
1551       target_arch = arch_sh4;
1552       break;
1553     case bfd_mach_sh5:
1554 #ifdef INCLUDE_SHMEDIA
1555       status = print_insn_sh64 (memaddr, info);
1556       if (status != -2)
1557         return status;
1558 #endif
1559       /* When we get here for sh64, it's because we want to disassemble
1560          SHcompact, i.e. arch_sh4.  */
1561       target_arch = arch_sh4;
1562       break;
1563     default:
1564       fprintf (stderr, "sh architecture not supported\n");
1565       return -1;
1566     }
1567
1568   status = info->read_memory_func (memaddr, insn, 2, info);
1569
1570   if (status != 0)
1571     {
1572       info->memory_error_func (status, memaddr, info);
1573       return -1;
1574     }
1575
1576   if (info->endian == BFD_ENDIAN_LITTLE)
1577     {
1578       nibs[0] = (insn[1] >> 4) & 0xf;
1579       nibs[1] = insn[1] & 0xf;
1580
1581       nibs[2] = (insn[0] >> 4) & 0xf;
1582       nibs[3] = insn[0] & 0xf;
1583     }
1584   else
1585     {
1586       nibs[0] = (insn[0] >> 4) & 0xf;
1587       nibs[1] = insn[0] & 0xf;
1588
1589       nibs[2] = (insn[1] >> 4) & 0xf;
1590       nibs[3] = insn[1] & 0xf;
1591     }
1592   status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
1593   if (status != 0)
1594     allow_op32 = 0;
1595   else
1596     {
1597       allow_op32 = 1;
1598
1599       if (info->endian == BFD_ENDIAN_LITTLE)
1600         {
1601           nibs[4] = (insn[3] >> 4) & 0xf;
1602           nibs[5] = insn[3] & 0xf;
1603
1604           nibs[6] = (insn[2] >> 4) & 0xf;
1605           nibs[7] = insn[2] & 0xf;
1606         }
1607       else
1608         {
1609           nibs[4] = (insn[2] >> 4) & 0xf;
1610           nibs[5] = insn[2] & 0xf;
1611
1612           nibs[6] = (insn[3] >> 4) & 0xf;
1613           nibs[7] = insn[3] & 0xf;
1614         }
1615     }
1616
1617   if (nibs[0] == 0xf && (nibs[1] & 4) == 0
1618       && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
1619     {
1620       if (nibs[1] & 8)
1621         {
1622           int field_b;
1623
1624           status = info->read_memory_func (memaddr + 2, insn, 2, info);
1625
1626           if (status != 0)
1627             {
1628               info->memory_error_func (status, memaddr + 2, info);
1629               return -1;
1630             }
1631
1632           if (info->endian == BFD_ENDIAN_LITTLE)
1633             field_b = insn[1] << 8 | insn[0];
1634           else
1635             field_b = insn[0] << 8 | insn[1];
1636
1637           print_insn_ppi (field_b, info);
1638           print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1639           return 4;
1640         }
1641       print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1642       return 2;
1643     }
1644   for (op = sh_table; op->name; op++)
1645     {
1646       int n;
1647       int imm = 0;
1648       int rn = 0;
1649       int rm = 0;
1650       int rb = 0;
1651       int disp_pc;
1652       bfd_vma disp_pc_addr = 0;
1653       int disp = 0;
1654       int has_disp = 0;
1655       int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
1656
1657       if (!allow_op32
1658           && SH_MERGE_ARCH_SET (op->arch, arch_op32))
1659         goto fail;
1660
1661       if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
1662         goto fail;
1663       for (n = 0; n < max_n; n++)
1664         {
1665           int i = op->nibbles[n];
1666
1667           if (i < 16)
1668             {
1669               if (nibs[n] == i)
1670                 continue;
1671               goto fail;
1672             }
1673           switch (i)
1674             {
1675             case BRANCH_8:
1676               imm = (nibs[2] << 4) | (nibs[3]);
1677               if (imm & 0x80)
1678                 imm |= ~0xff;
1679               imm = ((char) imm) * 2 + 4;
1680               goto ok;
1681             case BRANCH_12:
1682               imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
1683               if (imm & 0x800)
1684                 imm |= ~0xfff;
1685               imm = imm * 2 + 4;
1686               goto ok;
1687             case IMM0_3c:
1688               if (nibs[3] & 0x8)
1689                 goto fail;
1690               imm = nibs[3] & 0x7;
1691               break;
1692             case IMM0_3s:
1693               if (!(nibs[3] & 0x8))
1694                 goto fail;
1695               imm = nibs[3] & 0x7;
1696               break;
1697             case IMM0_3Uc:
1698               if (nibs[2] & 0x8)
1699                 goto fail;
1700               imm = nibs[2] & 0x7;
1701               break;
1702             case IMM0_3Us:
1703               if (!(nibs[2] & 0x8))
1704                 goto fail;
1705               imm = nibs[2] & 0x7;
1706               break;
1707             case DISP0_12:
1708             case DISP1_12:
1709               disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
1710               has_disp = 1;
1711               goto ok;
1712             case DISP0_12BY2:
1713             case DISP1_12BY2:
1714               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
1715               relmask = ~(bfd_vma) 1;
1716               has_disp = 1;
1717               goto ok;
1718             case DISP0_12BY4:
1719             case DISP1_12BY4:
1720               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
1721               relmask = ~(bfd_vma) 3;
1722               has_disp = 1;
1723               goto ok;
1724             case DISP0_12BY8:
1725             case DISP1_12BY8:
1726               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
1727               relmask = ~(bfd_vma) 7;
1728               has_disp = 1;
1729               goto ok;
1730             case IMM0_20_4:
1731               break;
1732             case IMM0_20:
1733               imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1734                      | (nibs[6] << 4) | nibs[7]);
1735               if (imm & 0x80000)
1736                 imm -= 0x100000;
1737               goto ok;
1738             case IMM0_20BY8:
1739               imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1740                      | (nibs[6] << 4) | nibs[7]);
1741               imm <<= 8;
1742               if (imm & 0x8000000)
1743                 imm -= 0x10000000;
1744               goto ok;
1745             case IMM0_4:
1746             case IMM1_4:
1747               imm = nibs[3];
1748               goto ok;
1749             case IMM0_4BY2:
1750             case IMM1_4BY2:
1751               imm = nibs[3] << 1;
1752               goto ok;
1753             case IMM0_4BY4:
1754             case IMM1_4BY4:
1755               imm = nibs[3] << 2;
1756               goto ok;
1757             case IMM0_8:
1758             case IMM1_8:
1759               imm = (nibs[2] << 4) | nibs[3];
1760               disp = imm;
1761               has_disp = 1;
1762               if (imm & 0x80)
1763                 imm -= 0x100;
1764               goto ok;
1765             case PCRELIMM_8BY2:
1766               imm = ((nibs[2] << 4) | nibs[3]) << 1;
1767               relmask = ~(bfd_vma) 1;
1768               goto ok;
1769             case PCRELIMM_8BY4:
1770               imm = ((nibs[2] << 4) | nibs[3]) << 2;
1771               relmask = ~(bfd_vma) 3;
1772               goto ok;
1773             case IMM0_8BY2:
1774             case IMM1_8BY2:
1775               imm = ((nibs[2] << 4) | nibs[3]) << 1;
1776               goto ok;
1777             case IMM0_8BY4:
1778             case IMM1_8BY4:
1779               imm = ((nibs[2] << 4) | nibs[3]) << 2;
1780               goto ok;
1781             case REG_N_D:
1782               if ((nibs[n] & 1) != 0)
1783                 goto fail;
1784               /* fall through */
1785             case REG_N:
1786               rn = nibs[n];
1787               break;
1788             case REG_M:
1789               rm = nibs[n];
1790               break;
1791             case REG_N_B01:
1792               if ((nibs[n] & 0x3) != 1 /* binary 01 */)
1793                 goto fail;
1794               rn = (nibs[n] & 0xc) >> 2;
1795               break;
1796             case REG_NM:
1797               rn = (nibs[n] & 0xc) >> 2;
1798               rm = (nibs[n] & 0x3);
1799               break;
1800             case REG_B:
1801               rb = nibs[n] & 0x07;
1802               break;
1803             case SDT_REG_N:
1804               /* sh-dsp: single data transfer.  */
1805               rn = nibs[n];
1806               if ((rn & 0xc) != 4)
1807                 goto fail;
1808               rn = rn & 0x3;
1809               rn |= (!(rn & 2)) << 2;
1810               break;
1811             case PPI:
1812             case REPEAT:
1813               goto fail;
1814             default:
1815               abort ();
1816             }
1817         }
1818
1819     ok:
1820       /* sh2a has D_REG but not X_REG.  We don't know the pattern
1821          doesn't match unless we check the output args to see if they
1822          make sense.  */
1823       if (target_arch == arch_sh2a
1824           && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
1825               || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
1826         goto fail;
1827
1828       fprintf_fn (stream, "%s\t", op->name);
1829       disp_pc = 0;
1830       for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1831         {
1832           if (n && op->arg[1] != A_END)
1833             fprintf_fn (stream, ",");
1834           switch (op->arg[n])
1835             {
1836             case A_IMM:
1837               fprintf_fn (stream, "#%d", imm);
1838               break;
1839             case A_R0:
1840               fprintf_fn (stream, "r0");
1841               break;
1842             case A_REG_N:
1843               fprintf_fn (stream, "r%d", rn);
1844               break;
1845             case A_INC_N:
1846             case AS_INC_N:
1847               fprintf_fn (stream, "@r%d+", rn);
1848               break;
1849             case A_DEC_N:
1850             case AS_DEC_N:
1851               fprintf_fn (stream, "@-r%d", rn);
1852               break;
1853             case A_IND_N:
1854             case AS_IND_N:
1855               fprintf_fn (stream, "@r%d", rn);
1856               break;
1857             case A_DISP_REG_N:
1858               fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
1859               break;
1860             case AS_PMOD_N:
1861               fprintf_fn (stream, "@r%d+r8", rn);
1862               break;
1863             case A_REG_M:
1864               fprintf_fn (stream, "r%d", rm);
1865               break;
1866             case A_INC_M:
1867               fprintf_fn (stream, "@r%d+", rm);
1868               break;
1869             case A_DEC_M:
1870               fprintf_fn (stream, "@-r%d", rm);
1871               break;
1872             case A_IND_M:
1873               fprintf_fn (stream, "@r%d", rm);
1874               break;
1875             case A_DISP_REG_M:
1876               fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
1877               break;
1878             case A_REG_B:
1879               fprintf_fn (stream, "r%d_bank", rb);
1880               break;
1881             case A_DISP_PC:
1882               disp_pc = 1;
1883               disp_pc_addr = imm + 4 + (memaddr & relmask);
1884               (*info->print_address_func) (disp_pc_addr, info);
1885               break;
1886             case A_IND_R0_REG_N:
1887               fprintf_fn (stream, "@(r0,r%d)", rn);
1888               break;
1889             case A_IND_R0_REG_M:
1890               fprintf_fn (stream, "@(r0,r%d)", rm);
1891               break;
1892             case A_DISP_GBR:
1893               fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
1894               break;
1895             case A_TBR:
1896               fprintf_fn (stream, "tbr");
1897               break;
1898             case A_DISP2_TBR:
1899               fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
1900               break;
1901             case A_INC_R15:
1902               fprintf_fn (stream, "@r15+");
1903               break;
1904             case A_DEC_R15:
1905               fprintf_fn (stream, "@-r15");
1906               break;
1907             case A_R0_GBR:
1908               fprintf_fn (stream, "@(r0,gbr)");
1909               break;
1910             case A_BDISP12:
1911             case A_BDISP8:
1912                 {
1913                     bfd_vma addr;
1914                     addr = imm + memaddr;
1915                     (*info->print_address_func) (addr, info);
1916                 }
1917               break;
1918             case A_SR:
1919               fprintf_fn (stream, "sr");
1920               break;
1921             case A_GBR:
1922               fprintf_fn (stream, "gbr");
1923               break;
1924             case A_VBR:
1925               fprintf_fn (stream, "vbr");
1926               break;
1927             case A_DSR:
1928               fprintf_fn (stream, "dsr");
1929               break;
1930             case A_MOD:
1931               fprintf_fn (stream, "mod");
1932               break;
1933             case A_RE:
1934               fprintf_fn (stream, "re");
1935               break;
1936             case A_RS:
1937               fprintf_fn (stream, "rs");
1938               break;
1939             case A_A0:
1940               fprintf_fn (stream, "a0");
1941               break;
1942             case A_X0:
1943               fprintf_fn (stream, "x0");
1944               break;
1945             case A_X1:
1946               fprintf_fn (stream, "x1");
1947               break;
1948             case A_Y0:
1949               fprintf_fn (stream, "y0");
1950               break;
1951             case A_Y1:
1952               fprintf_fn (stream, "y1");
1953               break;
1954             case DSP_REG_M:
1955               print_dsp_reg (rm, fprintf_fn, stream);
1956               break;
1957             case A_SSR:
1958               fprintf_fn (stream, "ssr");
1959               break;
1960             case A_SPC:
1961               fprintf_fn (stream, "spc");
1962               break;
1963             case A_MACH:
1964               fprintf_fn (stream, "mach");
1965               break;
1966             case A_MACL:
1967               fprintf_fn (stream, "macl");
1968               break;
1969             case A_PR:
1970               fprintf_fn (stream, "pr");
1971               break;
1972             case A_SGR:
1973               fprintf_fn (stream, "sgr");
1974               break;
1975             case A_DBR:
1976               fprintf_fn (stream, "dbr");
1977               break;
1978             case F_REG_N:
1979               fprintf_fn (stream, "fr%d", rn);
1980               break;
1981             case F_REG_M:
1982               fprintf_fn (stream, "fr%d", rm);
1983               break;
1984             case DX_REG_N:
1985               if (rn & 1)
1986                 {
1987                   fprintf_fn (stream, "xd%d", rn & ~1);
1988                   break;
1989                 }
1990             case D_REG_N:
1991               fprintf_fn (stream, "dr%d", rn);
1992               break;
1993             case DX_REG_M:
1994               if (rm & 1)
1995                 {
1996                   fprintf_fn (stream, "xd%d", rm & ~1);
1997                   break;
1998                 }
1999             case D_REG_M:
2000               fprintf_fn (stream, "dr%d", rm);
2001               break;
2002             case FPSCR_M:
2003             case FPSCR_N:
2004               fprintf_fn (stream, "fpscr");
2005               break;
2006             case FPUL_M:
2007             case FPUL_N:
2008               fprintf_fn (stream, "fpul");
2009               break;
2010             case F_FR0:
2011               fprintf_fn (stream, "fr0");
2012               break;
2013             case V_REG_N:
2014               fprintf_fn (stream, "fv%d", rn * 4);
2015               break;
2016             case V_REG_M:
2017               fprintf_fn (stream, "fv%d", rm * 4);
2018               break;
2019             case XMTRX_M4:
2020               fprintf_fn (stream, "xmtrx");
2021               break;
2022             default:
2023               abort ();
2024             }
2025         }
2026
2027 #if 0
2028       /* This code prints instructions in delay slots on the same line
2029          as the instruction which needs the delay slots.  This can be
2030          confusing, since other disassembler don't work this way, and
2031          it means that the instructions are not all in a line.  So I
2032          disabled it.  Ian.  */
2033       if (!(info->flags & 1)
2034           && (op->name[0] == 'j'
2035               || (op->name[0] == 'b'
2036                   && (op->name[1] == 'r'
2037                       || op->name[1] == 's'))
2038               || (op->name[0] == 'r' && op->name[1] == 't')
2039               || (op->name[0] == 'b' && op->name[2] == '.')))
2040         {
2041           info->flags |= 1;
2042           fprintf_fn (stream, "\t(slot ");
2043           print_insn_sh (memaddr + 2, info);
2044           info->flags &= ~1;
2045           fprintf_fn (stream, ")");
2046           return 4;
2047         }
2048 #endif
2049
2050       if (disp_pc && strcmp (op->name, "mova") != 0)
2051         {
2052           int size;
2053           bfd_byte bytes[4];
2054
2055           if (relmask == ~(bfd_vma) 1)
2056             size = 2;
2057           else
2058             size = 4;
2059           status = info->read_memory_func (disp_pc_addr, bytes, size, info);
2060           if (status == 0)
2061             {
2062               unsigned int val;
2063
2064               if (size == 2)
2065                 {
2066                   if (info->endian == BFD_ENDIAN_LITTLE)
2067                     val = bfd_getl16 (bytes);
2068                   else
2069                     val = bfd_getb16 (bytes);
2070                 }
2071               else
2072                 {
2073                   if (info->endian == BFD_ENDIAN_LITTLE)
2074                     val = bfd_getl32 (bytes);
2075                   else
2076                     val = bfd_getb32 (bytes);
2077                 }
2078               if ((*info->symbol_at_address_func) (val, info))
2079                 {
2080                   fprintf_fn (stream, "\t! 0x");
2081                   (*info->print_address_func) (val, info);
2082                 }
2083               else
2084                 fprintf_fn (stream, "\t! 0x%x", val);
2085             }
2086         }
2087
2088       return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
2089     fail:
2090       ;
2091
2092     }
2093   fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
2094   return 2;
2095 }