hw/pxa2xx_lcd.c

   1 /*
   2  * Intel XScale PXA255/270 LCDC emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  */
   9
  10 #include "hw.h"
  11 #include "console.h"
  12 #include "pxa.h"
  13 #include "pixel_ops.h"
  14 /* FIXME: For graphic_rotate. Should probably be done in common code.  */
  15 #include "sysemu.h"
  16 #include "framebuffer.h"
  17
  18 struct PXA2xxLCDState {
  19     qemu_irq irq;
  20     int irqlevel;
  21
  22     int invalidated;
  23     DisplayState *ds;
  24     drawfn *line_fn[2];
  25     int dest_width;
  26     int xres, yres;
  27     int pal_for;
  28     int transp;
  29     enum {
  30         pxa_lcdc_2bpp = 1,
  31         pxa_lcdc_4bpp = 2,
  32         pxa_lcdc_8bpp = 3,
  33         pxa_lcdc_16bpp = 4,
  34         pxa_lcdc_18bpp = 5,
  35         pxa_lcdc_18pbpp = 6,
  36         pxa_lcdc_19bpp = 7,
  37         pxa_lcdc_19pbpp = 8,
  38         pxa_lcdc_24bpp = 9,
  39         pxa_lcdc_25bpp = 10,
  40     } bpp;
  41
  42     uint32_t control[6];
  43     uint32_t status[2];
  44     uint32_t ovl1c[2];
  45     uint32_t ovl2c[2];
  46     uint32_t ccr;
  47     uint32_t cmdcr;
  48     uint32_t trgbr;
  49     uint32_t tcr;
  50     uint32_t liidr;
  51     uint8_t bscntr;
  52
  53     struct {
  54         target_phys_addr_t branch;
  55         int up;
  56         uint8_t palette[1024];
  57         uint8_t pbuffer[1024];
  58         void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
  59                         int *miny, int *maxy);
  60
  61         target_phys_addr_t descriptor;
  62         target_phys_addr_t source;
  63         uint32_t id;
  64         uint32_t command;
  65     } dma_ch[7];
  66
  67     qemu_irq vsync_cb;
  68     int orientation;
  69 };
  70
  71 typedef struct __attribute__ ((__packed__)) {
  72     uint32_t fdaddr;
  73     uint32_t fsaddr;
  74     uint32_t fidr;
  75     uint32_t ldcmd;
  76 } PXAFrameDescriptor;
  77
  78 #define LCCR0   0x000   /* LCD Controller Control register 0 */
  79 #define LCCR1   0x004   /* LCD Controller Control register 1 */
  80 #define LCCR2   0x008   /* LCD Controller Control register 2 */
  81 #define LCCR3   0x00c   /* LCD Controller Control register 3 */
  82 #define LCCR4   0x010   /* LCD Controller Control register 4 */
  83 #define LCCR5   0x014   /* LCD Controller Control register 5 */
  84
  85 #define FBR0    0x020   /* DMA Channel 0 Frame Branch register */
  86 #define FBR1    0x024   /* DMA Channel 1 Frame Branch register */
  87 #define FBR2    0x028   /* DMA Channel 2 Frame Branch register */
  88 #define FBR3    0x02c   /* DMA Channel 3 Frame Branch register */
  89 #define FBR4    0x030   /* DMA Channel 4 Frame Branch register */
  90 #define FBR5    0x110   /* DMA Channel 5 Frame Branch register */
  91 #define FBR6    0x114   /* DMA Channel 6 Frame Branch register */
  92
  93 #define LCSR1   0x034   /* LCD Controller Status register 1 */
  94 #define LCSR0   0x038   /* LCD Controller Status register 0 */
  95 #define LIIDR   0x03c   /* LCD Controller Interrupt ID register */
  96
  97 #define TRGBR   0x040   /* TMED RGB Seed register */
  98 #define TCR     0x044   /* TMED Control register */
  99
 100 #define OVL1C1  0x050   /* Overlay 1 Control register 1 */
 101 #define OVL1C2  0x060   /* Overlay 1 Control register 2 */
 102 #define OVL2C1  0x070   /* Overlay 2 Control register 1 */
 103 #define OVL2C2  0x080   /* Overlay 2 Control register 2 */
 104 #define CCR     0x090   /* Cursor Control register */
 105
 106 #define CMDCR   0x100   /* Command Control register */
 107 #define PRSR    0x104   /* Panel Read Status register */
 108
 109 #define PXA_LCDDMA_CHANS        7
 110 #define DMA_FDADR               0x00    /* Frame Descriptor Address register */
 111 #define DMA_FSADR               0x04    /* Frame Source Address register */
 112 #define DMA_FIDR                0x08    /* Frame ID register */
 113 #define DMA_LDCMD               0x0c    /* Command register */
 114
 115 /* LCD Buffer Strength Control register */
 116 #define BSCNTR  0x04000054
 117
 118 /* Bitfield masks */
 119 #define LCCR0_ENB       (1 << 0)
 120 #define LCCR0_CMS       (1 << 1)
 121 #define LCCR0_SDS       (1 << 2)
 122 #define LCCR0_LDM       (1 << 3)
 123 #define LCCR0_SOFM0     (1 << 4)
 124 #define LCCR0_IUM       (1 << 5)
 125 #define LCCR0_EOFM0     (1 << 6)
 126 #define LCCR0_PAS       (1 << 7)
 127 #define LCCR0_DPD       (1 << 9)
 128 #define LCCR0_DIS       (1 << 10)
 129 #define LCCR0_QDM       (1 << 11)
 130 #define LCCR0_PDD       (0xff << 12)
 131 #define LCCR0_BSM0      (1 << 20)
 132 #define LCCR0_OUM       (1 << 21)
 133 #define LCCR0_LCDT      (1 << 22)
 134 #define LCCR0_RDSTM     (1 << 23)
 135 #define LCCR0_CMDIM     (1 << 24)
 136 #define LCCR0_OUC       (1 << 25)
 137 #define LCCR0_LDDALT    (1 << 26)
 138 #define LCCR1_PPL(x)    ((x) & 0x3ff)
 139 #define LCCR2_LPP(x)    ((x) & 0x3ff)
 140 #define LCCR3_API       (15 << 16)
 141 #define LCCR3_BPP(x)    ((((x) >> 24) & 7) | (((x) >> 26) & 8))
 142 #define LCCR3_PDFOR(x)  (((x) >> 30) & 3)
 143 #define LCCR4_K1(x)     (((x) >> 0) & 7)
 144 #define LCCR4_K2(x)     (((x) >> 3) & 7)
 145 #define LCCR4_K3(x)     (((x) >> 6) & 7)
 146 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
 147 #define LCCR5_SOFM(ch)  (1 << (ch - 1))
 148 #define LCCR5_EOFM(ch)  (1 << (ch + 7))
 149 #define LCCR5_BSM(ch)   (1 << (ch + 15))
 150 #define LCCR5_IUM(ch)   (1 << (ch + 23))
 151 #define OVLC1_EN        (1 << 31)
 152 #define CCR_CEN         (1 << 31)
 153 #define FBR_BRA         (1 << 0)
 154 #define FBR_BINT        (1 << 1)
 155 #define FBR_SRCADDR     (0xfffffff << 4)
 156 #define LCSR0_LDD       (1 << 0)
 157 #define LCSR0_SOF0      (1 << 1)
 158 #define LCSR0_BER       (1 << 2)
 159 #define LCSR0_ABC       (1 << 3)
 160 #define LCSR0_IU0       (1 << 4)
 161 #define LCSR0_IU1       (1 << 5)
 162 #define LCSR0_OU        (1 << 6)
 163 #define LCSR0_QD        (1 << 7)
 164 #define LCSR0_EOF0      (1 << 8)
 165 #define LCSR0_BS0       (1 << 9)
 166 #define LCSR0_SINT      (1 << 10)
 167 #define LCSR0_RDST      (1 << 11)
 168 #define LCSR0_CMDINT    (1 << 12)
 169 #define LCSR0_BERCH(x)  (((x) & 7) << 28)
 170 #define LCSR1_SOF(ch)   (1 << (ch - 1))
 171 #define LCSR1_EOF(ch)   (1 << (ch + 7))
 172 #define LCSR1_BS(ch)    (1 << (ch + 15))
 173 #define LCSR1_IU(ch)    (1 << (ch + 23))
 174 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
 175 #define LDCMD_EOFINT    (1 << 21)
 176 #define LDCMD_SOFINT    (1 << 22)
 177 #define LDCMD_PAL       (1 << 26)
 178
 179 /* Route internal interrupt lines to the global IC */
 180 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
 181 {
 182     int level = 0;
 183     level |= (s->status[0] & LCSR0_LDD)    && !(s->control[0] & LCCR0_LDM);
 184     level |= (s->status[0] & LCSR0_SOF0)   && !(s->control[0] & LCCR0_SOFM0);
 185     level |= (s->status[0] & LCSR0_IU0)    && !(s->control[0] & LCCR0_IUM);
 186     level |= (s->status[0] & LCSR0_IU1)    && !(s->control[5] & LCCR5_IUM(1));
 187     level |= (s->status[0] & LCSR0_OU)     && !(s->control[0] & LCCR0_OUM);
 188     level |= (s->status[0] & LCSR0_QD)     && !(s->control[0] & LCCR0_QDM);
 189     level |= (s->status[0] & LCSR0_EOF0)   && !(s->control[0] & LCCR0_EOFM0);
 190     level |= (s->status[0] & LCSR0_BS0)    && !(s->control[0] & LCCR0_BSM0);
 191     level |= (s->status[0] & LCSR0_RDST)   && !(s->control[0] & LCCR0_RDSTM);
 192     level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
 193     level |= (s->status[1] & ~s->control[5]);
 194
 195     qemu_set_irq(s->irq, !!level);
 196     s->irqlevel = level;
 197 }
 198
 199 /* Set Branch Status interrupt high and poke associated registers */
 200 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
 201 {
 202     int unmasked;
 203     if (ch == 0) {
 204         s->status[0] |= LCSR0_BS0;
 205         unmasked = !(s->control[0] & LCCR0_BSM0);
 206     } else {
 207         s->status[1] |= LCSR1_BS(ch);
 208         unmasked = !(s->control[5] & LCCR5_BSM(ch));
 209     }
 210
 211     if (unmasked) {
 212         if (s->irqlevel)
 213             s->status[0] |= LCSR0_SINT;
 214         else
 215             s->liidr = s->dma_ch[ch].id;
 216     }
 217 }
 218
 219 /* Set Start Of Frame Status interrupt high and poke associated registers */
 220 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
 221 {
 222     int unmasked;
 223     if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
 224         return;
 225
 226     if (ch == 0) {
 227         s->status[0] |= LCSR0_SOF0;
 228         unmasked = !(s->control[0] & LCCR0_SOFM0);
 229     } else {
 230         s->status[1] |= LCSR1_SOF(ch);
 231         unmasked = !(s->control[5] & LCCR5_SOFM(ch));
 232     }
 233
 234     if (unmasked) {
 235         if (s->irqlevel)
 236             s->status[0] |= LCSR0_SINT;
 237         else
 238             s->liidr = s->dma_ch[ch].id;
 239     }
 240 }
 241
 242 /* Set End Of Frame Status interrupt high and poke associated registers */
 243 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
 244 {
 245     int unmasked;
 246     if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
 247         return;
 248
 249     if (ch == 0) {
 250         s->status[0] |= LCSR0_EOF0;
 251         unmasked = !(s->control[0] & LCCR0_EOFM0);
 252     } else {
 253         s->status[1] |= LCSR1_EOF(ch);
 254         unmasked = !(s->control[5] & LCCR5_EOFM(ch));
 255     }
 256
 257     if (unmasked) {
 258         if (s->irqlevel)
 259             s->status[0] |= LCSR0_SINT;
 260         else
 261             s->liidr = s->dma_ch[ch].id;
 262     }
 263 }
 264
 265 /* Set Bus Error Status interrupt high and poke associated registers */
 266 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
 267 {
 268     s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
 269     if (s->irqlevel)
 270         s->status[0] |= LCSR0_SINT;
 271     else
 272         s->liidr = s->dma_ch[ch].id;
 273 }
 274
 275 /* Set Read Status interrupt high and poke associated registers */
 276 static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
 277 {
 278     s->status[0] |= LCSR0_RDST;
 279     if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
 280         s->status[0] |= LCSR0_SINT;
 281 }
 282
 283 /* Load new Frame Descriptors from DMA */
 284 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
 285 {
 286     PXAFrameDescriptor desc;
 287     target_phys_addr_t descptr;
 288     int i;
 289
 290     for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
 291         s->dma_ch[i].source = 0;
 292
 293         if (!s->dma_ch[i].up)
 294             continue;
 295
 296         if (s->dma_ch[i].branch & FBR_BRA) {
 297             descptr = s->dma_ch[i].branch & FBR_SRCADDR;
 298             if (s->dma_ch[i].branch & FBR_BINT)
 299                 pxa2xx_dma_bs_set(s, i);
 300             s->dma_ch[i].branch &= ~FBR_BRA;
 301         } else
 302             descptr = s->dma_ch[i].descriptor;
 303
 304         if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
 305                     sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
 306             continue;
 307
 308         cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
 309         s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
 310         s->dma_ch[i].source = tswap32(desc.fsaddr);
 311         s->dma_ch[i].id = tswap32(desc.fidr);
 312         s->dma_ch[i].command = tswap32(desc.ldcmd);
 313     }
 314 }
 315
 316 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
 317 {
 318     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 319     int ch;
 320
 321     switch (offset) {
 322     case LCCR0:
 323         return s->control[0];
 324     case LCCR1:
 325         return s->control[1];
 326     case LCCR2:
 327         return s->control[2];
 328     case LCCR3:
 329         return s->control[3];
 330     case LCCR4:
 331         return s->control[4];
 332     case LCCR5:
 333         return s->control[5];
 334
 335     case OVL1C1:
 336         return s->ovl1c[0];
 337     case OVL1C2:
 338         return s->ovl1c[1];
 339     case OVL2C1:
 340         return s->ovl2c[0];
 341     case OVL2C2:
 342         return s->ovl2c[1];
 343
 344     case CCR:
 345         return s->ccr;
 346
 347     case CMDCR:
 348         return s->cmdcr;
 349
 350     case TRGBR:
 351         return s->trgbr;
 352     case TCR:
 353         return s->tcr;
 354
 355     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 356         ch = (offset - 0x200) >> 4;
 357         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 358             goto fail;
 359
 360         switch (offset & 0xf) {
 361         case DMA_FDADR:
 362             return s->dma_ch[ch].descriptor;
 363         case DMA_FSADR:
 364             return s->dma_ch[ch].source;
 365         case DMA_FIDR:
 366             return s->dma_ch[ch].id;
 367         case DMA_LDCMD:
 368             return s->dma_ch[ch].command;
 369         default:
 370             goto fail;
 371         }
 372
 373     case FBR0:
 374         return s->dma_ch[0].branch;
 375     case FBR1:
 376         return s->dma_ch[1].branch;
 377     case FBR2:
 378         return s->dma_ch[2].branch;
 379     case FBR3:
 380         return s->dma_ch[3].branch;
 381     case FBR4:
 382         return s->dma_ch[4].branch;
 383     case FBR5:
 384         return s->dma_ch[5].branch;
 385     case FBR6:
 386         return s->dma_ch[6].branch;
 387
 388     case BSCNTR:
 389         return s->bscntr;
 390
 391     case PRSR:
 392         return 0;
 393
 394     case LCSR0:
 395         return s->status[0];
 396     case LCSR1:
 397         return s->status[1];
 398     case LIIDR:
 399         return s->liidr;
 400
 401     default:
 402     fail:
 403         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 404     }
 405
 406     return 0;
 407 }
 408
 409 static void pxa2xx_lcdc_write(void *opaque,
 410                 target_phys_addr_t offset, uint32_t value)
 411 {
 412     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 413     int ch;
 414
 415     switch (offset) {
 416     case LCCR0:
 417         /* ACK Quick Disable done */
 418         if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
 419             s->status[0] |= LCSR0_QD;
 420
 421         if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
 422             printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
 423
 424         if ((s->control[3] & LCCR3_API) &&
 425                 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
 426             s->status[0] |= LCSR0_ABC;
 427
 428         s->control[0] = value & 0x07ffffff;
 429         pxa2xx_lcdc_int_update(s);
 430
 431         s->dma_ch[0].up = !!(value & LCCR0_ENB);
 432         s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
 433         break;
 434
 435     case LCCR1:
 436         s->control[1] = value;
 437         break;
 438
 439     case LCCR2:
 440         s->control[2] = value;
 441         break;
 442
 443     case LCCR3:
 444         s->control[3] = value & 0xefffffff;
 445         s->bpp = LCCR3_BPP(value);
 446         break;
 447
 448     case LCCR4:
 449         s->control[4] = value & 0x83ff81ff;
 450         break;
 451
 452     case LCCR5:
 453         s->control[5] = value & 0x3f3f3f3f;
 454         break;
 455
 456     case OVL1C1:
 457         if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
 458             printf("%s: Overlay 1 not supported\n", __FUNCTION__);
 459
 460         s->ovl1c[0] = value & 0x80ffffff;
 461         s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
 462         break;
 463
 464     case OVL1C2:
 465         s->ovl1c[1] = value & 0x000fffff;
 466         break;
 467
 468     case OVL2C1:
 469         if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
 470             printf("%s: Overlay 2 not supported\n", __FUNCTION__);
 471
 472         s->ovl2c[0] = value & 0x80ffffff;
 473         s->dma_ch[2].up = !!(value & OVLC1_EN);
 474         s->dma_ch[3].up = !!(value & OVLC1_EN);
 475         s->dma_ch[4].up = !!(value & OVLC1_EN);
 476         break;
 477
 478     case OVL2C2:
 479         s->ovl2c[1] = value & 0x007fffff;
 480         break;
 481
 482     case CCR:
 483         if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
 484             printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
 485
 486         s->ccr = value & 0x81ffffe7;
 487         s->dma_ch[5].up = !!(value & CCR_CEN);
 488         break;
 489
 490     case CMDCR:
 491         s->cmdcr = value & 0xff;
 492         break;
 493
 494     case TRGBR:
 495         s->trgbr = value & 0x00ffffff;
 496         break;
 497
 498     case TCR:
 499         s->tcr = value & 0x7fff;
 500         break;
 501
 502     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 503         ch = (offset - 0x200) >> 4;
 504         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 505             goto fail;
 506
 507         switch (offset & 0xf) {
 508         case DMA_FDADR:
 509             s->dma_ch[ch].descriptor = value & 0xfffffff0;
 510             break;
 511
 512         default:
 513             goto fail;
 514         }
 515         break;
 516
 517     case FBR0:
 518         s->dma_ch[0].branch = value & 0xfffffff3;
 519         break;
 520     case FBR1:
 521         s->dma_ch[1].branch = value & 0xfffffff3;
 522         break;
 523     case FBR2:
 524         s->dma_ch[2].branch = value & 0xfffffff3;
 525         break;
 526     case FBR3:
 527         s->dma_ch[3].branch = value & 0xfffffff3;
 528         break;
 529     case FBR4:
 530         s->dma_ch[4].branch = value & 0xfffffff3;
 531         break;
 532     case FBR5:
 533         s->dma_ch[5].branch = value & 0xfffffff3;
 534         break;
 535     case FBR6:
 536         s->dma_ch[6].branch = value & 0xfffffff3;
 537         break;
 538
 539     case BSCNTR:
 540         s->bscntr = value & 0xf;
 541         break;
 542
 543     case PRSR:
 544         break;
 545
 546     case LCSR0:
 547         s->status[0] &= ~(value & 0xfff);
 548         if (value & LCSR0_BER)
 549             s->status[0] &= ~LCSR0_BERCH(7);
 550         break;
 551
 552     case LCSR1:
 553         s->status[1] &= ~(value & 0x3e3f3f);
 554         break;
 555
 556     default:
 557     fail:
 558         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 559     }
 560 }
 561
 562 static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = {
 563     pxa2xx_lcdc_read,
 564     pxa2xx_lcdc_read,
 565     pxa2xx_lcdc_read
 566 };
 567
 568 static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = {
 569     pxa2xx_lcdc_write,
 570     pxa2xx_lcdc_write,
 571     pxa2xx_lcdc_write
 572 };
 573
 574 /* Load new palette for a given DMA channel, convert to internal format */
 575 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
 576 {
 577     int i, n, format, r, g, b, alpha;
 578     uint32_t *dest, *src;
 579     s->pal_for = LCCR4_PALFOR(s->control[4]);
 580     format = s->pal_for;
 581
 582     switch (bpp) {
 583     case pxa_lcdc_2bpp:
 584         n = 4;
 585         break;
 586     case pxa_lcdc_4bpp:
 587         n = 16;
 588         break;
 589     case pxa_lcdc_8bpp:
 590         n = 256;
 591         break;
 592     default:
 593         format = 0;
 594         return;
 595     }
 596
 597     src = (uint32_t *) s->dma_ch[ch].pbuffer;
 598     dest = (uint32_t *) s->dma_ch[ch].palette;
 599     alpha = r = g = b = 0;
 600
 601     for (i = 0; i < n; i ++) {
 602         switch (format) {
 603         case 0: /* 16 bpp, no transparency */
 604             alpha = 0;
 605             if (s->control[0] & LCCR0_CMS)
 606                 r = g = b = *src & 0xff;
 607             else {
 608                 r = (*src & 0xf800) >> 8;
 609                 g = (*src & 0x07e0) >> 3;
 610                 b = (*src & 0x001f) << 3;
 611             }
 612             break;
 613         case 1: /* 16 bpp plus transparency */
 614             alpha = *src & (1 << 24);
 615             if (s->control[0] & LCCR0_CMS)
 616                 r = g = b = *src & 0xff;
 617             else {
 618                 r = (*src & 0xf800) >> 8;
 619                 g = (*src & 0x07e0) >> 3;
 620                 b = (*src & 0x001f) << 3;
 621             }
 622             break;
 623         case 2: /* 18 bpp plus transparency */
 624             alpha = *src & (1 << 24);
 625             if (s->control[0] & LCCR0_CMS)
 626                 r = g = b = *src & 0xff;
 627             else {
 628                 r = (*src & 0xf80000) >> 16;
 629                 g = (*src & 0x00fc00) >> 8;
 630                 b = (*src & 0x0000f8);
 631             }
 632             break;
 633         case 3: /* 24 bpp plus transparency */
 634             alpha = *src & (1 << 24);
 635             if (s->control[0] & LCCR0_CMS)
 636                 r = g = b = *src & 0xff;
 637             else {
 638                 r = (*src & 0xff0000) >> 16;
 639                 g = (*src & 0x00ff00) >> 8;
 640                 b = (*src & 0x0000ff);
 641             }
 642             break;
 643         }
 644         switch (ds_get_bits_per_pixel(s->ds)) {
 645         case 8:
 646             *dest = rgb_to_pixel8(r, g, b) | alpha;
 647             break;
 648         case 15:
 649             *dest = rgb_to_pixel15(r, g, b) | alpha;
 650             break;
 651         case 16:
 652             *dest = rgb_to_pixel16(r, g, b) | alpha;
 653             break;
 654         case 24:
 655             *dest = rgb_to_pixel24(r, g, b) | alpha;
 656             break;
 657         case 32:
 658             *dest = rgb_to_pixel32(r, g, b) | alpha;
 659             break;
 660         }
 661         src ++;
 662         dest ++;
 663     }
 664 }
 665
 666 static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
 667                 target_phys_addr_t addr, int *miny, int *maxy)
 668 {
 669     int src_width, dest_width;
 670     drawfn fn = NULL;
 671     if (s->dest_width)
 672         fn = s->line_fn[s->transp][s->bpp];
 673     if (!fn)
 674         return;
 675
 676     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 677     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 678         src_width *= 3;
 679     else if (s->bpp > pxa_lcdc_16bpp)
 680         src_width *= 4;
 681     else if (s->bpp > pxa_lcdc_8bpp)
 682         src_width *= 2;
 683
 684     dest_width = s->xres * s->dest_width;
 685     *miny = 0;
 686     framebuffer_update_display(s->ds,
 687                                addr, s->xres, s->yres,
 688                                src_width, dest_width, s->dest_width,
 689                                s->invalidated,
 690                                fn, s->dma_ch[0].palette, miny, maxy);
 691 }
 692
 693 static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s,
 694                target_phys_addr_t addr, int *miny, int *maxy)
 695 {
 696     int src_width, dest_width;
 697     drawfn fn = NULL;
 698     if (s->dest_width)
 699         fn = s->line_fn[s->transp][s->bpp];
 700     if (!fn)
 701         return;
 702
 703     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 704     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 705         src_width *= 3;
 706     else if (s->bpp > pxa_lcdc_16bpp)
 707         src_width *= 4;
 708     else if (s->bpp > pxa_lcdc_8bpp)
 709         src_width *= 2;
 710
 711     dest_width = s->yres * s->dest_width;
 712     *miny = 0;
 713     framebuffer_update_display(s->ds,
 714                                addr, s->xres, s->yres,
 715                                src_width, s->dest_width, -dest_width,
 716                                s->invalidated,
 717                                fn, s->dma_ch[0].palette,
 718                                miny, maxy);
 719 }
 720
 721 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
 722 {
 723     int width, height;
 724     if (!(s->control[0] & LCCR0_ENB))
 725         return;
 726
 727     width = LCCR1_PPL(s->control[1]) + 1;
 728     height = LCCR2_LPP(s->control[2]) + 1;
 729
 730     if (width != s->xres || height != s->yres) {
 731         if (s->orientation)
 732             qemu_console_resize(s->ds, height, width);
 733         else
 734             qemu_console_resize(s->ds, width, height);
 735         s->invalidated = 1;
 736         s->xres = width;
 737         s->yres = height;
 738     }
 739 }
 740
 741 static void pxa2xx_update_display(void *opaque)
 742 {
 743     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 744     target_phys_addr_t fbptr;
 745     int miny, maxy;
 746     int ch;
 747     if (!(s->control[0] & LCCR0_ENB))
 748         return;
 749
 750     pxa2xx_descriptor_load(s);
 751
 752     pxa2xx_lcdc_resize(s);
 753     miny = s->yres;
 754     maxy = 0;
 755     s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
 756     /* Note: With overlay planes the order depends on LCCR0 bit 25.  */
 757     for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
 758         if (s->dma_ch[ch].up) {
 759             if (!s->dma_ch[ch].source) {
 760                 pxa2xx_dma_ber_set(s, ch);
 761                 continue;
 762             }
 763             fbptr = s->dma_ch[ch].source;
 764             if (!(fbptr >= PXA2XX_SDRAM_BASE &&
 765                     fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
 766                 pxa2xx_dma_ber_set(s, ch);
 767                 continue;
 768             }
 769
 770             if (s->dma_ch[ch].command & LDCMD_PAL) {
 771                 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
 772                     MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
 773                         sizeof(s->dma_ch[ch].pbuffer)));
 774                 pxa2xx_palette_parse(s, ch, s->bpp);
 775             } else {
 776                 /* Do we need to reparse palette */
 777                 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
 778                     pxa2xx_palette_parse(s, ch, s->bpp);
 779
 780                 /* ACK frame start */
 781                 pxa2xx_dma_sof_set(s, ch);
 782
 783                 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
 784                 s->invalidated = 0;
 785
 786                 /* ACK frame completed */
 787                 pxa2xx_dma_eof_set(s, ch);
 788             }
 789         }
 790
 791     if (s->control[0] & LCCR0_DIS) {
 792         /* ACK last frame completed */
 793         s->control[0] &= ~LCCR0_ENB;
 794         s->status[0] |= LCSR0_LDD;
 795     }
 796
 797     if (miny >= 0) {
 798         if (s->orientation)
 799             dpy_update(s->ds, miny, 0, maxy, s->xres);
 800         else
 801             dpy_update(s->ds, 0, miny, s->xres, maxy);
 802     }
 803     pxa2xx_lcdc_int_update(s);
 804
 805     qemu_irq_raise(s->vsync_cb);
 806 }
 807
 808 static void pxa2xx_invalidate_display(void *opaque)
 809 {
 810     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 811     s->invalidated = 1;
 812 }
 813
 814 static void pxa2xx_screen_dump(void *opaque, const char *filename)
 815 {
 816     /* TODO */
 817 }
 818
 819 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 820 {
 821     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 822
 823     if (angle) {
 824         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
 825     } else {
 826         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
 827     }
 828
 829     s->orientation = angle;
 830     s->xres = s->yres = -1;
 831     pxa2xx_lcdc_resize(s);
 832 }
 833
 834 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
 835 {
 836     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 837     int i;
 838
 839     qemu_put_be32(f, s->irqlevel);
 840     qemu_put_be32(f, s->transp);
 841
 842     for (i = 0; i < 6; i ++)
 843         qemu_put_be32s(f, &s->control[i]);
 844     for (i = 0; i < 2; i ++)
 845         qemu_put_be32s(f, &s->status[i]);
 846     for (i = 0; i < 2; i ++)
 847         qemu_put_be32s(f, &s->ovl1c[i]);
 848     for (i = 0; i < 2; i ++)
 849         qemu_put_be32s(f, &s->ovl2c[i]);
 850     qemu_put_be32s(f, &s->ccr);
 851     qemu_put_be32s(f, &s->cmdcr);
 852     qemu_put_be32s(f, &s->trgbr);
 853     qemu_put_be32s(f, &s->tcr);
 854     qemu_put_be32s(f, &s->liidr);
 855     qemu_put_8s(f, &s->bscntr);
 856
 857     for (i = 0; i < 7; i ++) {
 858         qemu_put_betl(f, s->dma_ch[i].branch);
 859         qemu_put_byte(f, s->dma_ch[i].up);
 860         qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 861
 862         qemu_put_betl(f, s->dma_ch[i].descriptor);
 863         qemu_put_betl(f, s->dma_ch[i].source);
 864         qemu_put_be32s(f, &s->dma_ch[i].id);
 865         qemu_put_be32s(f, &s->dma_ch[i].command);
 866     }
 867 }
 868
 869 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
 870 {
 871     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 872     int i;
 873
 874     s->irqlevel = qemu_get_be32(f);
 875     s->transp = qemu_get_be32(f);
 876
 877     for (i = 0; i < 6; i ++)
 878         qemu_get_be32s(f, &s->control[i]);
 879     for (i = 0; i < 2; i ++)
 880         qemu_get_be32s(f, &s->status[i]);
 881     for (i = 0; i < 2; i ++)
 882         qemu_get_be32s(f, &s->ovl1c[i]);
 883     for (i = 0; i < 2; i ++)
 884         qemu_get_be32s(f, &s->ovl2c[i]);
 885     qemu_get_be32s(f, &s->ccr);
 886     qemu_get_be32s(f, &s->cmdcr);
 887     qemu_get_be32s(f, &s->trgbr);
 888     qemu_get_be32s(f, &s->tcr);
 889     qemu_get_be32s(f, &s->liidr);
 890     qemu_get_8s(f, &s->bscntr);
 891
 892     for (i = 0; i < 7; i ++) {
 893         s->dma_ch[i].branch = qemu_get_betl(f);
 894         s->dma_ch[i].up = qemu_get_byte(f);
 895         qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 896
 897         s->dma_ch[i].descriptor = qemu_get_betl(f);
 898         s->dma_ch[i].source = qemu_get_betl(f);
 899         qemu_get_be32s(f, &s->dma_ch[i].id);
 900         qemu_get_be32s(f, &s->dma_ch[i].command);
 901     }
 902
 903     s->bpp = LCCR3_BPP(s->control[3]);
 904     s->xres = s->yres = s->pal_for = -1;
 905
 906     return 0;
 907 }
 908
 909 #define BITS 8
 910 #include "pxa2xx_template.h"
 911 #define BITS 15
 912 #include "pxa2xx_template.h"
 913 #define BITS 16
 914 #include "pxa2xx_template.h"
 915 #define BITS 24
 916 #include "pxa2xx_template.h"
 917 #define BITS 32
 918 #include "pxa2xx_template.h"
 919
 920 PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
 921 {
 922     int iomemtype;
 923     PXA2xxLCDState *s;
 924
 925     s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
 926     s->invalidated = 1;
 927     s->irq = irq;
 928
 929     pxa2xx_lcdc_orientation(s, graphic_rotate);
 930
 931     iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
 932                     pxa2xx_lcdc_writefn, s);
 933     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 934
 935     s->ds = graphic_console_init(pxa2xx_update_display,
 936                                  pxa2xx_invalidate_display,
 937                                  pxa2xx_screen_dump, NULL, s);
 938
 939     switch (ds_get_bits_per_pixel(s->ds)) {
 940     case 0:
 941         s->dest_width = 0;
 942         break;
 943     case 8:
 944         s->line_fn[0] = pxa2xx_draw_fn_8;
 945         s->line_fn[1] = pxa2xx_draw_fn_8t;
 946         s->dest_width = 1;
 947         break;
 948     case 15:
 949         s->line_fn[0] = pxa2xx_draw_fn_15;
 950         s->line_fn[1] = pxa2xx_draw_fn_15t;
 951         s->dest_width = 2;
 952         break;
 953     case 16:
 954         s->line_fn[0] = pxa2xx_draw_fn_16;
 955         s->line_fn[1] = pxa2xx_draw_fn_16t;
 956         s->dest_width = 2;
 957         break;
 958     case 24:
 959         s->line_fn[0] = pxa2xx_draw_fn_24;
 960         s->line_fn[1] = pxa2xx_draw_fn_24t;
 961         s->dest_width = 3;
 962         break;
 963     case 32:
 964         s->line_fn[0] = pxa2xx_draw_fn_32;
 965         s->line_fn[1] = pxa2xx_draw_fn_32t;
 966         s->dest_width = 4;
 967         break;
 968     default:
 969         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 970         exit(1);
 971     }
 972
 973     register_savevm("pxa2xx_lcdc", 0, 0,
 974                     pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
 975
 976     return s;
 977 }
 978
 979 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
 980 {
 981     s->vsync_cb = handler;
 982 }