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virtio-9p: Add fidtype so that we can do type specific operation
[qemu/stefanha.git] / hw / pci.c
bloba98d6f3ad1730de0cf5b798fd6d8cd9c58e9db10
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29 #include "loader.h"
30 #include "qemu-objects.h"
31
32 //#define DEBUG_PCI
33 #ifdef DEBUG_PCI
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
35 #else
36 # define PCI_DPRINTF(format, ...) do { } while (0)
37 #endif
38
39 struct PCIBus {
40 BusState qbus;
41 int devfn_min;
42 pci_set_irq_fn set_irq;
43 pci_map_irq_fn map_irq;
44 pci_hotplug_fn hotplug;
45 DeviceState *hotplug_qdev;
46 void *irq_opaque;
47 PCIDevice *devices[256];
48 PCIDevice *parent_dev;
49 target_phys_addr_t mem_base;
50
51 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
53
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
56 int nirq;
57 int *irq_count;
58 };
59
60 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
61 static char *pcibus_get_dev_path(DeviceState *dev);
62
63 static struct BusInfo pci_bus_info = {
64 .name = "PCI",
65 .size = sizeof(PCIBus),
66 .print_dev = pcibus_dev_print,
67 .get_dev_path = pcibus_get_dev_path,
68 .props = (Property[]) {
69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
70 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
71 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
72 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
74 DEFINE_PROP_END_OF_LIST()
75 }
76 };
77
78 static void pci_update_mappings(PCIDevice *d);
79 static void pci_set_irq(void *opaque, int irq_num, int level);
80 static int pci_add_option_rom(PCIDevice *pdev);
81 static void pci_del_option_rom(PCIDevice *pdev);
82
83 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
84 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
85
86 struct PCIHostBus {
87 int domain;
88 struct PCIBus *bus;
89 QLIST_ENTRY(PCIHostBus) next;
90 };
91 static QLIST_HEAD(, PCIHostBus) host_buses;
92
93 static const VMStateDescription vmstate_pcibus = {
94 .name = "PCIBUS",
95 .version_id = 1,
96 .minimum_version_id = 1,
97 .minimum_version_id_old = 1,
98 .fields = (VMStateField []) {
99 VMSTATE_INT32_EQUAL(nirq, PCIBus),
100 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
101 VMSTATE_END_OF_LIST()
102 }
103 };
104
105 static int pci_bar(PCIDevice *d, int reg)
106 {
107 uint8_t type;
108
109 if (reg != PCI_ROM_SLOT)
110 return PCI_BASE_ADDRESS_0 + reg * 4;
111
112 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
113 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
114 }
115
116 static inline int pci_irq_state(PCIDevice *d, int irq_num)
117 {
118 return (d->irq_state >> irq_num) & 0x1;
119 }
120
121 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
122 {
123 d->irq_state &= ~(0x1 << irq_num);
124 d->irq_state |= level << irq_num;
125 }
126
127 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
128 {
129 PCIBus *bus;
130 for (;;) {
131 bus = pci_dev->bus;
132 irq_num = bus->map_irq(pci_dev, irq_num);
133 if (bus->set_irq)
134 break;
135 pci_dev = bus->parent_dev;
136 }
137 bus->irq_count[irq_num] += change;
138 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
139 }
140
141 /* Update interrupt status bit in config space on interrupt
142 * state change. */
143 static void pci_update_irq_status(PCIDevice *dev)
144 {
145 if (dev->irq_state) {
146 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
147 } else {
148 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
149 }
150 }
151
152 static void pci_device_reset(PCIDevice *dev)
153 {
154 int r;
155
156 dev->irq_state = 0;
157 pci_update_irq_status(dev);
158 /* Clear all writeable bits */
159 pci_set_word(dev->config + PCI_COMMAND,
160 pci_get_word(dev->config + PCI_COMMAND) &
161 ~pci_get_word(dev->wmask + PCI_COMMAND));
162 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
163 dev->config[PCI_INTERRUPT_LINE] = 0x0;
164 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
165 PCIIORegion *region = &dev->io_regions[r];
166 if (!region->size) {
167 continue;
168 }
169
170 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
171 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
172 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
173 } else {
174 pci_set_long(dev->config + pci_bar(dev, r), region->type);
175 }
176 }
177 pci_update_mappings(dev);
178 }
179
180 static void pci_bus_reset(void *opaque)
181 {
182 PCIBus *bus = opaque;
183 int i;
184
185 for (i = 0; i < bus->nirq; i++) {
186 bus->irq_count[i] = 0;
187 }
188 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
189 if (bus->devices[i]) {
190 pci_device_reset(bus->devices[i]);
191 }
192 }
193 }
194
195 static void pci_host_bus_register(int domain, PCIBus *bus)
196 {
197 struct PCIHostBus *host;
198 host = qemu_mallocz(sizeof(*host));
199 host->domain = domain;
200 host->bus = bus;
201 QLIST_INSERT_HEAD(&host_buses, host, next);
202 }
203
204 PCIBus *pci_find_root_bus(int domain)
205 {
206 struct PCIHostBus *host;
207
208 QLIST_FOREACH(host, &host_buses, next) {
209 if (host->domain == domain) {
210 return host->bus;
211 }
212 }
213
214 return NULL;
215 }
216
217 int pci_find_domain(const PCIBus *bus)
218 {
219 PCIDevice *d;
220 struct PCIHostBus *host;
221
222 /* obtain root bus */
223 while ((d = bus->parent_dev) != NULL) {
224 bus = d->bus;
225 }
226
227 QLIST_FOREACH(host, &host_buses, next) {
228 if (host->bus == bus) {
229 return host->domain;
230 }
231 }
232
233 abort(); /* should not be reached */
234 return -1;
235 }
236
237 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
238 const char *name, int devfn_min)
239 {
240 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
241 assert(PCI_FUNC(devfn_min) == 0);
242 bus->devfn_min = devfn_min;
243
244 /* host bridge */
245 QLIST_INIT(&bus->child);
246 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
247
248 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
249 qemu_register_reset(pci_bus_reset, bus);
250 }
251
252 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
253 {
254 PCIBus *bus;
255
256 bus = qemu_mallocz(sizeof(*bus));
257 bus->qbus.qdev_allocated = 1;
258 pci_bus_new_inplace(bus, parent, name, devfn_min);
259 return bus;
260 }
261
262 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
263 void *irq_opaque, int nirq)
264 {
265 bus->set_irq = set_irq;
266 bus->map_irq = map_irq;
267 bus->irq_opaque = irq_opaque;
268 bus->nirq = nirq;
269 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
270 }
271
272 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
273 {
274 bus->qbus.allow_hotplug = 1;
275 bus->hotplug = hotplug;
276 bus->hotplug_qdev = qdev;
277 }
278
279 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
280 {
281 bus->mem_base = base;
282 }
283
284 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
285 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
286 void *irq_opaque, int devfn_min, int nirq)
287 {
288 PCIBus *bus;
289
290 bus = pci_bus_new(parent, name, devfn_min);
291 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
292 return bus;
293 }
294
295 static void pci_register_secondary_bus(PCIBus *parent,
296 PCIBus *bus,
297 PCIDevice *dev,
298 pci_map_irq_fn map_irq,
299 const char *name)
300 {
301 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
302 bus->map_irq = map_irq;
303 bus->parent_dev = dev;
304
305 QLIST_INIT(&bus->child);
306 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
307 }
308
309 static void pci_unregister_secondary_bus(PCIBus *bus)
310 {
311 assert(QLIST_EMPTY(&bus->child));
312 QLIST_REMOVE(bus, sibling);
313 }
314
315 int pci_bus_num(PCIBus *s)
316 {
317 if (!s->parent_dev)
318 return 0; /* pci host bridge */
319 return s->parent_dev->config[PCI_SECONDARY_BUS];
320 }
321
322 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
323 {
324 PCIDevice *s = container_of(pv, PCIDevice, config);
325 uint8_t *config;
326 int i;
327
328 assert(size == pci_config_size(s));
329 config = qemu_malloc(size);
330
331 qemu_get_buffer(f, config, size);
332 for (i = 0; i < size; ++i) {
333 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
334 qemu_free(config);
335 return -EINVAL;
336 }
337 }
338 memcpy(s->config, config, size);
339
340 pci_update_mappings(s);
341
342 qemu_free(config);
343 return 0;
344 }
345
346 /* just put buffer */
347 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
348 {
349 const uint8_t **v = pv;
350 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
351 qemu_put_buffer(f, *v, size);
352 }
353
354 static VMStateInfo vmstate_info_pci_config = {
355 .name = "pci config",
356 .get = get_pci_config_device,
357 .put = put_pci_config_device,
358 };
359
360 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
361 {
362 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
363 uint32_t irq_state[PCI_NUM_PINS];
364 int i;
365 for (i = 0; i < PCI_NUM_PINS; ++i) {
366 irq_state[i] = qemu_get_be32(f);
367 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
368 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
369 irq_state[i]);
370 return -EINVAL;
371 }
372 }
373
374 for (i = 0; i < PCI_NUM_PINS; ++i) {
375 pci_set_irq_state(s, i, irq_state[i]);
376 }
377
378 return 0;
379 }
380
381 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
382 {
383 int i;
384 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
385
386 for (i = 0; i < PCI_NUM_PINS; ++i) {
387 qemu_put_be32(f, pci_irq_state(s, i));
388 }
389 }
390
391 static VMStateInfo vmstate_info_pci_irq_state = {
392 .name = "pci irq state",
393 .get = get_pci_irq_state,
394 .put = put_pci_irq_state,
395 };
396
397 const VMStateDescription vmstate_pci_device = {
398 .name = "PCIDevice",
399 .version_id = 2,
400 .minimum_version_id = 1,
401 .minimum_version_id_old = 1,
402 .fields = (VMStateField []) {
403 VMSTATE_INT32_LE(version_id, PCIDevice),
404 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
405 vmstate_info_pci_config,
406 PCI_CONFIG_SPACE_SIZE),
407 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
408 vmstate_info_pci_irq_state,
409 PCI_NUM_PINS * sizeof(int32_t)),
410 VMSTATE_END_OF_LIST()
411 }
412 };
413
414 const VMStateDescription vmstate_pcie_device = {
415 .name = "PCIDevice",
416 .version_id = 2,
417 .minimum_version_id = 1,
418 .minimum_version_id_old = 1,
419 .fields = (VMStateField []) {
420 VMSTATE_INT32_LE(version_id, PCIDevice),
421 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
422 vmstate_info_pci_config,
423 PCIE_CONFIG_SPACE_SIZE),
424 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
425 vmstate_info_pci_irq_state,
426 PCI_NUM_PINS * sizeof(int32_t)),
427 VMSTATE_END_OF_LIST()
428 }
429 };
430
431 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
432 {
433 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
434 }
435
436 void pci_device_save(PCIDevice *s, QEMUFile *f)
437 {
438 /* Clear interrupt status bit: it is implicit
439 * in irq_state which we are saving.
440 * This makes us compatible with old devices
441 * which never set or clear this bit. */
442 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
443 vmstate_save_state(f, pci_get_vmstate(s), s);
444 /* Restore the interrupt status bit. */
445 pci_update_irq_status(s);
446 }
447
448 int pci_device_load(PCIDevice *s, QEMUFile *f)
449 {
450 int ret;
451 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
452 /* Restore the interrupt status bit. */
453 pci_update_irq_status(s);
454 return ret;
455 }
456
457 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
458 {
459 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
460 pci_default_sub_vendor_id);
461 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
462 pci_default_sub_device_id);
463 }
464
465 /*
466 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
467 */
468 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
469 {
470 const char *p;
471 char *e;
472 unsigned long val;
473 unsigned long dom = 0, bus = 0;
474 unsigned slot = 0;
475
476 p = addr;
477 val = strtoul(p, &e, 16);
478 if (e == p)
479 return -1;
480 if (*e == ':') {
481 bus = val;
482 p = e + 1;
483 val = strtoul(p, &e, 16);
484 if (e == p)
485 return -1;
486 if (*e == ':') {
487 dom = bus;
488 bus = val;
489 p = e + 1;
490 val = strtoul(p, &e, 16);
491 if (e == p)
492 return -1;
493 }
494 }
495
496 if (dom > 0xffff || bus > 0xff || val > 0x1f)
497 return -1;
498
499 slot = val;
500
501 if (*e)
502 return -1;
503
504 /* Note: QEMU doesn't implement domains other than 0 */
505 if (!pci_find_bus(pci_find_root_bus(dom), bus))
506 return -1;
507
508 *domp = dom;
509 *busp = bus;
510 *slotp = slot;
511 return 0;
512 }
513
514 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
515 unsigned *slotp)
516 {
517 /* strip legacy tag */
518 if (!strncmp(addr, "pci_addr=", 9)) {
519 addr += 9;
520 }
521 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
522 monitor_printf(mon, "Invalid pci address\n");
523 return -1;
524 }
525 return 0;
526 }
527
528 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
529 {
530 int dom, bus;
531 unsigned slot;
532
533 if (!devaddr) {
534 *devfnp = -1;
535 return pci_find_bus(pci_find_root_bus(0), 0);
536 }
537
538 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
539 return NULL;
540 }
541
542 *devfnp = slot << 3;
543 return pci_find_bus(pci_find_root_bus(dom), bus);
544 }
545
546 static void pci_init_cmask(PCIDevice *dev)
547 {
548 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
549 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
550 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
551 dev->cmask[PCI_REVISION_ID] = 0xff;
552 dev->cmask[PCI_CLASS_PROG] = 0xff;
553 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
554 dev->cmask[PCI_HEADER_TYPE] = 0xff;
555 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
556 }
557
558 static void pci_init_wmask(PCIDevice *dev)
559 {
560 int config_size = pci_config_size(dev);
561
562 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
563 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
564 pci_set_word(dev->wmask + PCI_COMMAND,
565 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
566 PCI_COMMAND_INTX_DISABLE);
567
568 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
569 config_size - PCI_CONFIG_HEADER_SIZE);
570 }
571
572 static void pci_init_wmask_bridge(PCIDevice *d)
573 {
574 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
575 PCI_SEC_LETENCY_TIMER */
576 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
577
578 /* base and limit */
579 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
580 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
581 pci_set_word(d->wmask + PCI_MEMORY_BASE,
582 PCI_MEMORY_RANGE_MASK & 0xffff);
583 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
584 PCI_MEMORY_RANGE_MASK & 0xffff);
585 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
586 PCI_PREF_RANGE_MASK & 0xffff);
587 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
588 PCI_PREF_RANGE_MASK & 0xffff);
589
590 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
591 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
592
593 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
594 }
595
596 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
597 {
598 uint8_t slot = PCI_SLOT(dev->devfn);
599 uint8_t func;
600
601 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
602 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
603 }
604
605 /*
606 * multifuction bit is interpreted in two ways as follows.
607 * - all functions must set the bit to 1.
608 * Example: Intel X53
609 * - function 0 must set the bit, but the rest function (> 0)
610 * is allowed to leave the bit to 0.
611 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
612 *
613 * So OS (at least Linux) checks the bit of only function 0,
614 * and doesn't see the bit of function > 0.
615 *
616 * The below check allows both interpretation.
617 */
618 if (PCI_FUNC(dev->devfn)) {
619 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
620 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
621 /* function 0 should set multifunction bit */
622 error_report("PCI: single function device can't be populated "
623 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
624 return -1;
625 }
626 return 0;
627 }
628
629 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
630 return 0;
631 }
632 /* function 0 indicates single function, so function > 0 must be NULL */
633 for (func = 1; func < PCI_FUNC_MAX; ++func) {
634 if (bus->devices[PCI_DEVFN(slot, func)]) {
635 error_report("PCI: %x.0 indicates single function, "
636 "but %x.%x is already populated.",
637 slot, slot, func);
638 return -1;
639 }
640 }
641 return 0;
642 }
643
644 static void pci_config_alloc(PCIDevice *pci_dev)
645 {
646 int config_size = pci_config_size(pci_dev);
647
648 pci_dev->config = qemu_mallocz(config_size);
649 pci_dev->cmask = qemu_mallocz(config_size);
650 pci_dev->wmask = qemu_mallocz(config_size);
651 pci_dev->used = qemu_mallocz(config_size);
652 }
653
654 static void pci_config_free(PCIDevice *pci_dev)
655 {
656 qemu_free(pci_dev->config);
657 qemu_free(pci_dev->cmask);
658 qemu_free(pci_dev->wmask);
659 qemu_free(pci_dev->used);
660 }
661
662 /* -1 for devfn means auto assign */
663 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
664 const char *name, int devfn,
665 PCIConfigReadFunc *config_read,
666 PCIConfigWriteFunc *config_write,
667 bool is_bridge)
668 {
669 if (devfn < 0) {
670 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
671 devfn += PCI_FUNC_MAX) {
672 if (!bus->devices[devfn])
673 goto found;
674 }
675 error_report("PCI: no slot/function available for %s, all in use", name);
676 return NULL;
677 found: ;
678 } else if (bus->devices[devfn]) {
679 error_report("PCI: slot %d function %d not available for %s, in use by %s",
680 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
681 return NULL;
682 }
683 pci_dev->bus = bus;
684 pci_dev->devfn = devfn;
685 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
686 pci_dev->irq_state = 0;
687 pci_config_alloc(pci_dev);
688
689 if (!is_bridge) {
690 pci_set_default_subsystem_id(pci_dev);
691 }
692 pci_init_cmask(pci_dev);
693 pci_init_wmask(pci_dev);
694 if (is_bridge) {
695 pci_init_wmask_bridge(pci_dev);
696 }
697 if (pci_init_multifunction(bus, pci_dev)) {
698 pci_config_free(pci_dev);
699 return NULL;
700 }
701
702 if (!config_read)
703 config_read = pci_default_read_config;
704 if (!config_write)
705 config_write = pci_default_write_config;
706 pci_dev->config_read = config_read;
707 pci_dev->config_write = config_write;
708 bus->devices[devfn] = pci_dev;
709 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
710 pci_dev->version_id = 2; /* Current pci device vmstate version */
711 return pci_dev;
712 }
713
714 static void do_pci_unregister_device(PCIDevice *pci_dev)
715 {
716 qemu_free_irqs(pci_dev->irq);
717 pci_dev->bus->devices[pci_dev->devfn] = NULL;
718 pci_config_free(pci_dev);
719 }
720
721 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
722 int instance_size, int devfn,
723 PCIConfigReadFunc *config_read,
724 PCIConfigWriteFunc *config_write)
725 {
726 PCIDevice *pci_dev;
727
728 pci_dev = qemu_mallocz(instance_size);
729 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
730 config_read, config_write,
731 PCI_HEADER_TYPE_NORMAL);
732 if (pci_dev == NULL) {
733 hw_error("PCI: can't register device\n");
734 }
735 return pci_dev;
736 }
737
738 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
739 target_phys_addr_t addr)
740 {
741 return addr + bus->mem_base;
742 }
743
744 static void pci_unregister_io_regions(PCIDevice *pci_dev)
745 {
746 PCIIORegion *r;
747 int i;
748
749 for(i = 0; i < PCI_NUM_REGIONS; i++) {
750 r = &pci_dev->io_regions[i];
751 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
752 continue;
753 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
754 isa_unassign_ioport(r->addr, r->filtered_size);
755 } else {
756 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
757 r->addr),
758 r->filtered_size,
759 IO_MEM_UNASSIGNED);
760 }
761 }
762 }
763
764 static int pci_unregister_device(DeviceState *dev)
765 {
766 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
767 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
768 int ret = 0;
769
770 if (info->exit)
771 ret = info->exit(pci_dev);
772 if (ret)
773 return ret;
774
775 pci_unregister_io_regions(pci_dev);
776 pci_del_option_rom(pci_dev);
777 do_pci_unregister_device(pci_dev);
778 return 0;
779 }
780
781 void pci_register_bar(PCIDevice *pci_dev, int region_num,
782 pcibus_t size, int type,
783 PCIMapIORegionFunc *map_func)
784 {
785 PCIIORegion *r;
786 uint32_t addr;
787 pcibus_t wmask;
788
789 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
790 return;
791
792 if (size & (size-1)) {
793 fprintf(stderr, "ERROR: PCI region size must be pow2 "
794 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
795 exit(1);
796 }
797
798 r = &pci_dev->io_regions[region_num];
799 r->addr = PCI_BAR_UNMAPPED;
800 r->size = size;
801 r->filtered_size = size;
802 r->type = type;
803 r->map_func = map_func;
804
805 wmask = ~(size - 1);
806 addr = pci_bar(pci_dev, region_num);
807 if (region_num == PCI_ROM_SLOT) {
808 /* ROM enable bit is writeable */
809 wmask |= PCI_ROM_ADDRESS_ENABLE;
810 }
811 pci_set_long(pci_dev->config + addr, type);
812 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
813 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
814 pci_set_quad(pci_dev->wmask + addr, wmask);
815 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
816 } else {
817 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
818 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
819 }
820 }
821
822 static uint32_t pci_config_get_io_base(PCIDevice *d,
823 uint32_t base, uint32_t base_upper16)
824 {
825 uint32_t val;
826
827 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
828 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
829 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
830 }
831 return val;
832 }
833
834 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
835 {
836 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
837 << 16;
838 }
839
840 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
841 uint32_t base, uint32_t upper)
842 {
843 pcibus_t tmp;
844 pcibus_t val;
845
846 tmp = (pcibus_t)pci_get_word(d->config + base);
847 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
848 if (tmp & PCI_PREF_RANGE_TYPE_64) {
849 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
850 }
851 return val;
852 }
853
854 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
855 {
856 pcibus_t base;
857 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
858 base = pci_config_get_io_base(bridge,
859 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
860 } else {
861 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
862 base = pci_config_get_pref_base(
863 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
864 } else {
865 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
866 }
867 }
868
869 return base;
870 }
871
872 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
873 {
874 pcibus_t limit;
875 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
876 limit = pci_config_get_io_base(bridge,
877 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
878 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
879 } else {
880 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
881 limit = pci_config_get_pref_base(
882 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
883 } else {
884 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
885 }
886 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
887 }
888 return limit;
889 }
890
891 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
892 uint8_t type)
893 {
894 pcibus_t base = *addr;
895 pcibus_t limit = *addr + *size - 1;
896 PCIDevice *br;
897
898 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
899 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
900
901 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
902 if (!(cmd & PCI_COMMAND_IO)) {
903 goto no_map;
904 }
905 } else {
906 if (!(cmd & PCI_COMMAND_MEMORY)) {
907 goto no_map;
908 }
909 }
910
911 base = MAX(base, pci_bridge_get_base(br, type));
912 limit = MIN(limit, pci_bridge_get_limit(br, type));
913 }
914
915 if (base > limit) {
916 goto no_map;
917 }
918 *addr = base;
919 *size = limit - base + 1;
920 return;
921 no_map:
922 *addr = PCI_BAR_UNMAPPED;
923 *size = 0;
924 }
925
926 static pcibus_t pci_bar_address(PCIDevice *d,
927 int reg, uint8_t type, pcibus_t size)
928 {
929 pcibus_t new_addr, last_addr;
930 int bar = pci_bar(d, reg);
931 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
932
933 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
934 if (!(cmd & PCI_COMMAND_IO)) {
935 return PCI_BAR_UNMAPPED;
936 }
937 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
938 last_addr = new_addr + size - 1;
939 /* NOTE: we have only 64K ioports on PC */
940 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
941 return PCI_BAR_UNMAPPED;
942 }
943 return new_addr;
944 }
945
946 if (!(cmd & PCI_COMMAND_MEMORY)) {
947 return PCI_BAR_UNMAPPED;
948 }
949 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
950 new_addr = pci_get_quad(d->config + bar);
951 } else {
952 new_addr = pci_get_long(d->config + bar);
953 }
954 /* the ROM slot has a specific enable bit */
955 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
956 return PCI_BAR_UNMAPPED;
957 }
958 new_addr &= ~(size - 1);
959 last_addr = new_addr + size - 1;
960 /* NOTE: we do not support wrapping */
961 /* XXX: as we cannot support really dynamic
962 mappings, we handle specific values as invalid
963 mappings. */
964 if (last_addr <= new_addr || new_addr == 0 ||
965 last_addr == PCI_BAR_UNMAPPED) {
966 return PCI_BAR_UNMAPPED;
967 }
968
969 /* Now pcibus_t is 64bit.
970 * Check if 32 bit BAR wraps around explicitly.
971 * Without this, PC ide doesn't work well.
972 * TODO: remove this work around.
973 */
974 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
975 return PCI_BAR_UNMAPPED;
976 }
977
978 /*
979 * OS is allowed to set BAR beyond its addressable
980 * bits. For example, 32 bit OS can set 64bit bar
981 * to >4G. Check it. TODO: we might need to support
982 * it in the future for e.g. PAE.
983 */
984 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
985 return PCI_BAR_UNMAPPED;
986 }
987
988 return new_addr;
989 }
990
991 static void pci_update_mappings(PCIDevice *d)
992 {
993 PCIIORegion *r;
994 int i;
995 pcibus_t new_addr, filtered_size;
996
997 for(i = 0; i < PCI_NUM_REGIONS; i++) {
998 r = &d->io_regions[i];
999
1000 /* this region isn't registered */
1001 if (!r->size)
1002 continue;
1003
1004 new_addr = pci_bar_address(d, i, r->type, r->size);
1005
1006 /* bridge filtering */
1007 filtered_size = r->size;
1008 if (new_addr != PCI_BAR_UNMAPPED) {
1009 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1010 }
1011
1012 /* This bar isn't changed */
1013 if (new_addr == r->addr && filtered_size == r->filtered_size)
1014 continue;
1015
1016 /* now do the real mapping */
1017 if (r->addr != PCI_BAR_UNMAPPED) {
1018 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1019 int class;
1020 /* NOTE: specific hack for IDE in PC case:
1021 only one byte must be mapped. */
1022 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1023 if (class == 0x0101 && r->size == 4) {
1024 isa_unassign_ioport(r->addr + 2, 1);
1025 } else {
1026 isa_unassign_ioport(r->addr, r->filtered_size);
1027 }
1028 } else {
1029 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1030 r->filtered_size,
1031 IO_MEM_UNASSIGNED);
1032 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1033 }
1034 }
1035 r->addr = new_addr;
1036 r->filtered_size = filtered_size;
1037 if (r->addr != PCI_BAR_UNMAPPED) {
1038 /*
1039 * TODO: currently almost all the map funcions assumes
1040 * filtered_size == size and addr & ~(size - 1) == addr.
1041 * However with bridge filtering, they aren't always true.
1042 * Teach them such cases, such that filtered_size < size and
1043 * addr & (size - 1) != 0.
1044 */
1045 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1046 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1047 } else {
1048 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1049 r->filtered_size, r->type);
1050 }
1051 }
1052 }
1053 }
1054
1055 static inline int pci_irq_disabled(PCIDevice *d)
1056 {
1057 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1058 }
1059
1060 /* Called after interrupt disabled field update in config space,
1061 * assert/deassert interrupts if necessary.
1062 * Gets original interrupt disable bit value (before update). */
1063 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1064 {
1065 int i, disabled = pci_irq_disabled(d);
1066 if (disabled == was_irq_disabled)
1067 return;
1068 for (i = 0; i < PCI_NUM_PINS; ++i) {
1069 int state = pci_irq_state(d, i);
1070 pci_change_irq_level(d, i, disabled ? -state : state);
1071 }
1072 }
1073
1074 uint32_t pci_default_read_config(PCIDevice *d,
1075 uint32_t address, int len)
1076 {
1077 uint32_t val = 0;
1078 assert(len == 1 || len == 2 || len == 4);
1079 len = MIN(len, pci_config_size(d) - address);
1080 memcpy(&val, d->config + address, len);
1081 return le32_to_cpu(val);
1082 }
1083
1084 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1085 {
1086 int i, was_irq_disabled = pci_irq_disabled(d);
1087 uint32_t config_size = pci_config_size(d);
1088
1089 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1090 uint8_t wmask = d->wmask[addr + i];
1091 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1092 }
1093 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1094 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1095 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1096 range_covers_byte(addr, l, PCI_COMMAND))
1097 pci_update_mappings(d);
1098
1099 if (range_covers_byte(addr, l, PCI_COMMAND))
1100 pci_update_irq_disabled(d, was_irq_disabled);
1101 }
1102
1103 /***********************************************************/
1104 /* generic PCI irq support */
1105
1106 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1107 static void pci_set_irq(void *opaque, int irq_num, int level)
1108 {
1109 PCIDevice *pci_dev = opaque;
1110 int change;
1111
1112 change = level - pci_irq_state(pci_dev, irq_num);
1113 if (!change)
1114 return;
1115
1116 pci_set_irq_state(pci_dev, irq_num, level);
1117 pci_update_irq_status(pci_dev);
1118 if (pci_irq_disabled(pci_dev))
1119 return;
1120 pci_change_irq_level(pci_dev, irq_num, change);
1121 }
1122
1123 /***********************************************************/
1124 /* monitor info on PCI */
1125
1126 typedef struct {
1127 uint16_t class;
1128 const char *desc;
1129 } pci_class_desc;
1130
1131 static const pci_class_desc pci_class_descriptions[] =
1132 {
1133 { 0x0100, "SCSI controller"},
1134 { 0x0101, "IDE controller"},
1135 { 0x0102, "Floppy controller"},
1136 { 0x0103, "IPI controller"},
1137 { 0x0104, "RAID controller"},
1138 { 0x0106, "SATA controller"},
1139 { 0x0107, "SAS controller"},
1140 { 0x0180, "Storage controller"},
1141 { 0x0200, "Ethernet controller"},
1142 { 0x0201, "Token Ring controller"},
1143 { 0x0202, "FDDI controller"},
1144 { 0x0203, "ATM controller"},
1145 { 0x0280, "Network controller"},
1146 { 0x0300, "VGA controller"},
1147 { 0x0301, "XGA controller"},
1148 { 0x0302, "3D controller"},
1149 { 0x0380, "Display controller"},
1150 { 0x0400, "Video controller"},
1151 { 0x0401, "Audio controller"},
1152 { 0x0402, "Phone"},
1153 { 0x0480, "Multimedia controller"},
1154 { 0x0500, "RAM controller"},
1155 { 0x0501, "Flash controller"},
1156 { 0x0580, "Memory controller"},
1157 { 0x0600, "Host bridge"},
1158 { 0x0601, "ISA bridge"},
1159 { 0x0602, "EISA bridge"},
1160 { 0x0603, "MC bridge"},
1161 { 0x0604, "PCI bridge"},
1162 { 0x0605, "PCMCIA bridge"},
1163 { 0x0606, "NUBUS bridge"},
1164 { 0x0607, "CARDBUS bridge"},
1165 { 0x0608, "RACEWAY bridge"},
1166 { 0x0680, "Bridge"},
1167 { 0x0c03, "USB controller"},
1168 { 0, NULL}
1169 };
1170
1171 static void pci_for_each_device_under_bus(PCIBus *bus,
1172 void (*fn)(PCIBus *b, PCIDevice *d))
1173 {
1174 PCIDevice *d;
1175 int devfn;
1176
1177 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1178 d = bus->devices[devfn];
1179 if (d) {
1180 fn(bus, d);
1181 }
1182 }
1183 }
1184
1185 void pci_for_each_device(PCIBus *bus, int bus_num,
1186 void (*fn)(PCIBus *b, PCIDevice *d))
1187 {
1188 bus = pci_find_bus(bus, bus_num);
1189
1190 if (bus) {
1191 pci_for_each_device_under_bus(bus, fn);
1192 }
1193 }
1194
1195 static void pci_device_print(Monitor *mon, QDict *device)
1196 {
1197 QDict *qdict;
1198 QListEntry *entry;
1199 uint64_t addr, size;
1200
1201 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1202 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1203 qdict_get_int(device, "slot"),
1204 qdict_get_int(device, "function"));
1205 monitor_printf(mon, " ");
1206
1207 qdict = qdict_get_qdict(device, "class_info");
1208 if (qdict_haskey(qdict, "desc")) {
1209 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1210 } else {
1211 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1212 }
1213
1214 qdict = qdict_get_qdict(device, "id");
1215 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1216 qdict_get_int(qdict, "device"),
1217 qdict_get_int(qdict, "vendor"));
1218
1219 if (qdict_haskey(device, "irq")) {
1220 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1221 qdict_get_int(device, "irq"));
1222 }
1223
1224 if (qdict_haskey(device, "pci_bridge")) {
1225 QDict *info;
1226
1227 qdict = qdict_get_qdict(device, "pci_bridge");
1228
1229 info = qdict_get_qdict(qdict, "bus");
1230 monitor_printf(mon, " BUS %" PRId64 ".\n",
1231 qdict_get_int(info, "number"));
1232 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1233 qdict_get_int(info, "secondary"));
1234 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1235 qdict_get_int(info, "subordinate"));
1236
1237 info = qdict_get_qdict(qdict, "io_range");
1238 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1239 qdict_get_int(info, "base"),
1240 qdict_get_int(info, "limit"));
1241
1242 info = qdict_get_qdict(qdict, "memory_range");
1243 monitor_printf(mon,
1244 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1245 qdict_get_int(info, "base"),
1246 qdict_get_int(info, "limit"));
1247
1248 info = qdict_get_qdict(qdict, "prefetchable_range");
1249 monitor_printf(mon, " prefetchable memory range "
1250 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1251 qdict_get_int(info, "base"),
1252 qdict_get_int(info, "limit"));
1253 }
1254
1255 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1256 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1257 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1258
1259 addr = qdict_get_int(qdict, "address");
1260 size = qdict_get_int(qdict, "size");
1261
1262 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1263 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1264 " [0x%04"FMT_PCIBUS"].\n",
1265 addr, addr + size - 1);
1266 } else {
1267 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1268 " [0x%08"FMT_PCIBUS"].\n",
1269 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1270 qdict_get_bool(qdict, "prefetch") ?
1271 " prefetchable" : "", addr, addr + size - 1);
1272 }
1273 }
1274
1275 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1276
1277 if (qdict_haskey(device, "pci_bridge")) {
1278 qdict = qdict_get_qdict(device, "pci_bridge");
1279 if (qdict_haskey(qdict, "devices")) {
1280 QListEntry *dev;
1281 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1282 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1283 }
1284 }
1285 }
1286 }
1287
1288 void do_pci_info_print(Monitor *mon, const QObject *data)
1289 {
1290 QListEntry *bus, *dev;
1291
1292 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1293 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1294 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1295 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1296 }
1297 }
1298 }
1299
1300 static QObject *pci_get_dev_class(const PCIDevice *dev)
1301 {
1302 int class;
1303 const pci_class_desc *desc;
1304
1305 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1306 desc = pci_class_descriptions;
1307 while (desc->desc && class != desc->class)
1308 desc++;
1309
1310 if (desc->desc) {
1311 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1312 desc->desc, class);
1313 } else {
1314 return qobject_from_jsonf("{ 'class': %d }", class);
1315 }
1316 }
1317
1318 static QObject *pci_get_dev_id(const PCIDevice *dev)
1319 {
1320 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1321 pci_get_word(dev->config + PCI_VENDOR_ID),
1322 pci_get_word(dev->config + PCI_DEVICE_ID));
1323 }
1324
1325 static QObject *pci_get_regions_list(const PCIDevice *dev)
1326 {
1327 int i;
1328 QList *regions_list;
1329
1330 regions_list = qlist_new();
1331
1332 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1333 QObject *obj;
1334 const PCIIORegion *r = &dev->io_regions[i];
1335
1336 if (!r->size) {
1337 continue;
1338 }
1339
1340 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1341 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1342 "'address': %" PRId64 ", "
1343 "'size': %" PRId64 " }",
1344 i, r->addr, r->size);
1345 } else {
1346 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1347
1348 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1349 "'mem_type_64': %i, 'prefetch': %i, "
1350 "'address': %" PRId64 ", "
1351 "'size': %" PRId64 " }",
1352 i, mem_type_64,
1353 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1354 r->addr, r->size);
1355 }
1356
1357 qlist_append_obj(regions_list, obj);
1358 }
1359
1360 return QOBJECT(regions_list);
1361 }
1362
1363 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1364
1365 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1366 {
1367 uint8_t type;
1368 QObject *obj;
1369
1370 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1371 " 'qdev_id': %s }",
1372 bus_num,
1373 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1374 pci_get_dev_class(dev), pci_get_dev_id(dev),
1375 pci_get_regions_list(dev),
1376 dev->qdev.id ? dev->qdev.id : "");
1377
1378 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1379 QDict *qdict = qobject_to_qdict(obj);
1380 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1381 }
1382
1383 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1384 if (type == PCI_HEADER_TYPE_BRIDGE) {
1385 QDict *qdict;
1386 QObject *pci_bridge;
1387
1388 pci_bridge = qobject_from_jsonf("{ 'bus': "
1389 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1390 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1391 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1392 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1393 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1394 dev->config[PCI_SUBORDINATE_BUS],
1395 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1396 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1397 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1398 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1399 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1400 PCI_BASE_ADDRESS_MEM_PREFETCH),
1401 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1402 PCI_BASE_ADDRESS_MEM_PREFETCH));
1403
1404 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1405 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1406
1407 if (child_bus) {
1408 qdict = qobject_to_qdict(pci_bridge);
1409 qdict_put_obj(qdict, "devices",
1410 pci_get_devices_list(child_bus,
1411 dev->config[PCI_SECONDARY_BUS]));
1412 }
1413 }
1414 qdict = qobject_to_qdict(obj);
1415 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1416 }
1417
1418 return obj;
1419 }
1420
1421 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1422 {
1423 int devfn;
1424 PCIDevice *dev;
1425 QList *dev_list;
1426
1427 dev_list = qlist_new();
1428
1429 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1430 dev = bus->devices[devfn];
1431 if (dev) {
1432 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1433 }
1434 }
1435
1436 return QOBJECT(dev_list);
1437 }
1438
1439 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1440 {
1441 bus = pci_find_bus(bus, bus_num);
1442 if (bus) {
1443 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1444 bus_num, pci_get_devices_list(bus, bus_num));
1445 }
1446
1447 return NULL;
1448 }
1449
1450 void do_pci_info(Monitor *mon, QObject **ret_data)
1451 {
1452 QList *bus_list;
1453 struct PCIHostBus *host;
1454
1455 bus_list = qlist_new();
1456
1457 QLIST_FOREACH(host, &host_buses, next) {
1458 QObject *obj = pci_get_bus_dict(host->bus, 0);
1459 if (obj) {
1460 qlist_append_obj(bus_list, obj);
1461 }
1462 }
1463
1464 *ret_data = QOBJECT(bus_list);
1465 }
1466
1467 static const char * const pci_nic_models[] = {
1468 "ne2k_pci",
1469 "i82551",
1470 "i82557b",
1471 "i82559er",
1472 "rtl8139",
1473 "e1000",
1474 "pcnet",
1475 "virtio",
1476 NULL
1477 };
1478
1479 static const char * const pci_nic_names[] = {
1480 "ne2k_pci",
1481 "i82551",
1482 "i82557b",
1483 "i82559er",
1484 "rtl8139",
1485 "e1000",
1486 "pcnet",
1487 "virtio-net-pci",
1488 NULL
1489 };
1490
1491 /* Initialize a PCI NIC. */
1492 /* FIXME callers should check for failure, but don't */
1493 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1494 const char *default_devaddr)
1495 {
1496 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1497 PCIBus *bus;
1498 int devfn;
1499 PCIDevice *pci_dev;
1500 DeviceState *dev;
1501 int i;
1502
1503 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1504 if (i < 0)
1505 return NULL;
1506
1507 bus = pci_get_bus_devfn(&devfn, devaddr);
1508 if (!bus) {
1509 error_report("Invalid PCI device address %s for device %s",
1510 devaddr, pci_nic_names[i]);
1511 return NULL;
1512 }
1513
1514 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1515 dev = &pci_dev->qdev;
1516 qdev_set_nic_properties(dev, nd);
1517 if (qdev_init(dev) < 0)
1518 return NULL;
1519 return pci_dev;
1520 }
1521
1522 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1523 const char *default_devaddr)
1524 {
1525 PCIDevice *res;
1526
1527 if (qemu_show_nic_models(nd->model, pci_nic_models))
1528 exit(0);
1529
1530 res = pci_nic_init(nd, default_model, default_devaddr);
1531 if (!res)
1532 exit(1);
1533 return res;
1534 }
1535
1536 typedef struct {
1537 PCIDevice dev;
1538 PCIBus bus;
1539 uint32_t vid;
1540 uint32_t did;
1541 } PCIBridge;
1542
1543
1544 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1545 {
1546 pci_update_mappings(d);
1547 }
1548
1549 static void pci_bridge_update_mappings(PCIBus *b)
1550 {
1551 PCIBus *child;
1552
1553 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1554
1555 QLIST_FOREACH(child, &b->child, sibling) {
1556 pci_bridge_update_mappings(child);
1557 }
1558 }
1559
1560 static void pci_bridge_write_config(PCIDevice *d,
1561 uint32_t address, uint32_t val, int len)
1562 {
1563 pci_default_write_config(d, address, val, len);
1564
1565 if (/* io base/limit */
1566 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1567
1568 /* memory base/limit, prefetchable base/limit and
1569 io base/limit upper 16 */
1570 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1571 PCIBridge *s = container_of(d, PCIBridge, dev);
1572 PCIBus *secondary_bus = &s->bus;
1573 pci_bridge_update_mappings(secondary_bus);
1574 }
1575 }
1576
1577 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1578 {
1579 PCIBus *sec;
1580
1581 if (!bus) {
1582 return NULL;
1583 }
1584
1585 if (pci_bus_num(bus) == bus_num) {
1586 return bus;
1587 }
1588
1589 /* try child bus */
1590 if (!bus->parent_dev /* host pci bridge */ ||
1591 (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1592 bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1593 for (; bus; bus = sec) {
1594 QLIST_FOREACH(sec, &bus->child, sibling) {
1595 assert(sec->parent_dev);
1596 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1597 return sec;
1598 }
1599 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1600 bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1601 break;
1602 }
1603 }
1604 }
1605 }
1606
1607 return NULL;
1608 }
1609
1610 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1611 {
1612 bus = pci_find_bus(bus, bus_num);
1613
1614 if (!bus)
1615 return NULL;
1616
1617 return bus->devices[PCI_DEVFN(slot, function)];
1618 }
1619
1620 static int pci_bridge_initfn(PCIDevice *dev)
1621 {
1622 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1623
1624 pci_config_set_vendor_id(s->dev.config, s->vid);
1625 pci_config_set_device_id(s->dev.config, s->did);
1626
1627 pci_set_word(dev->config + PCI_STATUS,
1628 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1629 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1630 dev->config[PCI_HEADER_TYPE] =
1631 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
1632 PCI_HEADER_TYPE_BRIDGE;
1633 pci_set_word(dev->config + PCI_SEC_STATUS,
1634 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1635 return 0;
1636 }
1637
1638 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1639 {
1640 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1641 PCIBus *bus = &s->bus;
1642 pci_unregister_secondary_bus(bus);
1643 return 0;
1644 }
1645
1646 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction,
1647 uint16_t vid, uint16_t did,
1648 pci_map_irq_fn map_irq, const char *name)
1649 {
1650 PCIDevice *dev;
1651 PCIBridge *s;
1652
1653 dev = pci_create_multifunction(bus, devfn, multifunction, "pci-bridge");
1654 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1655 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1656 qdev_init_nofail(&dev->qdev);
1657
1658 s = DO_UPCAST(PCIBridge, dev, dev);
1659 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1660 return &s->bus;
1661 }
1662
1663 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1664 {
1665 return bus->parent_dev;
1666 }
1667
1668 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1669 {
1670 PCIDevice *pci_dev = (PCIDevice *)qdev;
1671 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1672 PCIBus *bus;
1673 int devfn, rc;
1674
1675 /* initialize cap_present for pci_is_express() and pci_config_size() */
1676 if (info->is_express) {
1677 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1678 }
1679
1680 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1681 devfn = pci_dev->devfn;
1682 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1683 info->config_read, info->config_write,
1684 info->is_bridge);
1685 if (pci_dev == NULL)
1686 return -1;
1687 rc = info->init(pci_dev);
1688 if (rc != 0) {
1689 do_pci_unregister_device(pci_dev);
1690 return rc;
1691 }
1692
1693 /* rom loading */
1694 if (pci_dev->romfile == NULL && info->romfile != NULL)
1695 pci_dev->romfile = qemu_strdup(info->romfile);
1696 pci_add_option_rom(pci_dev);
1697
1698 if (qdev->hotplugged) {
1699 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1700 if (rc != 0) {
1701 int r = pci_unregister_device(&pci_dev->qdev);
1702 assert(!r);
1703 return rc;
1704 }
1705 }
1706 return 0;
1707 }
1708
1709 static int pci_unplug_device(DeviceState *qdev)
1710 {
1711 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1712
1713 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1714 }
1715
1716 void pci_qdev_register(PCIDeviceInfo *info)
1717 {
1718 info->qdev.init = pci_qdev_init;
1719 info->qdev.unplug = pci_unplug_device;
1720 info->qdev.exit = pci_unregister_device;
1721 info->qdev.bus_info = &pci_bus_info;
1722 qdev_register(&info->qdev);
1723 }
1724
1725 void pci_qdev_register_many(PCIDeviceInfo *info)
1726 {
1727 while (info->qdev.name) {
1728 pci_qdev_register(info);
1729 info++;
1730 }
1731 }
1732
1733 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1734 const char *name)
1735 {
1736 DeviceState *dev;
1737
1738 dev = qdev_create(&bus->qbus, name);
1739 qdev_prop_set_uint32(dev, "addr", devfn);
1740 qdev_prop_set_bit(dev, "multifunction", multifunction);
1741 return DO_UPCAST(PCIDevice, qdev, dev);
1742 }
1743
1744 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1745 bool multifunction,
1746 const char *name)
1747 {
1748 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1749 qdev_init_nofail(&dev->qdev);
1750 return dev;
1751 }
1752
1753 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1754 {
1755 return pci_create_multifunction(bus, devfn, false, name);
1756 }
1757
1758 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1759 {
1760 return pci_create_simple_multifunction(bus, devfn, false, name);
1761 }
1762
1763 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1764 {
1765 int config_size = pci_config_size(pdev);
1766 int offset = PCI_CONFIG_HEADER_SIZE;
1767 int i;
1768 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1769 if (pdev->used[i])
1770 offset = i + 1;
1771 else if (i - offset + 1 == size)
1772 return offset;
1773 return 0;
1774 }
1775
1776 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1777 uint8_t *prev_p)
1778 {
1779 uint8_t next, prev;
1780
1781 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1782 return 0;
1783
1784 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1785 prev = next + PCI_CAP_LIST_NEXT)
1786 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1787 break;
1788
1789 if (prev_p)
1790 *prev_p = prev;
1791 return next;
1792 }
1793
1794 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1795 {
1796 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1797 }
1798
1799 /* Add an option rom for the device */
1800 static int pci_add_option_rom(PCIDevice *pdev)
1801 {
1802 int size;
1803 char *path;
1804 void *ptr;
1805 char name[32];
1806
1807 if (!pdev->romfile)
1808 return 0;
1809 if (strlen(pdev->romfile) == 0)
1810 return 0;
1811
1812 if (!pdev->rom_bar) {
1813 /*
1814 * Load rom via fw_cfg instead of creating a rom bar,
1815 * for 0.11 compatibility.
1816 */
1817 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1818 if (class == 0x0300) {
1819 rom_add_vga(pdev->romfile);
1820 } else {
1821 rom_add_option(pdev->romfile);
1822 }
1823 return 0;
1824 }
1825
1826 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1827 if (path == NULL) {
1828 path = qemu_strdup(pdev->romfile);
1829 }
1830
1831 size = get_image_size(path);
1832 if (size < 0) {
1833 error_report("%s: failed to find romfile \"%s\"",
1834 __FUNCTION__, pdev->romfile);
1835 return -1;
1836 }
1837 if (size & (size - 1)) {
1838 size = 1 << qemu_fls(size);
1839 }
1840
1841 if (pdev->qdev.info->vmsd)
1842 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1843 else
1844 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1845 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1846
1847 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1848 load_image(path, ptr);
1849 qemu_free(path);
1850
1851 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1852 0, pci_map_option_rom);
1853
1854 return 0;
1855 }
1856
1857 static void pci_del_option_rom(PCIDevice *pdev)
1858 {
1859 if (!pdev->rom_offset)
1860 return;
1861
1862 qemu_ram_free(pdev->rom_offset);
1863 pdev->rom_offset = 0;
1864 }
1865
1866 /* Reserve space and add capability to the linked list in pci config space */
1867 int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1868 uint8_t offset, uint8_t size)
1869 {
1870 uint8_t *config = pdev->config + offset;
1871 config[PCI_CAP_LIST_ID] = cap_id;
1872 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1873 pdev->config[PCI_CAPABILITY_LIST] = offset;
1874 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1875 memset(pdev->used + offset, 0xFF, size);
1876 /* Make capability read-only by default */
1877 memset(pdev->wmask + offset, 0, size);
1878 /* Check capability by default */
1879 memset(pdev->cmask + offset, 0xFF, size);
1880 return offset;
1881 }
1882
1883 /* Find and reserve space and add capability to the linked list
1884 * in pci config space */
1885 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1886 {
1887 uint8_t offset = pci_find_space(pdev, size);
1888 if (!offset) {
1889 return -ENOSPC;
1890 }
1891 return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1892 }
1893
1894 /* Unlink capability from the pci config space. */
1895 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1896 {
1897 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1898 if (!offset)
1899 return;
1900 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1901 /* Make capability writeable again */
1902 memset(pdev->wmask + offset, 0xff, size);
1903 /* Clear cmask as device-specific registers can't be checked */
1904 memset(pdev->cmask + offset, 0, size);
1905 memset(pdev->used + offset, 0, size);
1906
1907 if (!pdev->config[PCI_CAPABILITY_LIST])
1908 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1909 }
1910
1911 /* Reserve space for capability at a known offset (to call after load). */
1912 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1913 {
1914 memset(pdev->used + offset, 0xff, size);
1915 }
1916
1917 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1918 {
1919 return pci_find_capability_list(pdev, cap_id, NULL);
1920 }
1921
1922 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1923 {
1924 PCIDevice *d = (PCIDevice *)dev;
1925 const pci_class_desc *desc;
1926 char ctxt[64];
1927 PCIIORegion *r;
1928 int i, class;
1929
1930 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1931 desc = pci_class_descriptions;
1932 while (desc->desc && class != desc->class)
1933 desc++;
1934 if (desc->desc) {
1935 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1936 } else {
1937 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1938 }
1939
1940 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1941 "pci id %04x:%04x (sub %04x:%04x)\n",
1942 indent, "", ctxt,
1943 d->config[PCI_SECONDARY_BUS],
1944 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1945 pci_get_word(d->config + PCI_VENDOR_ID),
1946 pci_get_word(d->config + PCI_DEVICE_ID),
1947 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1948 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1949 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1950 r = &d->io_regions[i];
1951 if (!r->size)
1952 continue;
1953 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1954 " [0x%"FMT_PCIBUS"]\n",
1955 indent, "",
1956 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1957 r->addr, r->addr + r->size - 1);
1958 }
1959 }
1960
1961 static char *pcibus_get_dev_path(DeviceState *dev)
1962 {
1963 PCIDevice *d = (PCIDevice *)dev;
1964 char path[16];
1965
1966 snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1967 pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1968 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1969
1970 return strdup(path);
1971 }
1972
1973 static PCIDeviceInfo bridge_info = {
1974 .qdev.name = "pci-bridge",
1975 .qdev.size = sizeof(PCIBridge),
1976 .init = pci_bridge_initfn,
1977 .exit = pci_bridge_exitfn,
1978 .config_write = pci_bridge_write_config,
1979 .is_bridge = 1,
1980 .qdev.props = (Property[]) {
1981 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1982 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1983 DEFINE_PROP_END_OF_LIST(),
1984 }
1985 };
1986
1987 static void pci_register_devices(void)
1988 {
1989 pci_qdev_register(&bridge_info);
1990 }
1991
1992 device_init(pci_register_devices)
Stefan Hajnoczi's patches