hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     uint64_t hpet_offset;
  63     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  64     uint32_t flags;
  65     uint8_t rtc_irq_level;
  66     uint8_t num_timers;
  67     HPETTimer timer[HPET_MAX_TIMERS];
  68
  69     /* Memory-mapped, software visible registers */
  70     uint64_t capability;        /* capabilities */
  71     uint64_t config;            /* configuration */
  72     uint64_t isr;               /* interrupt status reg */
  73     uint64_t hpet_counter;      /* main counter */
  74     uint8_t  hpet_id;           /* instance id */
  75 } HPETState;
  76
  77 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  78
  79 static uint32_t hpet_in_legacy_mode(HPETState *s)
  80 {
  81     return s->config & HPET_CFG_LEGACY;
  82 }
  83
  84 static uint32_t timer_int_route(struct HPETTimer *timer)
  85 {
  86     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  87 }
  88
  89 static uint32_t timer_fsb_route(HPETTimer *t)
  90 {
  91     return t->config & HPET_TN_FSB_ENABLE;
  92 }
  93
  94 static uint32_t hpet_enabled(HPETState *s)
  95 {
  96     return s->config & HPET_CFG_ENABLE;
  97 }
  98
  99 static uint32_t timer_is_periodic(HPETTimer *t)
 100 {
 101     return t->config & HPET_TN_PERIODIC;
 102 }
 103
 104 static uint32_t timer_enabled(HPETTimer *t)
 105 {
 106     return t->config & HPET_TN_ENABLE;
 107 }
 108
 109 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 110 {
 111     return ((int32_t)(b) - (int32_t)(a) < 0);
 112 }
 113
 114 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 115 {
 116     return ((int64_t)(b) - (int64_t)(a) < 0);
 117 }
 118
 119 static uint64_t ticks_to_ns(uint64_t value)
 120 {
 121     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 122 }
 123
 124 static uint64_t ns_to_ticks(uint64_t value)
 125 {
 126     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 127 }
 128
 129 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 130 {
 131     new &= mask;
 132     new |= old & ~mask;
 133     return new;
 134 }
 135
 136 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 137 {
 138     return (!(old & mask) && (new & mask));
 139 }
 140
 141 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 142 {
 143     return ((old & mask) && !(new & mask));
 144 }
 145
 146 static uint64_t hpet_get_ticks(HPETState *s)
 147 {
 148     return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
 149 }
 150
 151 /*
 152  * calculate diff between comparator value and current ticks
 153  */
 154 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 155 {
 156
 157     if (t->config & HPET_TN_32BIT) {
 158         uint32_t diff, cmp;
 159
 160         cmp = (uint32_t)t->cmp;
 161         diff = cmp - (uint32_t)current;
 162         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 163         return (uint64_t)diff;
 164     } else {
 165         uint64_t diff, cmp;
 166
 167         cmp = t->cmp;
 168         diff = cmp - current;
 169         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 170         return diff;
 171     }
 172 }
 173
 174 static void update_irq(struct HPETTimer *timer, int set)
 175 {
 176     uint64_t mask;
 177     HPETState *s;
 178     int route;
 179
 180     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 181         /* if LegacyReplacementRoute bit is set, HPET specification requires
 182          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 183          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 184          */
 185         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 186     } else {
 187         route = timer_int_route(timer);
 188     }
 189     s = timer->state;
 190     mask = 1 << timer->tn;
 191     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 192         s->isr &= ~mask;
 193         if (!timer_fsb_route(timer)) {
 194             qemu_irq_lower(s->irqs[route]);
 195         }
 196     } else if (timer_fsb_route(timer)) {
 197         stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 198     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 199         s->isr |= mask;
 200         qemu_irq_raise(s->irqs[route]);
 201     } else {
 202         s->isr &= ~mask;
 203         qemu_irq_pulse(s->irqs[route]);
 204     }
 205 }
 206
 207 static void hpet_pre_save(void *opaque)
 208 {
 209     HPETState *s = opaque;
 210
 211     /* save current counter value */
 212     s->hpet_counter = hpet_get_ticks(s);
 213 }
 214
 215 static int hpet_pre_load(void *opaque)
 216 {
 217     HPETState *s = opaque;
 218
 219     /* version 1 only supports 3, later versions will load the actual value */
 220     s->num_timers = HPET_MIN_TIMERS;
 221     return 0;
 222 }
 223
 224 static int hpet_post_load(void *opaque, int version_id)
 225 {
 226     HPETState *s = opaque;
 227
 228     /* Recalculate the offset between the main counter and guest time */
 229     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 230
 231     /* Push number of timers into capability returned via HPET_ID */
 232     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 233     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 234     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 235
 236     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 237     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 238     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 239         s->flags |= 1 << HPET_MSI_SUPPORT;
 240     }
 241     return 0;
 242 }
 243
 244 static const VMStateDescription vmstate_hpet_timer = {
 245     .name = "hpet_timer",
 246     .version_id = 1,
 247     .minimum_version_id = 1,
 248     .minimum_version_id_old = 1,
 249     .fields      = (VMStateField []) {
 250         VMSTATE_UINT8(tn, HPETTimer),
 251         VMSTATE_UINT64(config, HPETTimer),
 252         VMSTATE_UINT64(cmp, HPETTimer),
 253         VMSTATE_UINT64(fsb, HPETTimer),
 254         VMSTATE_UINT64(period, HPETTimer),
 255         VMSTATE_UINT8(wrap_flag, HPETTimer),
 256         VMSTATE_TIMER(qemu_timer, HPETTimer),
 257         VMSTATE_END_OF_LIST()
 258     }
 259 };
 260
 261 static const VMStateDescription vmstate_hpet = {
 262     .name = "hpet",
 263     .version_id = 2,
 264     .minimum_version_id = 1,
 265     .minimum_version_id_old = 1,
 266     .pre_save = hpet_pre_save,
 267     .pre_load = hpet_pre_load,
 268     .post_load = hpet_post_load,
 269     .fields      = (VMStateField []) {
 270         VMSTATE_UINT64(config, HPETState),
 271         VMSTATE_UINT64(isr, HPETState),
 272         VMSTATE_UINT64(hpet_counter, HPETState),
 273         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 274         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 275                                     vmstate_hpet_timer, HPETTimer),
 276         VMSTATE_END_OF_LIST()
 277     }
 278 };
 279
 280 /*
 281  * timer expiration callback
 282  */
 283 static void hpet_timer(void *opaque)
 284 {
 285     HPETTimer *t = opaque;
 286     uint64_t diff;
 287
 288     uint64_t period = t->period;
 289     uint64_t cur_tick = hpet_get_ticks(t->state);
 290
 291     if (timer_is_periodic(t) && period != 0) {
 292         if (t->config & HPET_TN_32BIT) {
 293             while (hpet_time_after(cur_tick, t->cmp)) {
 294                 t->cmp = (uint32_t)(t->cmp + t->period);
 295             }
 296         } else {
 297             while (hpet_time_after64(cur_tick, t->cmp)) {
 298                 t->cmp += period;
 299             }
 300         }
 301         diff = hpet_calculate_diff(t, cur_tick);
 302         qemu_mod_timer(t->qemu_timer,
 303                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 304     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 305         if (t->wrap_flag) {
 306             diff = hpet_calculate_diff(t, cur_tick);
 307             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 308                            (int64_t)ticks_to_ns(diff));
 309             t->wrap_flag = 0;
 310         }
 311     }
 312     update_irq(t, 1);
 313 }
 314
 315 static void hpet_set_timer(HPETTimer *t)
 316 {
 317     uint64_t diff;
 318     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 319     uint64_t cur_tick = hpet_get_ticks(t->state);
 320
 321     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 322     t->wrap_flag = 0;
 323     diff = hpet_calculate_diff(t, cur_tick);
 324
 325     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 326      * counter wraps in addition to an interrupt with comparator match.
 327      */
 328     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 329         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 330         if (wrap_diff < (uint32_t)diff) {
 331             diff = wrap_diff;
 332             t->wrap_flag = 1;
 333         }
 334     }
 335     qemu_mod_timer(t->qemu_timer,
 336                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 337 }
 338
 339 static void hpet_del_timer(HPETTimer *t)
 340 {
 341     qemu_del_timer(t->qemu_timer);
 342     update_irq(t, 0);
 343 }
 344
 345 #ifdef HPET_DEBUG
 346 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 347 {
 348     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 349     return 0;
 350 }
 351
 352 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 353 {
 354     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 355     return 0;
 356 }
 357 #endif
 358
 359 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 360 {
 361     HPETState *s = opaque;
 362     uint64_t cur_tick, index;
 363
 364     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 365     index = addr;
 366     /*address range of all TN regs*/
 367     if (index >= 0x100 && index <= 0x3ff) {
 368         uint8_t timer_id = (addr - 0x100) / 0x20;
 369         HPETTimer *timer = &s->timer[timer_id];
 370
 371         if (timer_id > s->num_timers) {
 372             DPRINTF("qemu: timer id out of range\n");
 373             return 0;
 374         }
 375
 376         switch ((addr - 0x100) % 0x20) {
 377         case HPET_TN_CFG:
 378             return timer->config;
 379         case HPET_TN_CFG + 4: // Interrupt capabilities
 380             return timer->config >> 32;
 381         case HPET_TN_CMP: // comparator register
 382             return timer->cmp;
 383         case HPET_TN_CMP + 4:
 384             return timer->cmp >> 32;
 385         case HPET_TN_ROUTE:
 386             return timer->fsb;
 387         case HPET_TN_ROUTE + 4:
 388             return timer->fsb >> 32;
 389         default:
 390             DPRINTF("qemu: invalid hpet_ram_readl\n");
 391             break;
 392         }
 393     } else {
 394         switch (index) {
 395         case HPET_ID:
 396             return s->capability;
 397         case HPET_PERIOD:
 398             return s->capability >> 32;
 399         case HPET_CFG:
 400             return s->config;
 401         case HPET_CFG + 4:
 402             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 403             return 0;
 404         case HPET_COUNTER:
 405             if (hpet_enabled(s)) {
 406                 cur_tick = hpet_get_ticks(s);
 407             } else {
 408                 cur_tick = s->hpet_counter;
 409             }
 410             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 411             return cur_tick;
 412         case HPET_COUNTER + 4:
 413             if (hpet_enabled(s)) {
 414                 cur_tick = hpet_get_ticks(s);
 415             } else {
 416                 cur_tick = s->hpet_counter;
 417             }
 418             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 419             return cur_tick >> 32;
 420         case HPET_STATUS:
 421             return s->isr;
 422         default:
 423             DPRINTF("qemu: invalid hpet_ram_readl\n");
 424             break;
 425         }
 426     }
 427     return 0;
 428 }
 429
 430 #ifdef HPET_DEBUG
 431 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 432                             uint32_t value)
 433 {
 434     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 435            addr, value);
 436 }
 437
 438 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 439                             uint32_t value)
 440 {
 441     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 442            addr, value);
 443 }
 444 #endif
 445
 446 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 447                             uint32_t value)
 448 {
 449     int i;
 450     HPETState *s = opaque;
 451     uint64_t old_val, new_val, val, index;
 452
 453     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 454     index = addr;
 455     old_val = hpet_ram_readl(opaque, addr);
 456     new_val = value;
 457
 458     /*address range of all TN regs*/
 459     if (index >= 0x100 && index <= 0x3ff) {
 460         uint8_t timer_id = (addr - 0x100) / 0x20;
 461         HPETTimer *timer = &s->timer[timer_id];
 462
 463         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 464         if (timer_id > s->num_timers) {
 465             DPRINTF("qemu: timer id out of range\n");
 466             return;
 467         }
 468         switch ((addr - 0x100) % 0x20) {
 469         case HPET_TN_CFG:
 470             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 471             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 472                 update_irq(timer, 0);
 473             }
 474             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 475             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 476             if (new_val & HPET_TN_32BIT) {
 477                 timer->cmp = (uint32_t)timer->cmp;
 478                 timer->period = (uint32_t)timer->period;
 479             }
 480             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 481                 hpet_set_timer(timer);
 482             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 483                 hpet_del_timer(timer);
 484             }
 485             break;
 486         case HPET_TN_CFG + 4: // Interrupt capabilities
 487             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 488             break;
 489         case HPET_TN_CMP: // comparator register
 490             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 491             if (timer->config & HPET_TN_32BIT) {
 492                 new_val = (uint32_t)new_val;
 493             }
 494             if (!timer_is_periodic(timer)
 495                 || (timer->config & HPET_TN_SETVAL)) {
 496                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 497             }
 498             if (timer_is_periodic(timer)) {
 499                 /*
 500                  * FIXME: Clamp period to reasonable min value?
 501                  * Clamp period to reasonable max value
 502                  */
 503                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 504                 timer->period =
 505                     (timer->period & 0xffffffff00000000ULL) | new_val;
 506             }
 507             timer->config &= ~HPET_TN_SETVAL;
 508             if (hpet_enabled(s)) {
 509                 hpet_set_timer(timer);
 510             }
 511             break;
 512         case HPET_TN_CMP + 4: // comparator register high order
 513             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 514             if (!timer_is_periodic(timer)
 515                 || (timer->config & HPET_TN_SETVAL)) {
 516                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 517             } else {
 518                 /*
 519                  * FIXME: Clamp period to reasonable min value?
 520                  * Clamp period to reasonable max value
 521                  */
 522                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 523                 timer->period =
 524                     (timer->period & 0xffffffffULL) | new_val << 32;
 525                 }
 526                 timer->config &= ~HPET_TN_SETVAL;
 527                 if (hpet_enabled(s)) {
 528                     hpet_set_timer(timer);
 529                 }
 530                 break;
 531         case HPET_TN_ROUTE:
 532             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 533             break;
 534         case HPET_TN_ROUTE + 4:
 535             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 536             break;
 537         default:
 538             DPRINTF("qemu: invalid hpet_ram_writel\n");
 539             break;
 540         }
 541         return;
 542     } else {
 543         switch (index) {
 544         case HPET_ID:
 545             return;
 546         case HPET_CFG:
 547             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 548             s->config = (s->config & 0xffffffff00000000ULL) | val;
 549             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 550                 /* Enable main counter and interrupt generation. */
 551                 s->hpet_offset =
 552                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 553                 for (i = 0; i < s->num_timers; i++) {
 554                     if ((&s->timer[i])->cmp != ~0ULL) {
 555                         hpet_set_timer(&s->timer[i]);
 556                     }
 557                 }
 558             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 559                 /* Halt main counter and disable interrupt generation. */
 560                 s->hpet_counter = hpet_get_ticks(s);
 561                 for (i = 0; i < s->num_timers; i++) {
 562                     hpet_del_timer(&s->timer[i]);
 563                 }
 564             }
 565             /* i8254 and RTC are disabled when HPET is in legacy mode */
 566             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 567                 hpet_pit_disable();
 568                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 569             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 570                 hpet_pit_enable();
 571                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 572             }
 573             break;
 574         case HPET_CFG + 4:
 575             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 576             break;
 577         case HPET_STATUS:
 578             val = new_val & s->isr;
 579             for (i = 0; i < s->num_timers; i++) {
 580                 if (val & (1 << i)) {
 581                     update_irq(&s->timer[i], 0);
 582                 }
 583             }
 584             break;
 585         case HPET_COUNTER:
 586             if (hpet_enabled(s)) {
 587                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 588             }
 589             s->hpet_counter =
 590                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 591             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 592                     value, s->hpet_counter);
 593             break;
 594         case HPET_COUNTER + 4:
 595             if (hpet_enabled(s)) {
 596                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 597             }
 598             s->hpet_counter =
 599                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 600             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 601                     value, s->hpet_counter);
 602             break;
 603         default:
 604             DPRINTF("qemu: invalid hpet_ram_writel\n");
 605             break;
 606         }
 607     }
 608 }
 609
 610 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 611 #ifdef HPET_DEBUG
 612     hpet_ram_readb,
 613     hpet_ram_readw,
 614 #else
 615     NULL,
 616     NULL,
 617 #endif
 618     hpet_ram_readl,
 619 };
 620
 621 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 622 #ifdef HPET_DEBUG
 623     hpet_ram_writeb,
 624     hpet_ram_writew,
 625 #else
 626     NULL,
 627     NULL,
 628 #endif
 629     hpet_ram_writel,
 630 };
 631
 632 static void hpet_reset(DeviceState *d)
 633 {
 634     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 635     int i;
 636     static int count = 0;
 637
 638     for (i = 0; i < s->num_timers; i++) {
 639         HPETTimer *timer = &s->timer[i];
 640
 641         hpet_del_timer(timer);
 642         timer->cmp = ~0ULL;
 643         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 644         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 645             timer->config |= HPET_TN_FSB_CAP;
 646         }
 647         /* advertise availability of ioapic inti2 */
 648         timer->config |=  0x00000004ULL << 32;
 649         timer->period = 0ULL;
 650         timer->wrap_flag = 0;
 651     }
 652
 653     s->hpet_counter = 0ULL;
 654     s->hpet_offset = 0ULL;
 655     s->config = 0ULL;
 656     if (count > 0) {
 657         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 658          * because hpet is taking over for pit here. On subsequent invocations,
 659          * hpet_reset is called due to system reset. At this point control must
 660          * be returned to pit until SW reenables hpet.
 661          */
 662         hpet_pit_enable();
 663     }
 664     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 665     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 666     count = 1;
 667 }
 668
 669 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 670 {
 671     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 672
 673     s->rtc_irq_level = level;
 674     if (!hpet_in_legacy_mode(s)) {
 675         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 676     }
 677 }
 678
 679 static int hpet_init(SysBusDevice *dev)
 680 {
 681     HPETState *s = FROM_SYSBUS(HPETState, dev);
 682     int i, iomemtype;
 683     HPETTimer *timer;
 684
 685     if (hpet_cfg.count == UINT8_MAX) {
 686         /* first instance */
 687         hpet_cfg.count = 0;
 688     }
 689
 690     if (hpet_cfg.count == 8) {
 691         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 692         return -1;
 693     }
 694
 695     s->hpet_id = hpet_cfg.count++;
 696
 697     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 698         sysbus_init_irq(dev, &s->irqs[i]);
 699     }
 700
 701     if (s->num_timers < HPET_MIN_TIMERS) {
 702         s->num_timers = HPET_MIN_TIMERS;
 703     } else if (s->num_timers > HPET_MAX_TIMERS) {
 704         s->num_timers = HPET_MAX_TIMERS;
 705     }
 706     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 707         timer = &s->timer[i];
 708         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 709         timer->tn = i;
 710         timer->state = s;
 711     }
 712
 713     /* 64-bit main counter; LegacyReplacementRoute. */
 714     s->capability = 0x8086a001ULL;
 715     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 716     s->capability |= ((HPET_CLK_PERIOD) << 32);
 717
 718     isa_reserve_irq(RTC_ISA_IRQ);
 719     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 720
 721     /* HPET Area */
 722     iomemtype = cpu_register_io_memory(hpet_ram_read,
 723                                        hpet_ram_write, s);
 724     sysbus_init_mmio(dev, 0x400, iomemtype);
 725     return 0;
 726 }
 727
 728 static SysBusDeviceInfo hpet_device_info = {
 729     .qdev.name    = "hpet",
 730     .qdev.size    = sizeof(HPETState),
 731     .qdev.no_user = 1,
 732     .qdev.vmsd    = &vmstate_hpet,
 733     .qdev.reset   = hpet_reset,
 734     .init         = hpet_init,
 735     .qdev.props = (Property[]) {
 736         DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 737         DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 738         DEFINE_PROP_END_OF_LIST(),
 739     },
 740 };
 741
 742 static void hpet_register_device(void)
 743 {
 744     sysbus_register_withprop(&hpet_device_info);
 745 }
 746
 747 device_init(hpet_register_device)