hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 #include "pcie.h"
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19 #define PCI_FUNC_MAX            8
  20
  21 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  22 #include "pci_ids.h"
  23
  24 /* QEMU-specific Vendor and Device ID definitions */
  25
  26 /* IBM (0x1014) */
  27 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  28 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  29
  30 /* Hitachi (0x1054) */
  31 #define PCI_VENDOR_ID_HITACHI            0x1054
  32 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  33
  34 /* Apple (0x106b) */
  35 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  39 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  40
  41 /* Realtek (0x10ec) */
  42 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  43
  44 /* Xilinx (0x10ee) */
  45 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  46
  47 /* Marvell (0x11ab) */
  48 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  49
  50 /* QEMU/Bochs VGA (0x1234) */
  51 #define PCI_VENDOR_ID_QEMU               0x1234
  52 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  53
  54 /* VMWare (0x15ad) */
  55 #define PCI_VENDOR_ID_VMWARE             0x15ad
  56 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  57 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  58 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  59 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  60 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  61
  62 /* Intel (0x8086) */
  63 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  64 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  65 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  66
  67 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  68 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  69 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  70 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  71
  72 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  73 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  74 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  75 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  76
  77 #define FMT_PCIBUS                      PRIx64
  78
  79 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  80                                 uint32_t address, uint32_t data, int len);
  81 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  82                                    uint32_t address, int len);
  83 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  84                                 pcibus_t addr, pcibus_t size, int type);
  85 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  86
  87 typedef struct PCIIORegion {
  88     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  89 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  90     pcibus_t size;
  91     pcibus_t filtered_size;
  92     uint8_t type;
  93     PCIMapIORegionFunc *map_func;
  94 } PCIIORegion;
  95
  96 #define PCI_ROM_SLOT 6
  97 #define PCI_NUM_REGIONS 7
  98
  99 #include "pci_regs.h"
 100
 101 /* PCI HEADER_TYPE */
 102 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 103
 104 /* Size of the standard PCI config header */
 105 #define PCI_CONFIG_HEADER_SIZE 0x40
 106 /* Size of the standard PCI config space */
 107 #define PCI_CONFIG_SPACE_SIZE 0x100
 108 /* Size of the standart PCIe config space: 4KB */
 109 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 110
 111 #define PCI_NUM_PINS 4 /* A-D */
 112
 113 /* Bits in cap_present field. */
 114 enum {
 115     QEMU_PCI_CAP_MSI = 0x1,
 116     QEMU_PCI_CAP_MSIX = 0x2,
 117     QEMU_PCI_CAP_EXPRESS = 0x4,
 118
 119     /* multifunction capable device */
 120 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 121     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 122
 123     /* command register SERR bit enabled */
 124 #define QEMU_PCI_CAP_SERR_BITNR 4
 125     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 126 };
 127
 128 struct PCIDevice {
 129     DeviceState qdev;
 130     /* PCI config space */
 131     uint8_t *config;
 132
 133     /* Used to enable config checks on load. Note that writeable bits are
 134      * never checked even if set in cmask. */
 135     uint8_t *cmask;
 136
 137     /* Used to implement R/W bytes */
 138     uint8_t *wmask;
 139
 140     /* Used to implement RW1C(Write 1 to Clear) bytes */
 141     uint8_t *w1cmask;
 142
 143     /* Used to allocate config space for capabilities. */
 144     uint8_t *used;
 145
 146     /* the following fields are read only */
 147     PCIBus *bus;
 148     uint32_t devfn;
 149     char name[64];
 150     PCIIORegion io_regions[PCI_NUM_REGIONS];
 151
 152     /* do not access the following fields */
 153     PCIConfigReadFunc *config_read;
 154     PCIConfigWriteFunc *config_write;
 155
 156     /* IRQ objects for the INTA-INTD pins.  */
 157     qemu_irq *irq;
 158
 159     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 160     uint8_t irq_state;
 161
 162     /* Capability bits */
 163     uint32_t cap_present;
 164
 165     /* Offset of MSI-X capability in config space */
 166     uint8_t msix_cap;
 167
 168     /* MSI-X entries */
 169     int msix_entries_nr;
 170
 171     /* Space to store MSIX table */
 172     uint8_t *msix_table_page;
 173     /* MMIO index used to map MSIX table and pending bit entries. */
 174     int msix_mmio_index;
 175     /* Reference-count for entries actually in use by driver. */
 176     unsigned *msix_entry_used;
 177     /* Region including the MSI-X table */
 178     uint32_t msix_bar_size;
 179     /* Version id needed for VMState */
 180     int32_t version_id;
 181
 182     /* Offset of MSI capability in config space */
 183     uint8_t msi_cap;
 184
 185     /* PCI Express */
 186     PCIExpressDevice exp;
 187
 188     /* Location of option rom */
 189     char *romfile;
 190     ram_addr_t rom_offset;
 191     uint32_t rom_bar;
 192 };
 193
 194 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 195                                int instance_size, int devfn,
 196                                PCIConfigReadFunc *config_read,
 197                                PCIConfigWriteFunc *config_write);
 198
 199 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 200                             pcibus_t size, uint8_t type,
 201                             PCIMapIORegionFunc *map_func);
 202
 203 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 204                        uint8_t offset, uint8_t size);
 205
 206 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 207
 208 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 209
 210 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 211
 212
 213 uint32_t pci_default_read_config(PCIDevice *d,
 214                                  uint32_t address, int len);
 215 void pci_default_write_config(PCIDevice *d,
 216                               uint32_t address, uint32_t val, int len);
 217 void pci_device_save(PCIDevice *s, QEMUFile *f);
 218 int pci_device_load(PCIDevice *s, QEMUFile *f);
 219
 220 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 221 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 222
 223 typedef enum {
 224     PCI_HOTPLUG_DISABLED,
 225     PCI_HOTPLUG_ENABLED,
 226     PCI_COLDPLUG_ENABLED,
 227 } PCIHotplugState;
 228
 229 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 230                               PCIHotplugState state);
 231 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 232                          const char *name, int devfn_min);
 233 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 234 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 235                   void *irq_opaque, int nirq);
 236 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 237 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 238                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 239                          void *irq_opaque, int devfn_min, int nirq);
 240 void pci_bus_reset(PCIBus *bus);
 241
 242 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 243
 244 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 245                         const char *default_devaddr);
 246 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 247                                const char *default_devaddr);
 248 int pci_bus_num(PCIBus *s);
 249 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 250 PCIBus *pci_find_root_bus(int domain);
 251 int pci_find_domain(const PCIBus *bus);
 252 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 253 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 254 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 255
 256 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 257                       unsigned int *slotp, unsigned int *funcp);
 258 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 259                      unsigned *slotp);
 260
 261 void do_pci_info_print(Monitor *mon, const QObject *data);
 262 void do_pci_info(Monitor *mon, QObject **ret_data);
 263 void pci_bridge_update_mappings(PCIBus *b);
 264
 265 static inline void
 266 pci_set_byte(uint8_t *config, uint8_t val)
 267 {
 268     *config = val;
 269 }
 270
 271 static inline uint8_t
 272 pci_get_byte(const uint8_t *config)
 273 {
 274     return *config;
 275 }
 276
 277 static inline void
 278 pci_set_word(uint8_t *config, uint16_t val)
 279 {
 280     cpu_to_le16wu((uint16_t *)config, val);
 281 }
 282
 283 static inline uint16_t
 284 pci_get_word(const uint8_t *config)
 285 {
 286     return le16_to_cpupu((const uint16_t *)config);
 287 }
 288
 289 static inline void
 290 pci_set_long(uint8_t *config, uint32_t val)
 291 {
 292     cpu_to_le32wu((uint32_t *)config, val);
 293 }
 294
 295 static inline uint32_t
 296 pci_get_long(const uint8_t *config)
 297 {
 298     return le32_to_cpupu((const uint32_t *)config);
 299 }
 300
 301 static inline void
 302 pci_set_quad(uint8_t *config, uint64_t val)
 303 {
 304     cpu_to_le64w((uint64_t *)config, val);
 305 }
 306
 307 static inline uint64_t
 308 pci_get_quad(const uint8_t *config)
 309 {
 310     return le64_to_cpup((const uint64_t *)config);
 311 }
 312
 313 static inline void
 314 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 315 {
 316     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 317 }
 318
 319 static inline void
 320 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 321 {
 322     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 323 }
 324
 325 static inline void
 326 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 327 {
 328     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 329 }
 330
 331 static inline void
 332 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 333 {
 334     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 335 }
 336
 337 static inline void
 338 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 339 {
 340     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 341 }
 342
 343 static inline void
 344 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 345 {
 346     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 347 }
 348
 349 /*
 350  * helper functions to do bit mask operation on configuration space.
 351  * Just to set bit, use test-and-set and discard returned value.
 352  * Just to clear bit, use test-and-clear and discard returned value.
 353  * NOTE: They aren't atomic.
 354  */
 355 static inline uint8_t
 356 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 357 {
 358     uint8_t val = pci_get_byte(config);
 359     pci_set_byte(config, val & ~mask);
 360     return val & mask;
 361 }
 362
 363 static inline uint8_t
 364 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 365 {
 366     uint8_t val = pci_get_byte(config);
 367     pci_set_byte(config, val | mask);
 368     return val & mask;
 369 }
 370
 371 static inline uint16_t
 372 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 373 {
 374     uint16_t val = pci_get_word(config);
 375     pci_set_word(config, val & ~mask);
 376     return val & mask;
 377 }
 378
 379 static inline uint16_t
 380 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 381 {
 382     uint16_t val = pci_get_word(config);
 383     pci_set_word(config, val | mask);
 384     return val & mask;
 385 }
 386
 387 static inline uint32_t
 388 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 389 {
 390     uint32_t val = pci_get_long(config);
 391     pci_set_long(config, val & ~mask);
 392     return val & mask;
 393 }
 394
 395 static inline uint32_t
 396 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 397 {
 398     uint32_t val = pci_get_long(config);
 399     pci_set_long(config, val | mask);
 400     return val & mask;
 401 }
 402
 403 static inline uint64_t
 404 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 405 {
 406     uint64_t val = pci_get_quad(config);
 407     pci_set_quad(config, val & ~mask);
 408     return val & mask;
 409 }
 410
 411 static inline uint64_t
 412 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 413 {
 414     uint64_t val = pci_get_quad(config);
 415     pci_set_quad(config, val | mask);
 416     return val & mask;
 417 }
 418
 419 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 420 typedef struct {
 421     DeviceInfo qdev;
 422     pci_qdev_initfn init;
 423     PCIUnregisterFunc *exit;
 424     PCIConfigReadFunc *config_read;
 425     PCIConfigWriteFunc *config_write;
 426
 427     /*
 428      * pci-to-pci bridge or normal device.
 429      * This doesn't mean pci host switch.
 430      * When card bus bridge is supported, this would be enhanced.
 431      */
 432     int is_bridge;
 433
 434     /* pcie stuff */
 435     int is_express;   /* is this device pci express? */
 436
 437     /* rom bar */
 438     const char *romfile;
 439 } PCIDeviceInfo;
 440
 441 void pci_qdev_register(PCIDeviceInfo *info);
 442 void pci_qdev_register_many(PCIDeviceInfo *info);
 443
 444 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 445                                     const char *name);
 446 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 447                                            bool multifunction,
 448                                            const char *name);
 449 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 450 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 451
 452 static inline int pci_is_express(const PCIDevice *d)
 453 {
 454     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 455 }
 456
 457 static inline uint32_t pci_config_size(const PCIDevice *d)
 458 {
 459     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 460 }
 461
 462 #endif