coroutine: add test-coroutine --benchmark-lifecycle
[qemu/stefanha.git] / hw / prep_pci.c
blobf88b8254c2749d47036b70938173a4f88c5a748c
1 /*
2 * QEMU PREP PCI host
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "hw.h"
26 #include "pci.h"
27 #include "pci_host.h"
28 #include "prep_pci.h"
30 typedef PCIHostState PREPPCIState;
32 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
34 int i;
36 for(i = 0; i < 11; i++) {
37 if ((addr & (1 << (11 + i))) != 0)
38 break;
40 return (addr & 0x7ff) | (i << 11);
43 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
45 PREPPCIState *s = opaque;
46 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
49 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
51 PREPPCIState *s = opaque;
52 val = bswap16(val);
53 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
56 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
58 PREPPCIState *s = opaque;
59 val = bswap32(val);
60 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
63 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
65 PREPPCIState *s = opaque;
66 uint32_t val;
67 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
68 return val;
71 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
73 PREPPCIState *s = opaque;
74 uint32_t val;
75 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
76 val = bswap16(val);
77 return val;
80 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
82 PREPPCIState *s = opaque;
83 uint32_t val;
84 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
85 val = bswap32(val);
86 return val;
89 static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
90 &PPC_PCIIO_writeb,
91 &PPC_PCIIO_writew,
92 &PPC_PCIIO_writel,
95 static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
96 &PPC_PCIIO_readb,
97 &PPC_PCIIO_readw,
98 &PPC_PCIIO_readl,
101 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
103 return (irq_num + (pci_dev->devfn >> 3)) & 1;
106 static void prep_set_irq(void *opaque, int irq_num, int level)
108 qemu_irq *pic = opaque;
110 qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
113 PCIBus *pci_prep_init(qemu_irq *pic)
115 PREPPCIState *s;
116 PCIDevice *d;
117 int PPC_io_memory;
119 s = qemu_mallocz(sizeof(PREPPCIState));
120 s->bus = pci_register_bus(NULL, "pci",
121 prep_set_irq, prep_map_irq, pic, 0, 4);
123 pci_host_conf_register_ioport(0xcf8, s);
125 pci_host_data_register_ioport(0xcfc, s);
127 PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
128 PPC_PCIIO_write, s,
129 DEVICE_NATIVE_ENDIAN);
130 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
132 /* PCI host bridge */
133 d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
134 sizeof(PCIDevice), 0, NULL, NULL);
135 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
136 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
137 d->config[0x08] = 0x00; // revision
138 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
139 d->config[0x0C] = 0x08; // cache_line_size
140 d->config[0x0D] = 0x10; // latency_timer
141 d->config[0x34] = 0x00; // capabilities_pointer
143 return s->bus;