coroutine: add test-coroutine --benchmark-lifecycle
[qemu/stefanha.git] / hw / omap_l4.c
blob4af0ca8ea611549151f61dfd686ec680d820f47e
1 /*
2 * TI OMAP L4 interconnect emulation.
4 * Copyright (C) 2007-2009 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) any later version of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "hw.h"
21 #include "omap.h"
23 #ifdef L4_MUX_HACK
24 static int omap_l4_io_entries;
25 static int omap_cpu_io_entry;
26 static struct omap_l4_entry {
27 CPUReadMemoryFunc * const *mem_read;
28 CPUWriteMemoryFunc * const *mem_write;
29 void *opaque;
30 } *omap_l4_io_entry;
31 static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
32 static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
33 static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
34 static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
35 static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
36 static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
37 static void **omap_l4_io_opaque;
39 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
40 CPUWriteMemoryFunc * const *mem_write, void *opaque)
42 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
43 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
44 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
46 return omap_l4_io_entries ++;
49 static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
51 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
53 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
56 static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
58 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
60 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
63 static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
65 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
67 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
70 static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
71 uint32_t value)
73 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
75 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
78 static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
79 uint32_t value)
81 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
83 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
86 static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
87 uint32_t value)
89 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
91 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
94 static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
95 omap_l4_io_readb,
96 omap_l4_io_readh,
97 omap_l4_io_readw,
100 static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
101 omap_l4_io_writeb,
102 omap_l4_io_writeh,
103 omap_l4_io_writew,
105 #else
106 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
107 CPUWriteMemoryFunc * const *mem_write,
108 void *opaque)
110 return cpu_register_io_memory(mem_read, mem_write, opaque,
111 DEVICE_NATIVE_ENDIAN);
113 #endif
115 struct omap_l4_s {
116 target_phys_addr_t base;
117 int ta_num;
118 struct omap_target_agent_s ta[0];
121 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
123 struct omap_l4_s *bus = qemu_mallocz(
124 sizeof(*bus) + ta_num * sizeof(*bus->ta));
126 bus->ta_num = ta_num;
127 bus->base = base;
129 #ifdef L4_MUX_HACK
130 omap_l4_io_entries = 1;
131 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
133 omap_cpu_io_entry =
134 cpu_register_io_memory(omap_l4_io_readfn,
135 omap_l4_io_writefn, bus, DEVICE_NATIVE_ENDIAN);
136 # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
137 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
138 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
139 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
140 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
141 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
142 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
143 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
144 #endif
146 return bus;
149 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
151 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
153 switch (addr) {
154 case 0x00: /* COMPONENT */
155 return s->component;
157 case 0x20: /* AGENT_CONTROL */
158 return s->control;
160 case 0x28: /* AGENT_STATUS */
161 return s->status;
164 OMAP_BAD_REG(addr);
165 return 0;
168 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
169 uint32_t value)
171 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
173 switch (addr) {
174 case 0x00: /* COMPONENT */
175 case 0x28: /* AGENT_STATUS */
176 OMAP_RO_REG(addr);
177 break;
179 case 0x20: /* AGENT_CONTROL */
180 s->control = value & 0x01000700;
181 if (value & 1) /* OCP_RESET */
182 s->status &= ~1; /* REQ_TIMEOUT */
183 break;
185 default:
186 OMAP_BAD_REG(addr);
190 static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
191 omap_badwidth_read16,
192 omap_l4ta_read,
193 omap_badwidth_read16,
196 static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
197 omap_badwidth_write32,
198 omap_badwidth_write32,
199 omap_l4ta_write,
202 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
203 const struct omap_l4_region_s *regions,
204 const struct omap_l4_agent_info_s *agents,
205 int cs)
207 int i, iomemtype;
208 struct omap_target_agent_s *ta = NULL;
209 const struct omap_l4_agent_info_s *info = NULL;
211 for (i = 0; i < bus->ta_num; i ++)
212 if (agents[i].ta == cs) {
213 ta = &bus->ta[i];
214 info = &agents[i];
215 break;
217 if (!ta) {
218 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
219 exit(-1);
222 ta->bus = bus;
223 ta->start = &regions[info->region];
224 ta->regions = info->regions;
226 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
227 ta->status = 0x00000000;
228 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
230 iomemtype = l4_register_io_memory(omap_l4ta_readfn,
231 omap_l4ta_writefn, ta);
232 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
234 return ta;
237 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
238 int iotype)
240 target_phys_addr_t base;
241 ssize_t size;
242 #ifdef L4_MUX_HACK
243 int i;
244 #endif
246 if (region < 0 || region >= ta->regions) {
247 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
248 exit(-1);
251 base = ta->bus->base + ta->start[region].offset;
252 size = ta->start[region].size;
253 if (iotype) {
254 #ifndef L4_MUX_HACK
255 cpu_register_physical_memory(base, size, iotype);
256 #else
257 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
258 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
259 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
260 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
261 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
262 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
263 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
264 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
265 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
266 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
268 #endif
271 return base;