coroutine: add test-coroutine --benchmark-lifecycle
[qemu/stefanha.git] / hw / axis_dev88.c
blob0e2135afd082ae41f07652fffc1abd8ad036f58d
1 /*
2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "sysbus.h"
26 #include "net.h"
27 #include "flash.h"
28 #include "boards.h"
29 #include "etraxfs.h"
30 #include "loader.h"
31 #include "elf.h"
32 #include "cris-boot.h"
34 #define D(x)
35 #define DNAND(x)
37 struct nand_state_t
39 NANDFlashState *nand;
40 unsigned int rdy:1;
41 unsigned int ale:1;
42 unsigned int cle:1;
43 unsigned int ce:1;
46 static struct nand_state_t nand_state;
47 static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
49 struct nand_state_t *s = opaque;
50 uint32_t r;
51 int rdy;
53 r = nand_getio(s->nand);
54 nand_getpins(s->nand, &rdy);
55 s->rdy = rdy;
57 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
58 return r;
61 static void
62 nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
64 struct nand_state_t *s = opaque;
65 int rdy;
67 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
68 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
69 nand_setio(s->nand, value);
70 nand_getpins(s->nand, &rdy);
71 s->rdy = rdy;
74 static CPUReadMemoryFunc * const nand_read[] = {
75 &nand_readl,
76 &nand_readl,
77 &nand_readl,
80 static CPUWriteMemoryFunc * const nand_write[] = {
81 &nand_writel,
82 &nand_writel,
83 &nand_writel,
87 struct tempsensor_t
89 unsigned int shiftreg;
90 unsigned int count;
91 enum {
92 ST_OUT, ST_IN, ST_Z
93 } state;
95 uint16_t regs[3];
98 static void tempsensor_clkedge(struct tempsensor_t *s,
99 unsigned int clk, unsigned int data_in)
101 D(printf("%s clk=%d state=%d sr=%x\n", __func__,
102 clk, s->state, s->shiftreg));
103 if (s->count == 0) {
104 s->count = 16;
105 s->state = ST_OUT;
107 switch (s->state) {
108 case ST_OUT:
109 /* Output reg is clocked at negedge. */
110 if (!clk) {
111 s->count--;
112 s->shiftreg <<= 1;
113 if (s->count == 0) {
114 s->shiftreg = 0;
115 s->state = ST_IN;
116 s->count = 16;
119 break;
120 case ST_Z:
121 if (clk) {
122 s->count--;
123 if (s->count == 0) {
124 s->shiftreg = 0;
125 s->state = ST_OUT;
126 s->count = 16;
129 break;
130 case ST_IN:
131 /* Indata is sampled at posedge. */
132 if (clk) {
133 s->count--;
134 s->shiftreg <<= 1;
135 s->shiftreg |= data_in & 1;
136 if (s->count == 0) {
137 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
138 s->regs[0] = s->shiftreg;
139 s->state = ST_OUT;
140 s->count = 16;
142 if ((s->regs[0] & 0xff) == 0) {
143 /* 25 degrees celcius. */
144 s->shiftreg = 0x0b9f;
145 } else if ((s->regs[0] & 0xff) == 0xff) {
146 /* Sensor ID, 0x8100 LM70. */
147 s->shiftreg = 0x8100;
148 } else
149 printf("Invalid tempsens state %x\n", s->regs[0]);
152 break;
157 #define RW_PA_DOUT 0x00
158 #define R_PA_DIN 0x01
159 #define RW_PA_OE 0x02
160 #define RW_PD_DOUT 0x10
161 #define R_PD_DIN 0x11
162 #define RW_PD_OE 0x12
164 static struct gpio_state_t
166 struct nand_state_t *nand;
167 struct tempsensor_t tempsensor;
168 uint32_t regs[0x5c / 4];
169 } gpio_state;
171 static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
173 struct gpio_state_t *s = opaque;
174 uint32_t r = 0;
176 addr >>= 2;
177 switch (addr)
179 case R_PA_DIN:
180 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
182 /* Encode pins from the nand. */
183 r |= s->nand->rdy << 7;
184 break;
185 case R_PD_DIN:
186 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
188 /* Encode temp sensor pins. */
189 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
190 break;
192 default:
193 r = s->regs[addr];
194 break;
196 return r;
197 D(printf("%s %x=%x\n", __func__, addr, r));
200 static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
202 struct gpio_state_t *s = opaque;
203 D(printf("%s %x=%x\n", __func__, addr, value));
205 addr >>= 2;
206 switch (addr)
208 case RW_PA_DOUT:
209 /* Decode nand pins. */
210 s->nand->ale = !!(value & (1 << 6));
211 s->nand->cle = !!(value & (1 << 5));
212 s->nand->ce = !!(value & (1 << 4));
214 s->regs[addr] = value;
215 break;
217 case RW_PD_DOUT:
218 /* Temp sensor clk. */
219 if ((s->regs[addr] ^ value) & 2)
220 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
221 !!(value & 16));
222 s->regs[addr] = value;
223 break;
225 default:
226 s->regs[addr] = value;
227 break;
231 static CPUReadMemoryFunc * const gpio_read[] = {
232 NULL, NULL,
233 &gpio_readl,
236 static CPUWriteMemoryFunc * const gpio_write[] = {
237 NULL, NULL,
238 &gpio_writel,
241 #define INTMEM_SIZE (128 * 1024)
243 static struct cris_load_info li;
245 static
246 void axisdev88_init (ram_addr_t ram_size,
247 const char *boot_device,
248 const char *kernel_filename, const char *kernel_cmdline,
249 const char *initrd_filename, const char *cpu_model)
251 CPUState *env;
252 DeviceState *dev;
253 SysBusDevice *s;
254 qemu_irq irq[30], nmi[2], *cpu_irq;
255 void *etraxfs_dmac;
256 struct etraxfs_dma_client *eth[2] = {NULL, NULL};
257 int i;
258 int nand_regs;
259 int gpio_regs;
260 ram_addr_t phys_ram;
261 ram_addr_t phys_intmem;
263 /* init CPUs */
264 if (cpu_model == NULL) {
265 cpu_model = "crisv32";
267 env = cpu_init(cpu_model);
269 /* allocate RAM */
270 phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
271 cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
273 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
274 internal memory. */
275 phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
276 cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
277 phys_intmem | IO_MEM_RAM);
280 /* Attach a NAND flash to CS1. */
281 nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
282 nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
283 DEVICE_NATIVE_ENDIAN);
284 cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
286 gpio_state.nand = &nand_state;
287 gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
288 DEVICE_NATIVE_ENDIAN);
289 cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
292 cpu_irq = cris_pic_init_cpu(env);
293 dev = qdev_create(NULL, "etraxfs,pic");
294 /* FIXME: Is there a proper way to signal vectors to the CPU core? */
295 qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
296 qdev_init_nofail(dev);
297 s = sysbus_from_qdev(dev);
298 sysbus_mmio_map(s, 0, 0x3001c000);
299 sysbus_connect_irq(s, 0, cpu_irq[0]);
300 sysbus_connect_irq(s, 1, cpu_irq[1]);
301 for (i = 0; i < 30; i++) {
302 irq[i] = qdev_get_gpio_in(dev, i);
304 nmi[0] = qdev_get_gpio_in(dev, 30);
305 nmi[1] = qdev_get_gpio_in(dev, 31);
307 etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
308 for (i = 0; i < 10; i++) {
309 /* On ETRAX, odd numbered channels are inputs. */
310 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
313 /* Add the two ethernet blocks. */
314 eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1);
315 if (nb_nics > 1)
316 eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2);
318 /* The DMA Connector block is missing, hardwire things for now. */
319 etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
320 etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
321 if (eth[1]) {
322 etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
323 etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
326 /* 2 timers. */
327 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
328 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
330 for (i = 0; i < 4; i++) {
331 sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
332 irq[0x14 + i]);
335 if (!kernel_filename) {
336 fprintf(stderr, "Kernel image must be specified\n");
337 exit(1);
340 li.image_filename = kernel_filename;
341 li.cmdline = kernel_cmdline;
342 cris_load_image(env, &li);
345 static QEMUMachine axisdev88_machine = {
346 .name = "axis-dev88",
347 .desc = "AXIS devboard 88",
348 .init = axisdev88_init,
351 static void axisdev88_machine_init(void)
353 qemu_register_machine(&axisdev88_machine);
356 machine_init(axisdev88_machine_init);