hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33
  34 //#define HPET_DEBUG
  35 #ifdef HPET_DEBUG
  36 #define DPRINTF printf
  37 #else
  38 #define DPRINTF(...)
  39 #endif
  40
  41 struct HPETState;
  42 typedef struct HPETTimer {  /* timers */
  43     uint8_t tn;             /*timer number*/
  44     QEMUTimer *qemu_timer;
  45     struct HPETState *state;
  46     /* Memory-mapped, software visible timer registers */
  47     uint64_t config;        /* configuration/cap */
  48     uint64_t cmp;           /* comparator */
  49     uint64_t fsb;           /* FSB route, not supported now */
  50     /* Hidden register state */
  51     uint64_t period;        /* Last value written to comparator */
  52     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  53                              * mode. Next pop will be actual timer expiration.
  54                              */
  55 } HPETTimer;
  56
  57 typedef struct HPETState {
  58     SysBusDevice busdev;
  59     uint64_t hpet_offset;
  60     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  61     HPETTimer timer[HPET_NUM_TIMERS];
  62
  63     /* Memory-mapped, software visible registers */
  64     uint64_t capability;        /* capabilities */
  65     uint64_t config;            /* configuration */
  66     uint64_t isr;               /* interrupt status reg */
  67     uint64_t hpet_counter;      /* main counter */
  68 } HPETState;
  69
  70 static HPETState *hpet_statep;
  71
  72 uint32_t hpet_in_legacy_mode(void)
  73 {
  74     if (!hpet_statep) {
  75         return 0;
  76     }
  77     return hpet_statep->config & HPET_CFG_LEGACY;
  78 }
  79
  80 static uint32_t timer_int_route(struct HPETTimer *timer)
  81 {
  82     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  83 }
  84
  85 static uint32_t hpet_enabled(void)
  86 {
  87     return hpet_statep->config & HPET_CFG_ENABLE;
  88 }
  89
  90 static uint32_t timer_is_periodic(HPETTimer *t)
  91 {
  92     return t->config & HPET_TN_PERIODIC;
  93 }
  94
  95 static uint32_t timer_enabled(HPETTimer *t)
  96 {
  97     return t->config & HPET_TN_ENABLE;
  98 }
  99
 100 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 101 {
 102     return ((int32_t)(b) - (int32_t)(a) < 0);
 103 }
 104
 105 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 106 {
 107     return ((int64_t)(b) - (int64_t)(a) < 0);
 108 }
 109
 110 static uint64_t ticks_to_ns(uint64_t value)
 111 {
 112     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 113 }
 114
 115 static uint64_t ns_to_ticks(uint64_t value)
 116 {
 117     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 118 }
 119
 120 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 121 {
 122     new &= mask;
 123     new |= old & ~mask;
 124     return new;
 125 }
 126
 127 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 128 {
 129     return (!(old & mask) && (new & mask));
 130 }
 131
 132 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 133 {
 134     return ((old & mask) && !(new & mask));
 135 }
 136
 137 static uint64_t hpet_get_ticks(void)
 138 {
 139     return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
 140 }
 141
 142 /*
 143  * calculate diff between comparator value and current ticks
 144  */
 145 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 146 {
 147
 148     if (t->config & HPET_TN_32BIT) {
 149         uint32_t diff, cmp;
 150
 151         cmp = (uint32_t)t->cmp;
 152         diff = cmp - (uint32_t)current;
 153         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 154         return (uint64_t)diff;
 155     } else {
 156         uint64_t diff, cmp;
 157
 158         cmp = t->cmp;
 159         diff = cmp - current;
 160         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 161         return diff;
 162     }
 163 }
 164
 165 static void update_irq(struct HPETTimer *timer)
 166 {
 167     int route;
 168
 169     if (timer->tn <= 1 && hpet_in_legacy_mode()) {
 170         /* if LegacyReplacementRoute bit is set, HPET specification requires
 171          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 172          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 173          */
 174         route = (timer->tn == 0) ? 0 : 8;
 175     } else {
 176         route = timer_int_route(timer);
 177     }
 178     if (!timer_enabled(timer) || !hpet_enabled()) {
 179         return;
 180     }
 181     qemu_irq_pulse(timer->state->irqs[route]);
 182 }
 183
 184 static void hpet_pre_save(void *opaque)
 185 {
 186     HPETState *s = opaque;
 187
 188     /* save current counter value */
 189     s->hpet_counter = hpet_get_ticks();
 190 }
 191
 192 static int hpet_post_load(void *opaque, int version_id)
 193 {
 194     HPETState *s = opaque;
 195
 196     /* Recalculate the offset between the main counter and guest time */
 197     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 198     return 0;
 199 }
 200
 201 static const VMStateDescription vmstate_hpet_timer = {
 202     .name = "hpet_timer",
 203     .version_id = 1,
 204     .minimum_version_id = 1,
 205     .minimum_version_id_old = 1,
 206     .fields      = (VMStateField []) {
 207         VMSTATE_UINT8(tn, HPETTimer),
 208         VMSTATE_UINT64(config, HPETTimer),
 209         VMSTATE_UINT64(cmp, HPETTimer),
 210         VMSTATE_UINT64(fsb, HPETTimer),
 211         VMSTATE_UINT64(period, HPETTimer),
 212         VMSTATE_UINT8(wrap_flag, HPETTimer),
 213         VMSTATE_TIMER(qemu_timer, HPETTimer),
 214         VMSTATE_END_OF_LIST()
 215     }
 216 };
 217
 218 static const VMStateDescription vmstate_hpet = {
 219     .name = "hpet",
 220     .version_id = 1,
 221     .minimum_version_id = 1,
 222     .minimum_version_id_old = 1,
 223     .pre_save = hpet_pre_save,
 224     .post_load = hpet_post_load,
 225     .fields      = (VMStateField []) {
 226         VMSTATE_UINT64(config, HPETState),
 227         VMSTATE_UINT64(isr, HPETState),
 228         VMSTATE_UINT64(hpet_counter, HPETState),
 229         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 230                              vmstate_hpet_timer, HPETTimer),
 231         VMSTATE_END_OF_LIST()
 232     }
 233 };
 234
 235 /*
 236  * timer expiration callback
 237  */
 238 static void hpet_timer(void *opaque)
 239 {
 240     HPETTimer *t = opaque;
 241     uint64_t diff;
 242
 243     uint64_t period = t->period;
 244     uint64_t cur_tick = hpet_get_ticks();
 245
 246     if (timer_is_periodic(t) && period != 0) {
 247         if (t->config & HPET_TN_32BIT) {
 248             while (hpet_time_after(cur_tick, t->cmp)) {
 249                 t->cmp = (uint32_t)(t->cmp + t->period);
 250             }
 251         } else {
 252             while (hpet_time_after64(cur_tick, t->cmp)) {
 253                 t->cmp += period;
 254             }
 255         }
 256         diff = hpet_calculate_diff(t, cur_tick);
 257         qemu_mod_timer(t->qemu_timer,
 258                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 259     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 260         if (t->wrap_flag) {
 261             diff = hpet_calculate_diff(t, cur_tick);
 262             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 263                            (int64_t)ticks_to_ns(diff));
 264             t->wrap_flag = 0;
 265         }
 266     }
 267     update_irq(t);
 268 }
 269
 270 static void hpet_set_timer(HPETTimer *t)
 271 {
 272     uint64_t diff;
 273     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 274     uint64_t cur_tick = hpet_get_ticks();
 275
 276     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 277     t->wrap_flag = 0;
 278     diff = hpet_calculate_diff(t, cur_tick);
 279
 280     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 281      * counter wraps in addition to an interrupt with comparator match.
 282      */
 283     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 284         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 285         if (wrap_diff < (uint32_t)diff) {
 286             diff = wrap_diff;
 287             t->wrap_flag = 1;
 288         }
 289     }
 290     qemu_mod_timer(t->qemu_timer,
 291                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 292 }
 293
 294 static void hpet_del_timer(HPETTimer *t)
 295 {
 296     qemu_del_timer(t->qemu_timer);
 297 }
 298
 299 #ifdef HPET_DEBUG
 300 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 301 {
 302     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 303     return 0;
 304 }
 305
 306 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 307 {
 308     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 309     return 0;
 310 }
 311 #endif
 312
 313 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 314 {
 315     HPETState *s = opaque;
 316     uint64_t cur_tick, index;
 317
 318     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 319     index = addr;
 320     /*address range of all TN regs*/
 321     if (index >= 0x100 && index <= 0x3ff) {
 322         uint8_t timer_id = (addr - 0x100) / 0x20;
 323         HPETTimer *timer = &s->timer[timer_id];
 324
 325         if (timer_id > HPET_NUM_TIMERS - 1) {
 326             DPRINTF("qemu: timer id out of range\n");
 327             return 0;
 328         }
 329
 330         switch ((addr - 0x100) % 0x20) {
 331         case HPET_TN_CFG:
 332             return timer->config;
 333         case HPET_TN_CFG + 4: // Interrupt capabilities
 334             return timer->config >> 32;
 335         case HPET_TN_CMP: // comparator register
 336             return timer->cmp;
 337         case HPET_TN_CMP + 4:
 338             return timer->cmp >> 32;
 339         case HPET_TN_ROUTE:
 340             return timer->fsb >> 32;
 341         default:
 342             DPRINTF("qemu: invalid hpet_ram_readl\n");
 343             break;
 344         }
 345     } else {
 346         switch (index) {
 347         case HPET_ID:
 348             return s->capability;
 349         case HPET_PERIOD:
 350             return s->capability >> 32;
 351         case HPET_CFG:
 352             return s->config;
 353         case HPET_CFG + 4:
 354             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 355             return 0;
 356         case HPET_COUNTER:
 357             if (hpet_enabled()) {
 358                 cur_tick = hpet_get_ticks();
 359             } else {
 360                 cur_tick = s->hpet_counter;
 361             }
 362             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 363             return cur_tick;
 364         case HPET_COUNTER + 4:
 365             if (hpet_enabled()) {
 366                 cur_tick = hpet_get_ticks();
 367             } else {
 368                 cur_tick = s->hpet_counter;
 369             }
 370             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 371             return cur_tick >> 32;
 372         case HPET_STATUS:
 373             return s->isr;
 374         default:
 375             DPRINTF("qemu: invalid hpet_ram_readl\n");
 376             break;
 377         }
 378     }
 379     return 0;
 380 }
 381
 382 #ifdef HPET_DEBUG
 383 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 384                             uint32_t value)
 385 {
 386     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 387            addr, value);
 388 }
 389
 390 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 391                             uint32_t value)
 392 {
 393     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 394            addr, value);
 395 }
 396 #endif
 397
 398 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 399                             uint32_t value)
 400 {
 401     int i;
 402     HPETState *s = opaque;
 403     uint64_t old_val, new_val, val, index;
 404
 405     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 406     index = addr;
 407     old_val = hpet_ram_readl(opaque, addr);
 408     new_val = value;
 409
 410     /*address range of all TN regs*/
 411     if (index >= 0x100 && index <= 0x3ff) {
 412         uint8_t timer_id = (addr - 0x100) / 0x20;
 413         HPETTimer *timer = &s->timer[timer_id];
 414
 415         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 416         if (timer_id > HPET_NUM_TIMERS - 1) {
 417             DPRINTF("qemu: timer id out of range\n");
 418             return;
 419         }
 420         switch ((addr - 0x100) % 0x20) {
 421         case HPET_TN_CFG:
 422             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 423             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 424             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 425             if (new_val & HPET_TN_32BIT) {
 426                 timer->cmp = (uint32_t)timer->cmp;
 427                 timer->period = (uint32_t)timer->period;
 428             }
 429             if (new_val & HPET_TN_TYPE_LEVEL) {
 430                 printf("qemu: level-triggered hpet not supported\n");
 431                 exit (-1);
 432             }
 433             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 434                 hpet_set_timer(timer);
 435             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 436                 hpet_del_timer(timer);
 437             }
 438             break;
 439         case HPET_TN_CFG + 4: // Interrupt capabilities
 440             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 441             break;
 442         case HPET_TN_CMP: // comparator register
 443             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 444             if (timer->config & HPET_TN_32BIT) {
 445                 new_val = (uint32_t)new_val;
 446             }
 447             if (!timer_is_periodic(timer)
 448                 || (timer->config & HPET_TN_SETVAL)) {
 449                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 450             }
 451             if (timer_is_periodic(timer)) {
 452                 /*
 453                  * FIXME: Clamp period to reasonable min value?
 454                  * Clamp period to reasonable max value
 455                  */
 456                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 457                 timer->period =
 458                     (timer->period & 0xffffffff00000000ULL) | new_val;
 459             }
 460             timer->config &= ~HPET_TN_SETVAL;
 461             if (hpet_enabled()) {
 462                 hpet_set_timer(timer);
 463             }
 464             break;
 465         case HPET_TN_CMP + 4: // comparator register high order
 466             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 467             if (!timer_is_periodic(timer)
 468                 || (timer->config & HPET_TN_SETVAL)) {
 469                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 470             } else {
 471                 /*
 472                  * FIXME: Clamp period to reasonable min value?
 473                  * Clamp period to reasonable max value
 474                  */
 475                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 476                 timer->period =
 477                     (timer->period & 0xffffffffULL) | new_val << 32;
 478                 }
 479                 timer->config &= ~HPET_TN_SETVAL;
 480                 if (hpet_enabled()) {
 481                     hpet_set_timer(timer);
 482                 }
 483                 break;
 484         case HPET_TN_ROUTE + 4:
 485             DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 486             break;
 487         default:
 488             DPRINTF("qemu: invalid hpet_ram_writel\n");
 489             break;
 490         }
 491         return;
 492     } else {
 493         switch (index) {
 494         case HPET_ID:
 495             return;
 496         case HPET_CFG:
 497             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 498             s->config = (s->config & 0xffffffff00000000ULL) | val;
 499             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 500                 /* Enable main counter and interrupt generation. */
 501                 s->hpet_offset =
 502                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 503                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 504                     if ((&s->timer[i])->cmp != ~0ULL) {
 505                         hpet_set_timer(&s->timer[i]);
 506                     }
 507                 }
 508             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 509                 /* Halt main counter and disable interrupt generation. */
 510                 s->hpet_counter = hpet_get_ticks();
 511                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 512                     hpet_del_timer(&s->timer[i]);
 513                 }
 514             }
 515             /* i8254 and RTC are disabled when HPET is in legacy mode */
 516             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 517                 hpet_pit_disable();
 518             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 519                 hpet_pit_enable();
 520             }
 521             break;
 522         case HPET_CFG + 4:
 523             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 524             break;
 525         case HPET_STATUS:
 526             /* FIXME: need to handle level-triggered interrupts */
 527             break;
 528         case HPET_COUNTER:
 529             if (hpet_enabled()) {
 530                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 531             }
 532             s->hpet_counter =
 533                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 534             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 535                     value, s->hpet_counter);
 536             break;
 537         case HPET_COUNTER + 4:
 538             if (hpet_enabled()) {
 539                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 540             }
 541             s->hpet_counter =
 542                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 543             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 544                     value, s->hpet_counter);
 545             break;
 546         default:
 547             DPRINTF("qemu: invalid hpet_ram_writel\n");
 548             break;
 549         }
 550     }
 551 }
 552
 553 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 554 #ifdef HPET_DEBUG
 555     hpet_ram_readb,
 556     hpet_ram_readw,
 557 #else
 558     NULL,
 559     NULL,
 560 #endif
 561     hpet_ram_readl,
 562 };
 563
 564 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 565 #ifdef HPET_DEBUG
 566     hpet_ram_writeb,
 567     hpet_ram_writew,
 568 #else
 569     NULL,
 570     NULL,
 571 #endif
 572     hpet_ram_writel,
 573 };
 574
 575 static void hpet_reset(DeviceState *d)
 576 {
 577     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 578     int i;
 579     static int count = 0;
 580
 581     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 582         HPETTimer *timer = &s->timer[i];
 583
 584         hpet_del_timer(timer);
 585         timer->cmp = ~0ULL;
 586         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 587         /* advertise availability of ioapic inti2 */
 588         timer->config |=  0x00000004ULL << 32;
 589         timer->period = 0ULL;
 590         timer->wrap_flag = 0;
 591     }
 592
 593     s->hpet_counter = 0ULL;
 594     s->hpet_offset = 0ULL;
 595     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 596     s->capability = 0x8086a201ULL;
 597     s->capability |= ((HPET_CLK_PERIOD) << 32);
 598     s->config = 0ULL;
 599     if (count > 0) {
 600         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 601          * because hpet is taking over for pit here. On subsequent invocations,
 602          * hpet_reset is called due to system reset. At this point control must
 603          * be returned to pit until SW reenables hpet.
 604          */
 605         hpet_pit_enable();
 606     }
 607     count = 1;
 608 }
 609
 610 static int hpet_init(SysBusDevice *dev)
 611 {
 612     HPETState *s = FROM_SYSBUS(HPETState, dev);
 613     int i, iomemtype;
 614     HPETTimer *timer;
 615
 616     assert(!hpet_statep);
 617     hpet_statep = s;
 618     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 619         sysbus_init_irq(dev, &s->irqs[i]);
 620     }
 621     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 622         timer = &s->timer[i];
 623         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 624         timer->tn = i;
 625         timer->state = s;
 626     }
 627
 628     /* HPET Area */
 629     iomemtype = cpu_register_io_memory(hpet_ram_read,
 630                                        hpet_ram_write, s);
 631     sysbus_init_mmio(dev, 0x400, iomemtype);
 632     return 0;
 633 }
 634
 635 static SysBusDeviceInfo hpet_device_info = {
 636     .qdev.name    = "hpet",
 637     .qdev.size    = sizeof(HPETState),
 638     .qdev.no_user = 1,
 639     .qdev.vmsd    = &vmstate_hpet,
 640     .qdev.reset   = hpet_reset,
 641     .init         = hpet_init,
 642 };
 643
 644 static void hpet_register_device(void)
 645 {
 646     sysbus_register_withprop(&hpet_device_info);
 647 }
 648
 649 device_init(hpet_register_device)