2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
18 #include "block_int.h"
21 //#define DEBUG_LSI_REG
24 #define DPRINTF(fmt, ...) \
25 do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
26 #define BADF(fmt, ...) \
27 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #define BADF(fmt, ...) \
31 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0)
34 #define LSI_MAX_DEVS 7
36 #define LSI_SCNTL0_TRG 0x01
37 #define LSI_SCNTL0_AAP 0x02
38 #define LSI_SCNTL0_EPC 0x08
39 #define LSI_SCNTL0_WATN 0x10
40 #define LSI_SCNTL0_START 0x20
42 #define LSI_SCNTL1_SST 0x01
43 #define LSI_SCNTL1_IARB 0x02
44 #define LSI_SCNTL1_AESP 0x04
45 #define LSI_SCNTL1_RST 0x08
46 #define LSI_SCNTL1_CON 0x10
47 #define LSI_SCNTL1_DHP 0x20
48 #define LSI_SCNTL1_ADB 0x40
49 #define LSI_SCNTL1_EXC 0x80
51 #define LSI_SCNTL2_WSR 0x01
52 #define LSI_SCNTL2_VUE0 0x02
53 #define LSI_SCNTL2_VUE1 0x04
54 #define LSI_SCNTL2_WSS 0x08
55 #define LSI_SCNTL2_SLPHBEN 0x10
56 #define LSI_SCNTL2_SLPMD 0x20
57 #define LSI_SCNTL2_CHM 0x40
58 #define LSI_SCNTL2_SDU 0x80
60 #define LSI_ISTAT0_DIP 0x01
61 #define LSI_ISTAT0_SIP 0x02
62 #define LSI_ISTAT0_INTF 0x04
63 #define LSI_ISTAT0_CON 0x08
64 #define LSI_ISTAT0_SEM 0x10
65 #define LSI_ISTAT0_SIGP 0x20
66 #define LSI_ISTAT0_SRST 0x40
67 #define LSI_ISTAT0_ABRT 0x80
69 #define LSI_ISTAT1_SI 0x01
70 #define LSI_ISTAT1_SRUN 0x02
71 #define LSI_ISTAT1_FLSH 0x04
73 #define LSI_SSTAT0_SDP0 0x01
74 #define LSI_SSTAT0_RST 0x02
75 #define LSI_SSTAT0_WOA 0x04
76 #define LSI_SSTAT0_LOA 0x08
77 #define LSI_SSTAT0_AIP 0x10
78 #define LSI_SSTAT0_OLF 0x20
79 #define LSI_SSTAT0_ORF 0x40
80 #define LSI_SSTAT0_ILF 0x80
82 #define LSI_SIST0_PAR 0x01
83 #define LSI_SIST0_RST 0x02
84 #define LSI_SIST0_UDC 0x04
85 #define LSI_SIST0_SGE 0x08
86 #define LSI_SIST0_RSL 0x10
87 #define LSI_SIST0_SEL 0x20
88 #define LSI_SIST0_CMP 0x40
89 #define LSI_SIST0_MA 0x80
91 #define LSI_SIST1_HTH 0x01
92 #define LSI_SIST1_GEN 0x02
93 #define LSI_SIST1_STO 0x04
94 #define LSI_SIST1_SBMC 0x10
96 #define LSI_SOCL_IO 0x01
97 #define LSI_SOCL_CD 0x02
98 #define LSI_SOCL_MSG 0x04
99 #define LSI_SOCL_ATN 0x08
100 #define LSI_SOCL_SEL 0x10
101 #define LSI_SOCL_BSY 0x20
102 #define LSI_SOCL_ACK 0x40
103 #define LSI_SOCL_REQ 0x80
105 #define LSI_DSTAT_IID 0x01
106 #define LSI_DSTAT_SIR 0x04
107 #define LSI_DSTAT_SSI 0x08
108 #define LSI_DSTAT_ABRT 0x10
109 #define LSI_DSTAT_BF 0x20
110 #define LSI_DSTAT_MDPE 0x40
111 #define LSI_DSTAT_DFE 0x80
113 #define LSI_DCNTL_COM 0x01
114 #define LSI_DCNTL_IRQD 0x02
115 #define LSI_DCNTL_STD 0x04
116 #define LSI_DCNTL_IRQM 0x08
117 #define LSI_DCNTL_SSM 0x10
118 #define LSI_DCNTL_PFEN 0x20
119 #define LSI_DCNTL_PFF 0x40
120 #define LSI_DCNTL_CLSE 0x80
122 #define LSI_DMODE_MAN 0x01
123 #define LSI_DMODE_BOF 0x02
124 #define LSI_DMODE_ERMP 0x04
125 #define LSI_DMODE_ERL 0x08
126 #define LSI_DMODE_DIOM 0x10
127 #define LSI_DMODE_SIOM 0x20
129 #define LSI_CTEST2_DACK 0x01
130 #define LSI_CTEST2_DREQ 0x02
131 #define LSI_CTEST2_TEOP 0x04
132 #define LSI_CTEST2_PCICIE 0x08
133 #define LSI_CTEST2_CM 0x10
134 #define LSI_CTEST2_CIO 0x20
135 #define LSI_CTEST2_SIGP 0x40
136 #define LSI_CTEST2_DDIR 0x80
138 #define LSI_CTEST5_BL2 0x04
139 #define LSI_CTEST5_DDIR 0x08
140 #define LSI_CTEST5_MASR 0x10
141 #define LSI_CTEST5_DFSN 0x20
142 #define LSI_CTEST5_BBCK 0x40
143 #define LSI_CTEST5_ADCK 0x80
145 #define LSI_CCNTL0_DILS 0x01
146 #define LSI_CCNTL0_DISFC 0x10
147 #define LSI_CCNTL0_ENNDJ 0x20
148 #define LSI_CCNTL0_PMJCTL 0x40
149 #define LSI_CCNTL0_ENPMJ 0x80
151 #define LSI_CCNTL1_EN64DBMV 0x01
152 #define LSI_CCNTL1_EN64TIBMV 0x02
153 #define LSI_CCNTL1_64TIMOD 0x04
154 #define LSI_CCNTL1_DDAC 0x08
155 #define LSI_CCNTL1_ZMOD 0x80
157 /* Enable Response to Reselection */
158 #define LSI_SCID_RRE 0x60
160 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
170 /* Maximum length of MSG IN data. */
171 #define LSI_MAX_MSGIN_LEN 8
173 /* Flag set if this is a tagged command. */
174 #define LSI_TAG_VALID (1 << 16)
176 typedef struct lsi_request
{
182 QTAILQ_ENTRY(lsi_request
) next
;
189 uint32_t script_ram_base
;
191 int carry
; /* ??? Should this be an a visible register somewhere? */
193 /* Action to take at the end of a MSG IN phase.
194 0 = COMMAND, 1 = disconnect, 2 = DATA OUT, 3 = DATA IN. */
197 uint8_t msg
[LSI_MAX_MSGIN_LEN
];
198 /* 0 if SCRIPTS are running or stopped.
199 * 1 if a Wait Reselect instruction has been issued.
200 * 2 if processing DMA from lsi_execute_script.
201 * 3 if a DMA operation is in progress. */
205 /* The tag is a combination of the device ID and the SCSI tag. */
207 int command_complete
;
208 QTAILQ_HEAD(, lsi_request
) queue
;
209 lsi_request
*current
;
270 uint32_t scratch
[18]; /* SCRATCHA-SCRATCHR */
273 /* Script ram is stored as 32-bit words in host byteorder. */
274 uint32_t script_ram
[2048];
277 static inline int lsi_irq_on_rsl(LSIState
*s
)
279 return (s
->sien0
& LSI_SIST0_RSL
) && (s
->scid
& LSI_SCID_RRE
);
282 static void lsi_soft_reset(LSIState
*s
)
296 memset(s
->scratch
, 0, sizeof(s
->scratch
));
300 s
->dstat
= LSI_DSTAT_DFE
;
309 s
->ctest2
= LSI_CTEST2_DACK
;
352 while (!QTAILQ_EMPTY(&s
->queue
)) {
353 p
= QTAILQ_FIRST(&s
->queue
);
354 QTAILQ_REMOVE(&s
->queue
, p
, next
);
358 qemu_free(s
->current
);
363 static int lsi_dma_40bit(LSIState
*s
)
365 if ((s
->ccntl1
& LSI_CCNTL1_40BIT
) == LSI_CCNTL1_40BIT
)
370 static int lsi_dma_ti64bit(LSIState
*s
)
372 if ((s
->ccntl1
& LSI_CCNTL1_EN64TIBMV
) == LSI_CCNTL1_EN64TIBMV
)
377 static int lsi_dma_64bit(LSIState
*s
)
379 if ((s
->ccntl1
& LSI_CCNTL1_EN64DBMV
) == LSI_CCNTL1_EN64DBMV
)
384 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
);
385 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
);
386 static void lsi_execute_script(LSIState
*s
);
387 static void lsi_reselect(LSIState
*s
, lsi_request
*p
);
389 static inline uint32_t read_dword(LSIState
*s
, uint32_t addr
)
393 /* Optimize reading from SCRIPTS RAM. */
394 if ((addr
& 0xffffe000) == s
->script_ram_base
) {
395 return s
->script_ram
[(addr
& 0x1fff) >> 2];
397 cpu_physical_memory_read(addr
, (uint8_t *)&buf
, 4);
398 return cpu_to_le32(buf
);
401 static void lsi_stop_script(LSIState
*s
)
403 s
->istat1
&= ~LSI_ISTAT1_SRUN
;
406 static void lsi_update_irq(LSIState
*s
)
409 static int last_level
;
412 /* It's unclear whether the DIP/SIP bits should be cleared when the
413 Interrupt Status Registers are cleared or when istat0 is read.
414 We currently do the formwer, which seems to work. */
417 if (s
->dstat
& s
->dien
)
419 s
->istat0
|= LSI_ISTAT0_DIP
;
421 s
->istat0
&= ~LSI_ISTAT0_DIP
;
424 if (s
->sist0
|| s
->sist1
) {
425 if ((s
->sist0
& s
->sien0
) || (s
->sist1
& s
->sien1
))
427 s
->istat0
|= LSI_ISTAT0_SIP
;
429 s
->istat0
&= ~LSI_ISTAT0_SIP
;
431 if (s
->istat0
& LSI_ISTAT0_INTF
)
434 if (level
!= last_level
) {
435 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
436 level
, s
->dstat
, s
->sist1
, s
->sist0
);
439 qemu_set_irq(s
->dev
.irq
[0], level
);
441 if (!level
&& lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
)) {
442 DPRINTF("Handled IRQs & disconnected, looking for pending "
444 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
453 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
454 static void lsi_script_scsi_interrupt(LSIState
*s
, int stat0
, int stat1
)
459 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
460 stat1
, stat0
, s
->sist1
, s
->sist0
);
463 /* Stop processor on fatal or unmasked interrupt. As a special hack
464 we don't stop processing when raising STO. Instead continue
465 execution and stop at the next insn that accesses the SCSI bus. */
466 mask0
= s
->sien0
| ~(LSI_SIST0_CMP
| LSI_SIST0_SEL
| LSI_SIST0_RSL
);
467 mask1
= s
->sien1
| ~(LSI_SIST1_GEN
| LSI_SIST1_HTH
);
468 mask1
&= ~LSI_SIST1_STO
;
469 if (s
->sist0
& mask0
|| s
->sist1
& mask1
) {
475 /* Stop SCRIPTS execution and raise a DMA interrupt. */
476 static void lsi_script_dma_interrupt(LSIState
*s
, int stat
)
478 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat
, s
->dstat
);
484 static inline void lsi_set_phase(LSIState
*s
, int phase
)
486 s
->sstat1
= (s
->sstat1
& ~PHASE_MASK
) | phase
;
489 static void lsi_bad_phase(LSIState
*s
, int out
, int new_phase
)
491 /* Trigger a phase mismatch. */
492 if (s
->ccntl0
& LSI_CCNTL0_ENPMJ
) {
493 if ((s
->ccntl0
& LSI_CCNTL0_PMJCTL
)) {
494 s
->dsp
= out
? s
->pmjad1
: s
->pmjad2
;
496 s
->dsp
= (s
->scntl2
& LSI_SCNTL2_WSR
? s
->pmjad2
: s
->pmjad1
);
498 DPRINTF("Data phase mismatch jump to %08x\n", s
->dsp
);
500 DPRINTF("Phase mismatch interrupt\n");
501 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
504 lsi_set_phase(s
, new_phase
);
508 /* Resume SCRIPTS execution after a DMA operation. */
509 static void lsi_resume_script(LSIState
*s
)
511 if (s
->waiting
!= 2) {
513 lsi_execute_script(s
);
519 static void lsi_disconnect(LSIState
*s
)
521 s
->scntl1
&= ~LSI_SCNTL1_CON
;
522 s
->sstat1
&= ~PHASE_MASK
;
525 static void lsi_bad_selection(LSIState
*s
, uint32_t id
)
527 DPRINTF("Selected absent target %d\n", id
);
528 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_STO
);
532 /* Initiate a SCSI layer data transfer. */
533 static void lsi_do_dma(LSIState
*s
, int out
)
536 target_phys_addr_t addr
;
540 if (!s
->current
->dma_len
) {
541 /* Wait until data is available. */
542 DPRINTF("DMA no data available\n");
546 id
= (s
->current
->tag
>> 8) & 0xf;
547 dev
= s
->bus
.devs
[id
];
549 lsi_bad_selection(s
, id
);
554 if (count
> s
->current
->dma_len
)
555 count
= s
->current
->dma_len
;
558 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
559 if (lsi_dma_40bit(s
) || lsi_dma_ti64bit(s
))
560 addr
|= ((uint64_t)s
->dnad64
<< 32);
562 addr
|= ((uint64_t)s
->dbms
<< 32);
564 addr
|= ((uint64_t)s
->sbms
<< 32);
566 DPRINTF("DMA addr=0x" TARGET_FMT_plx
" len=%d\n", addr
, count
);
571 if (s
->current
->dma_buf
== NULL
) {
572 s
->current
->dma_buf
= dev
->info
->get_buf(dev
, s
->current
->tag
);
575 /* ??? Set SFBR to first data byte. */
577 cpu_physical_memory_read(addr
, s
->current
->dma_buf
, count
);
579 cpu_physical_memory_write(addr
, s
->current
->dma_buf
, count
);
581 s
->current
->dma_len
-= count
;
582 if (s
->current
->dma_len
== 0) {
583 s
->current
->dma_buf
= NULL
;
585 /* Write the data. */
586 dev
->info
->write_data(dev
, s
->current
->tag
);
588 /* Request any remaining data. */
589 dev
->info
->read_data(dev
, s
->current
->tag
);
592 s
->current
->dma_buf
+= count
;
593 lsi_resume_script(s
);
598 /* Add a command to the queue. */
599 static void lsi_queue_command(LSIState
*s
)
601 lsi_request
*p
= s
->current
;
603 DPRINTF("Queueing tag=0x%x\n", p
->tag
);
604 assert(s
->current
!= NULL
);
605 assert(s
->current
->dma_len
== 0);
606 QTAILQ_INSERT_TAIL(&s
->queue
, s
->current
, next
);
610 p
->out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
613 /* Queue a byte for a MSG IN phase. */
614 static void lsi_add_msg_byte(LSIState
*s
, uint8_t data
)
616 if (s
->msg_len
>= LSI_MAX_MSGIN_LEN
) {
617 BADF("MSG IN data too long\n");
619 DPRINTF("MSG IN 0x%02x\n", data
);
620 s
->msg
[s
->msg_len
++] = data
;
624 /* Perform reselection to continue a command. */
625 static void lsi_reselect(LSIState
*s
, lsi_request
*p
)
629 assert(s
->current
== NULL
);
630 QTAILQ_REMOVE(&s
->queue
, p
, next
);
633 id
= (p
->tag
>> 8) & 0xf;
635 /* LSI53C700 Family Compatibility, see LSI53C895A 4-73 */
636 if (!(s
->dcntl
& LSI_DCNTL_COM
)) {
637 s
->sfbr
= 1 << (id
& 0x7);
639 DPRINTF("Reselected target %d\n", id
);
640 s
->scntl1
|= LSI_SCNTL1_CON
;
641 lsi_set_phase(s
, PHASE_MI
);
642 s
->msg_action
= p
->out
? 2 : 3;
643 s
->current
->dma_len
= p
->pending
;
644 lsi_add_msg_byte(s
, 0x80);
645 if (s
->current
->tag
& LSI_TAG_VALID
) {
646 lsi_add_msg_byte(s
, 0x20);
647 lsi_add_msg_byte(s
, p
->tag
& 0xff);
650 if (lsi_irq_on_rsl(s
)) {
651 lsi_script_scsi_interrupt(s
, LSI_SIST0_RSL
, 0);
655 /* Record that data is available for a queued command. Returns zero if
656 the device was reselected, nonzero if the IO is deferred. */
657 static int lsi_queue_tag(LSIState
*s
, uint32_t tag
, uint32_t arg
)
661 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
664 BADF("Multiple IO pending for tag %d\n", tag
);
667 /* Reselect if waiting for it, or if reselection triggers an IRQ
669 Since no interrupt stacking is implemented in the emulation, it
670 is also required that there are no pending interrupts waiting
671 for service from the device driver. */
672 if (s
->waiting
== 1 ||
673 (lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
) &&
674 !(s
->istat0
& (LSI_ISTAT0_SIP
| LSI_ISTAT0_DIP
)))) {
675 /* Reselect device. */
679 DPRINTF("Queueing IO tag=0x%x\n", tag
);
685 BADF("IO with unknown tag %d\n", tag
);
689 /* Callback to indicate that the SCSI layer has completed a transfer. */
690 static void lsi_command_complete(SCSIBus
*bus
, int reason
, uint32_t tag
,
693 LSIState
*s
= DO_UPCAST(LSIState
, dev
.qdev
, bus
->qbus
.parent
);
696 out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
697 if (reason
== SCSI_REASON_DONE
) {
698 DPRINTF("Command complete sense=%d\n", (int)arg
);
700 s
->command_complete
= 2;
701 if (s
->waiting
&& s
->dbc
!= 0) {
702 /* Raise phase mismatch for short transfers. */
703 lsi_bad_phase(s
, out
, PHASE_ST
);
705 lsi_set_phase(s
, PHASE_ST
);
708 qemu_free(s
->current
);
711 lsi_resume_script(s
);
715 if (s
->waiting
== 1 || !s
->current
|| tag
!= s
->current
->tag
||
716 (lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
))) {
717 if (lsi_queue_tag(s
, tag
, arg
))
721 /* host adapter (re)connected */
722 DPRINTF("Data ready tag=0x%x len=%d\n", tag
, arg
);
723 s
->current
->dma_len
= arg
;
724 s
->command_complete
= 1;
727 if (s
->waiting
== 1 || s
->dbc
== 0) {
728 lsi_resume_script(s
);
734 static void lsi_do_command(LSIState
*s
)
741 DPRINTF("Send command len=%d\n", s
->dbc
);
744 cpu_physical_memory_read(s
->dnad
, buf
, s
->dbc
);
746 s
->command_complete
= 0;
748 id
= (s
->select_tag
>> 8) & 0xf;
749 dev
= s
->bus
.devs
[id
];
751 lsi_bad_selection(s
, id
);
755 assert(s
->current
== NULL
);
756 s
->current
= qemu_mallocz(sizeof(lsi_request
));
757 s
->current
->tag
= s
->select_tag
;
759 n
= dev
->info
->send_command(dev
, s
->current
->tag
, buf
, s
->current_lun
);
761 lsi_set_phase(s
, PHASE_DI
);
762 dev
->info
->read_data(dev
, s
->current
->tag
);
764 lsi_set_phase(s
, PHASE_DO
);
765 dev
->info
->write_data(dev
, s
->current
->tag
);
768 if (!s
->command_complete
) {
770 /* Command did not complete immediately so disconnect. */
771 lsi_add_msg_byte(s
, 2); /* SAVE DATA POINTER */
772 lsi_add_msg_byte(s
, 4); /* DISCONNECT */
774 lsi_set_phase(s
, PHASE_MI
);
776 lsi_queue_command(s
);
778 /* wait command complete */
779 lsi_set_phase(s
, PHASE_DI
);
784 static void lsi_do_status(LSIState
*s
)
787 DPRINTF("Get status len=%d sense=%d\n", s
->dbc
, s
->sense
);
789 BADF("Bad Status move\n");
793 cpu_physical_memory_write(s
->dnad
, &sense
, 1);
794 lsi_set_phase(s
, PHASE_MI
);
796 lsi_add_msg_byte(s
, 0); /* COMMAND COMPLETE */
799 static void lsi_do_msgin(LSIState
*s
)
802 DPRINTF("Message in len=%d/%d\n", s
->dbc
, s
->msg_len
);
807 cpu_physical_memory_write(s
->dnad
, s
->msg
, len
);
808 /* Linux drivers rely on the last byte being in the SIDL. */
809 s
->sidl
= s
->msg
[len
- 1];
812 memmove(s
->msg
, s
->msg
+ len
, s
->msg_len
);
814 /* ??? Check if ATN (not yet implemented) is asserted and maybe
815 switch to PHASE_MO. */
816 switch (s
->msg_action
) {
818 lsi_set_phase(s
, PHASE_CMD
);
824 lsi_set_phase(s
, PHASE_DO
);
827 lsi_set_phase(s
, PHASE_DI
);
835 /* Read the next byte during a MSGOUT phase. */
836 static uint8_t lsi_get_msgbyte(LSIState
*s
)
839 cpu_physical_memory_read(s
->dnad
, &data
, 1);
845 /* Skip the next n bytes during a MSGOUT phase. */
846 static void lsi_skip_msgbytes(LSIState
*s
, unsigned int n
)
852 static void lsi_do_msgout(LSIState
*s
)
857 DPRINTF("MSG out len=%d\n", s
->dbc
);
859 msg
= lsi_get_msgbyte(s
);
864 DPRINTF("MSG: Disconnect\n");
868 DPRINTF("MSG: No Operation\n");
869 lsi_set_phase(s
, PHASE_CMD
);
872 len
= lsi_get_msgbyte(s
);
873 msg
= lsi_get_msgbyte(s
);
874 (void)len
; /* avoid a warning about unused variable*/
875 DPRINTF("Extended message 0x%x (len %d)\n", msg
, len
);
878 DPRINTF("SDTR (ignored)\n");
879 lsi_skip_msgbytes(s
, 2);
882 DPRINTF("WDTR (ignored)\n");
883 lsi_skip_msgbytes(s
, 1);
889 case 0x20: /* SIMPLE queue */
890 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
891 DPRINTF("SIMPLE queue tag=0x%x\n", s
->select_tag
& 0xff);
893 case 0x21: /* HEAD of queue */
894 BADF("HEAD queue not implemented\n");
895 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
897 case 0x22: /* ORDERED queue */
898 BADF("ORDERED queue not implemented\n");
899 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
902 if ((msg
& 0x80) == 0) {
905 s
->current_lun
= msg
& 7;
906 DPRINTF("Select LUN %d\n", s
->current_lun
);
907 lsi_set_phase(s
, PHASE_CMD
);
913 BADF("Unimplemented message 0x%02x\n", msg
);
914 lsi_set_phase(s
, PHASE_MI
);
915 lsi_add_msg_byte(s
, 7); /* MESSAGE REJECT */
919 /* Sign extend a 24-bit value. */
920 static inline int32_t sxt24(int32_t n
)
922 return (n
<< 8) >> 8;
925 #define LSI_BUF_SIZE 4096
926 static void lsi_memcpy(LSIState
*s
, uint32_t dest
, uint32_t src
, int count
)
929 uint8_t buf
[LSI_BUF_SIZE
];
931 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest
, src
, count
);
933 n
= (count
> LSI_BUF_SIZE
) ? LSI_BUF_SIZE
: count
;
934 cpu_physical_memory_read(src
, buf
, n
);
935 cpu_physical_memory_write(dest
, buf
, n
);
942 static void lsi_wait_reselect(LSIState
*s
)
946 DPRINTF("Wait Reselect\n");
948 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
954 if (s
->current
== NULL
) {
959 static void lsi_execute_script(LSIState
*s
)
962 uint32_t addr
, addr_high
;
964 int insn_processed
= 0;
966 s
->istat1
|= LSI_ISTAT1_SRUN
;
969 insn
= read_dword(s
, s
->dsp
);
971 /* If we receive an empty opcode increment the DSP by 4 bytes
972 instead of 8 and execute the next opcode at that location */
976 addr
= read_dword(s
, s
->dsp
+ 4);
978 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s
->dsp
, insn
, addr
);
980 s
->dcmd
= insn
>> 24;
982 switch (insn
>> 30) {
983 case 0: /* Block move. */
984 if (s
->sist1
& LSI_SIST1_STO
) {
985 DPRINTF("Delayed select timeout\n");
989 s
->dbc
= insn
& 0xffffff;
993 if (insn
& (1 << 29)) {
994 /* Indirect addressing. */
995 addr
= read_dword(s
, addr
);
996 } else if (insn
& (1 << 28)) {
999 /* Table indirect addressing. */
1001 /* 32-bit Table indirect */
1002 offset
= sxt24(addr
);
1003 cpu_physical_memory_read(s
->dsa
+ offset
, (uint8_t *)buf
, 8);
1004 /* byte count is stored in bits 0:23 only */
1005 s
->dbc
= cpu_to_le32(buf
[0]) & 0xffffff;
1007 addr
= cpu_to_le32(buf
[1]);
1009 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
1010 * table, bits [31:24] */
1011 if (lsi_dma_40bit(s
))
1012 addr_high
= cpu_to_le32(buf
[0]) >> 24;
1013 else if (lsi_dma_ti64bit(s
)) {
1014 int selector
= (cpu_to_le32(buf
[0]) >> 24) & 0x1f;
1017 /* offset index into scratch registers since
1018 * TI64 mode can use registers C to R */
1019 addr_high
= s
->scratch
[2 + selector
];
1022 addr_high
= s
->mmrs
;
1025 addr_high
= s
->mmws
;
1034 addr_high
= s
->sbms
;
1037 addr_high
= s
->dbms
;
1040 BADF("Illegal selector specified (0x%x > 0x15)"
1041 " for 64-bit DMA block move", selector
);
1045 } else if (lsi_dma_64bit(s
)) {
1046 /* fetch a 3rd dword if 64-bit direct move is enabled and
1047 only if we're not doing table indirect or indirect addressing */
1048 s
->dbms
= read_dword(s
, s
->dsp
);
1050 s
->ia
= s
->dsp
- 12;
1052 if ((s
->sstat1
& PHASE_MASK
) != ((insn
>> 24) & 7)) {
1053 DPRINTF("Wrong phase got %d expected %d\n",
1054 s
->sstat1
& PHASE_MASK
, (insn
>> 24) & 7);
1055 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
1059 s
->dnad64
= addr_high
;
1060 switch (s
->sstat1
& 0x7) {
1086 BADF("Unimplemented phase %d\n", s
->sstat1
& PHASE_MASK
);
1089 s
->dfifo
= s
->dbc
& 0xff;
1090 s
->ctest5
= (s
->ctest5
& 0xfc) | ((s
->dbc
>> 8) & 3);
1093 s
->ua
= addr
+ s
->dbc
;
1096 case 1: /* IO or Read/Write instruction. */
1097 opcode
= (insn
>> 27) & 7;
1101 if (insn
& (1 << 25)) {
1102 id
= read_dword(s
, s
->dsa
+ sxt24(insn
));
1106 id
= (id
>> 16) & 0xf;
1107 if (insn
& (1 << 26)) {
1108 addr
= s
->dsp
+ sxt24(addr
);
1112 case 0: /* Select */
1114 if (s
->scntl1
& LSI_SCNTL1_CON
) {
1115 DPRINTF("Already reselected, jumping to alternative address\n");
1119 s
->sstat0
|= LSI_SSTAT0_WOA
;
1120 s
->scntl1
&= ~LSI_SCNTL1_IARB
;
1121 if (id
>= LSI_MAX_DEVS
|| !s
->bus
.devs
[id
]) {
1122 lsi_bad_selection(s
, id
);
1125 DPRINTF("Selected target %d%s\n",
1126 id
, insn
& (1 << 3) ? " ATN" : "");
1127 /* ??? Linux drivers compain when this is set. Maybe
1128 it only applies in low-level mode (unimplemented).
1129 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1130 s
->select_tag
= id
<< 8;
1131 s
->scntl1
|= LSI_SCNTL1_CON
;
1132 if (insn
& (1 << 3)) {
1133 s
->socl
|= LSI_SOCL_ATN
;
1135 lsi_set_phase(s
, PHASE_MO
);
1137 case 1: /* Disconnect */
1138 DPRINTF("Wait Disconnect\n");
1139 s
->scntl1
&= ~LSI_SCNTL1_CON
;
1141 case 2: /* Wait Reselect */
1142 if (!lsi_irq_on_rsl(s
)) {
1143 lsi_wait_reselect(s
);
1147 DPRINTF("Set%s%s%s%s\n",
1148 insn
& (1 << 3) ? " ATN" : "",
1149 insn
& (1 << 6) ? " ACK" : "",
1150 insn
& (1 << 9) ? " TM" : "",
1151 insn
& (1 << 10) ? " CC" : "");
1152 if (insn
& (1 << 3)) {
1153 s
->socl
|= LSI_SOCL_ATN
;
1154 lsi_set_phase(s
, PHASE_MO
);
1156 if (insn
& (1 << 9)) {
1157 BADF("Target mode not implemented\n");
1160 if (insn
& (1 << 10))
1164 DPRINTF("Clear%s%s%s%s\n",
1165 insn
& (1 << 3) ? " ATN" : "",
1166 insn
& (1 << 6) ? " ACK" : "",
1167 insn
& (1 << 9) ? " TM" : "",
1168 insn
& (1 << 10) ? " CC" : "");
1169 if (insn
& (1 << 3)) {
1170 s
->socl
&= ~LSI_SOCL_ATN
;
1172 if (insn
& (1 << 10))
1183 static const char *opcode_names
[3] =
1184 {"Write", "Read", "Read-Modify-Write"};
1185 static const char *operator_names
[8] =
1186 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1189 reg
= ((insn
>> 16) & 0x7f) | (insn
& 0x80);
1190 data8
= (insn
>> 8) & 0xff;
1191 opcode
= (insn
>> 27) & 7;
1192 operator = (insn
>> 24) & 7;
1193 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1194 opcode_names
[opcode
- 5], reg
,
1195 operator_names
[operator], data8
, s
->sfbr
,
1196 (insn
& (1 << 23)) ? " SFBR" : "");
1199 case 5: /* From SFBR */
1203 case 6: /* To SFBR */
1205 op0
= lsi_reg_readb(s
, reg
);
1208 case 7: /* Read-modify-write */
1210 op0
= lsi_reg_readb(s
, reg
);
1211 if (insn
& (1 << 23)) {
1223 case 1: /* Shift left */
1225 op0
= (op0
<< 1) | s
->carry
;
1239 op0
= (op0
>> 1) | (s
->carry
<< 7);
1244 s
->carry
= op0
< op1
;
1247 op0
+= op1
+ s
->carry
;
1249 s
->carry
= op0
<= op1
;
1251 s
->carry
= op0
< op1
;
1256 case 5: /* From SFBR */
1257 case 7: /* Read-modify-write */
1258 lsi_reg_writeb(s
, reg
, op0
);
1260 case 6: /* To SFBR */
1267 case 2: /* Transfer Control. */
1272 if ((insn
& 0x002e0000) == 0) {
1276 if (s
->sist1
& LSI_SIST1_STO
) {
1277 DPRINTF("Delayed select timeout\n");
1281 cond
= jmp
= (insn
& (1 << 19)) != 0;
1282 if (cond
== jmp
&& (insn
& (1 << 21))) {
1283 DPRINTF("Compare carry %d\n", s
->carry
== jmp
);
1284 cond
= s
->carry
!= 0;
1286 if (cond
== jmp
&& (insn
& (1 << 17))) {
1287 DPRINTF("Compare phase %d %c= %d\n",
1288 (s
->sstat1
& PHASE_MASK
),
1290 ((insn
>> 24) & 7));
1291 cond
= (s
->sstat1
& PHASE_MASK
) == ((insn
>> 24) & 7);
1293 if (cond
== jmp
&& (insn
& (1 << 18))) {
1296 mask
= (~insn
>> 8) & 0xff;
1297 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1298 s
->sfbr
, mask
, jmp
? '=' : '!', insn
& mask
);
1299 cond
= (s
->sfbr
& mask
) == (insn
& mask
);
1302 if (insn
& (1 << 23)) {
1303 /* Relative address. */
1304 addr
= s
->dsp
+ sxt24(addr
);
1306 switch ((insn
>> 27) & 7) {
1308 DPRINTF("Jump to 0x%08x\n", addr
);
1312 DPRINTF("Call 0x%08x\n", addr
);
1316 case 2: /* Return */
1317 DPRINTF("Return to 0x%08x\n", s
->temp
);
1320 case 3: /* Interrupt */
1321 DPRINTF("Interrupt 0x%08x\n", s
->dsps
);
1322 if ((insn
& (1 << 20)) != 0) {
1323 s
->istat0
|= LSI_ISTAT0_INTF
;
1326 lsi_script_dma_interrupt(s
, LSI_DSTAT_SIR
);
1330 DPRINTF("Illegal transfer control\n");
1331 lsi_script_dma_interrupt(s
, LSI_DSTAT_IID
);
1335 DPRINTF("Control condition failed\n");
1341 if ((insn
& (1 << 29)) == 0) {
1344 /* ??? The docs imply the destination address is loaded into
1345 the TEMP register. However the Linux drivers rely on
1346 the value being presrved. */
1347 dest
= read_dword(s
, s
->dsp
);
1349 lsi_memcpy(s
, dest
, addr
, insn
& 0xffffff);
1356 if (insn
& (1 << 28)) {
1357 addr
= s
->dsa
+ sxt24(addr
);
1360 reg
= (insn
>> 16) & 0xff;
1361 if (insn
& (1 << 24)) {
1362 cpu_physical_memory_read(addr
, data
, n
);
1363 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg
, n
,
1364 addr
, *(int *)data
);
1365 for (i
= 0; i
< n
; i
++) {
1366 lsi_reg_writeb(s
, reg
+ i
, data
[i
]);
1369 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg
, n
, addr
);
1370 for (i
= 0; i
< n
; i
++) {
1371 data
[i
] = lsi_reg_readb(s
, reg
+ i
);
1373 cpu_physical_memory_write(addr
, data
, n
);
1377 if (insn_processed
> 10000 && !s
->waiting
) {
1378 /* Some windows drivers make the device spin waiting for a memory
1379 location to change. If we have been executed a lot of code then
1380 assume this is the case and force an unexpected device disconnect.
1381 This is apparently sufficient to beat the drivers into submission.
1383 if (!(s
->sien0
& LSI_SIST0_UDC
))
1384 fprintf(stderr
, "inf. loop with UDC masked\n");
1385 lsi_script_scsi_interrupt(s
, LSI_SIST0_UDC
, 0);
1387 } else if (s
->istat1
& LSI_ISTAT1_SRUN
&& !s
->waiting
) {
1388 if (s
->dcntl
& LSI_DCNTL_SSM
) {
1389 lsi_script_dma_interrupt(s
, LSI_DSTAT_SSI
);
1394 DPRINTF("SCRIPTS execution stopped\n");
1397 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
)
1400 #define CASE_GET_REG24(name, addr) \
1401 case addr: return s->name & 0xff; \
1402 case addr + 1: return (s->name >> 8) & 0xff; \
1403 case addr + 2: return (s->name >> 16) & 0xff;
1405 #define CASE_GET_REG32(name, addr) \
1406 case addr: return s->name & 0xff; \
1407 case addr + 1: return (s->name >> 8) & 0xff; \
1408 case addr + 2: return (s->name >> 16) & 0xff; \
1409 case addr + 3: return (s->name >> 24) & 0xff;
1411 #ifdef DEBUG_LSI_REG
1412 DPRINTF("Read reg %x\n", offset
);
1415 case 0x00: /* SCNTL0 */
1417 case 0x01: /* SCNTL1 */
1419 case 0x02: /* SCNTL2 */
1421 case 0x03: /* SCNTL3 */
1423 case 0x04: /* SCID */
1425 case 0x05: /* SXFER */
1427 case 0x06: /* SDID */
1429 case 0x07: /* GPREG0 */
1431 case 0x08: /* Revision ID */
1433 case 0xa: /* SSID */
1435 case 0xb: /* SBCL */
1436 /* ??? This is not correct. However it's (hopefully) only
1437 used for diagnostics, so should be ok. */
1439 case 0xc: /* DSTAT */
1440 tmp
= s
->dstat
| 0x80;
1441 if ((s
->istat0
& LSI_ISTAT0_INTF
) == 0)
1445 case 0x0d: /* SSTAT0 */
1447 case 0x0e: /* SSTAT1 */
1449 case 0x0f: /* SSTAT2 */
1450 return s
->scntl1
& LSI_SCNTL1_CON
? 0 : 2;
1451 CASE_GET_REG32(dsa
, 0x10)
1452 case 0x14: /* ISTAT0 */
1454 case 0x15: /* ISTAT1 */
1456 case 0x16: /* MBOX0 */
1458 case 0x17: /* MBOX1 */
1460 case 0x18: /* CTEST0 */
1462 case 0x19: /* CTEST1 */
1464 case 0x1a: /* CTEST2 */
1465 tmp
= s
->ctest2
| LSI_CTEST2_DACK
| LSI_CTEST2_CM
;
1466 if (s
->istat0
& LSI_ISTAT0_SIGP
) {
1467 s
->istat0
&= ~LSI_ISTAT0_SIGP
;
1468 tmp
|= LSI_CTEST2_SIGP
;
1471 case 0x1b: /* CTEST3 */
1473 CASE_GET_REG32(temp
, 0x1c)
1474 case 0x20: /* DFIFO */
1476 case 0x21: /* CTEST4 */
1478 case 0x22: /* CTEST5 */
1480 case 0x23: /* CTEST6 */
1482 CASE_GET_REG24(dbc
, 0x24)
1483 case 0x27: /* DCMD */
1485 CASE_GET_REG32(dnad
, 0x28)
1486 CASE_GET_REG32(dsp
, 0x2c)
1487 CASE_GET_REG32(dsps
, 0x30)
1488 CASE_GET_REG32(scratch
[0], 0x34)
1489 case 0x38: /* DMODE */
1491 case 0x39: /* DIEN */
1493 case 0x3a: /* SBR */
1495 case 0x3b: /* DCNTL */
1497 case 0x40: /* SIEN0 */
1499 case 0x41: /* SIEN1 */
1501 case 0x42: /* SIST0 */
1506 case 0x43: /* SIST1 */
1511 case 0x46: /* MACNTL */
1513 case 0x47: /* GPCNTL0 */
1515 case 0x48: /* STIME0 */
1517 case 0x4a: /* RESPID0 */
1519 case 0x4b: /* RESPID1 */
1521 case 0x4d: /* STEST1 */
1523 case 0x4e: /* STEST2 */
1525 case 0x4f: /* STEST3 */
1527 case 0x50: /* SIDL */
1528 /* This is needed by the linux drivers. We currently only update it
1529 during the MSG IN phase. */
1531 case 0x52: /* STEST4 */
1533 case 0x56: /* CCNTL0 */
1535 case 0x57: /* CCNTL1 */
1537 case 0x58: /* SBDL */
1538 /* Some drivers peek at the data bus during the MSG IN phase. */
1539 if ((s
->sstat1
& PHASE_MASK
) == PHASE_MI
)
1542 case 0x59: /* SBDL high */
1544 CASE_GET_REG32(mmrs
, 0xa0)
1545 CASE_GET_REG32(mmws
, 0xa4)
1546 CASE_GET_REG32(sfs
, 0xa8)
1547 CASE_GET_REG32(drs
, 0xac)
1548 CASE_GET_REG32(sbms
, 0xb0)
1549 CASE_GET_REG32(dbms
, 0xb4)
1550 CASE_GET_REG32(dnad64
, 0xb8)
1551 CASE_GET_REG32(pmjad1
, 0xc0)
1552 CASE_GET_REG32(pmjad2
, 0xc4)
1553 CASE_GET_REG32(rbc
, 0xc8)
1554 CASE_GET_REG32(ua
, 0xcc)
1555 CASE_GET_REG32(ia
, 0xd4)
1556 CASE_GET_REG32(sbc
, 0xd8)
1557 CASE_GET_REG32(csbc
, 0xdc)
1559 if (offset
>= 0x5c && offset
< 0xa0) {
1562 n
= (offset
- 0x58) >> 2;
1563 shift
= (offset
& 3) * 8;
1564 return (s
->scratch
[n
] >> shift
) & 0xff;
1566 BADF("readb 0x%x\n", offset
);
1568 #undef CASE_GET_REG24
1569 #undef CASE_GET_REG32
1572 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
)
1574 #define CASE_SET_REG24(name, addr) \
1575 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1576 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1577 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1579 #define CASE_SET_REG32(name, addr) \
1580 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1581 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1582 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1583 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1585 #ifdef DEBUG_LSI_REG
1586 DPRINTF("Write reg %x = %02x\n", offset
, val
);
1589 case 0x00: /* SCNTL0 */
1591 if (val
& LSI_SCNTL0_START
) {
1592 BADF("Start sequence not implemented\n");
1595 case 0x01: /* SCNTL1 */
1596 s
->scntl1
= val
& ~LSI_SCNTL1_SST
;
1597 if (val
& LSI_SCNTL1_IARB
) {
1598 BADF("Immediate Arbritration not implemented\n");
1600 if (val
& LSI_SCNTL1_RST
) {
1601 if (!(s
->sstat0
& LSI_SSTAT0_RST
)) {
1605 for (id
= 0; id
< s
->bus
.ndev
; id
++) {
1606 if (s
->bus
.devs
[id
]) {
1607 dev
= &s
->bus
.devs
[id
]->qdev
;
1608 dev
->info
->reset(dev
);
1611 s
->sstat0
|= LSI_SSTAT0_RST
;
1612 lsi_script_scsi_interrupt(s
, LSI_SIST0_RST
, 0);
1615 s
->sstat0
&= ~LSI_SSTAT0_RST
;
1618 case 0x02: /* SCNTL2 */
1619 val
&= ~(LSI_SCNTL2_WSR
| LSI_SCNTL2_WSS
);
1622 case 0x03: /* SCNTL3 */
1625 case 0x04: /* SCID */
1628 case 0x05: /* SXFER */
1631 case 0x06: /* SDID */
1632 if ((val
& 0xf) != (s
->ssid
& 0xf))
1633 BADF("Destination ID does not match SSID\n");
1634 s
->sdid
= val
& 0xf;
1636 case 0x07: /* GPREG0 */
1638 case 0x08: /* SFBR */
1639 /* The CPU is not allowed to write to this register. However the
1640 SCRIPTS register move instructions are. */
1643 case 0x0a: case 0x0b:
1644 /* Openserver writes to these readonly registers on startup */
1646 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1647 /* Linux writes to these readonly registers on startup. */
1649 CASE_SET_REG32(dsa
, 0x10)
1650 case 0x14: /* ISTAT0 */
1651 s
->istat0
= (s
->istat0
& 0x0f) | (val
& 0xf0);
1652 if (val
& LSI_ISTAT0_ABRT
) {
1653 lsi_script_dma_interrupt(s
, LSI_DSTAT_ABRT
);
1655 if (val
& LSI_ISTAT0_INTF
) {
1656 s
->istat0
&= ~LSI_ISTAT0_INTF
;
1659 if (s
->waiting
== 1 && val
& LSI_ISTAT0_SIGP
) {
1660 DPRINTF("Woken by SIGP\n");
1663 lsi_execute_script(s
);
1665 if (val
& LSI_ISTAT0_SRST
) {
1669 case 0x16: /* MBOX0 */
1672 case 0x17: /* MBOX1 */
1675 case 0x1a: /* CTEST2 */
1676 s
->ctest2
= val
& LSI_CTEST2_PCICIE
;
1678 case 0x1b: /* CTEST3 */
1679 s
->ctest3
= val
& 0x0f;
1681 CASE_SET_REG32(temp
, 0x1c)
1682 case 0x21: /* CTEST4 */
1684 BADF("Unimplemented CTEST4-FBL 0x%x\n", val
);
1688 case 0x22: /* CTEST5 */
1689 if (val
& (LSI_CTEST5_ADCK
| LSI_CTEST5_BBCK
)) {
1690 BADF("CTEST5 DMA increment not implemented\n");
1694 CASE_SET_REG24(dbc
, 0x24)
1695 CASE_SET_REG32(dnad
, 0x28)
1696 case 0x2c: /* DSP[0:7] */
1697 s
->dsp
&= 0xffffff00;
1700 case 0x2d: /* DSP[8:15] */
1701 s
->dsp
&= 0xffff00ff;
1704 case 0x2e: /* DSP[16:23] */
1705 s
->dsp
&= 0xff00ffff;
1706 s
->dsp
|= val
<< 16;
1708 case 0x2f: /* DSP[24:31] */
1709 s
->dsp
&= 0x00ffffff;
1710 s
->dsp
|= val
<< 24;
1711 if ((s
->dmode
& LSI_DMODE_MAN
) == 0
1712 && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1713 lsi_execute_script(s
);
1715 CASE_SET_REG32(dsps
, 0x30)
1716 CASE_SET_REG32(scratch
[0], 0x34)
1717 case 0x38: /* DMODE */
1718 if (val
& (LSI_DMODE_SIOM
| LSI_DMODE_DIOM
)) {
1719 BADF("IO mappings not implemented\n");
1723 case 0x39: /* DIEN */
1727 case 0x3a: /* SBR */
1730 case 0x3b: /* DCNTL */
1731 s
->dcntl
= val
& ~(LSI_DCNTL_PFF
| LSI_DCNTL_STD
);
1732 if ((val
& LSI_DCNTL_STD
) && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1733 lsi_execute_script(s
);
1735 case 0x40: /* SIEN0 */
1739 case 0x41: /* SIEN1 */
1743 case 0x47: /* GPCNTL0 */
1745 case 0x48: /* STIME0 */
1748 case 0x49: /* STIME1 */
1750 DPRINTF("General purpose timer not implemented\n");
1751 /* ??? Raising the interrupt immediately seems to be sufficient
1752 to keep the FreeBSD driver happy. */
1753 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_GEN
);
1756 case 0x4a: /* RESPID0 */
1759 case 0x4b: /* RESPID1 */
1762 case 0x4d: /* STEST1 */
1765 case 0x4e: /* STEST2 */
1767 BADF("Low level mode not implemented\n");
1771 case 0x4f: /* STEST3 */
1773 BADF("SCSI FIFO test mode not implemented\n");
1777 case 0x56: /* CCNTL0 */
1780 case 0x57: /* CCNTL1 */
1783 CASE_SET_REG32(mmrs
, 0xa0)
1784 CASE_SET_REG32(mmws
, 0xa4)
1785 CASE_SET_REG32(sfs
, 0xa8)
1786 CASE_SET_REG32(drs
, 0xac)
1787 CASE_SET_REG32(sbms
, 0xb0)
1788 CASE_SET_REG32(dbms
, 0xb4)
1789 CASE_SET_REG32(dnad64
, 0xb8)
1790 CASE_SET_REG32(pmjad1
, 0xc0)
1791 CASE_SET_REG32(pmjad2
, 0xc4)
1792 CASE_SET_REG32(rbc
, 0xc8)
1793 CASE_SET_REG32(ua
, 0xcc)
1794 CASE_SET_REG32(ia
, 0xd4)
1795 CASE_SET_REG32(sbc
, 0xd8)
1796 CASE_SET_REG32(csbc
, 0xdc)
1798 if (offset
>= 0x5c && offset
< 0xa0) {
1801 n
= (offset
- 0x58) >> 2;
1802 shift
= (offset
& 3) * 8;
1803 s
->scratch
[n
] &= ~(0xff << shift
);
1804 s
->scratch
[n
] |= (val
& 0xff) << shift
;
1806 BADF("Unhandled writeb 0x%x = 0x%x\n", offset
, val
);
1809 #undef CASE_SET_REG24
1810 #undef CASE_SET_REG32
1813 static void lsi_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1815 LSIState
*s
= opaque
;
1817 lsi_reg_writeb(s
, addr
& 0xff, val
);
1820 static void lsi_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1822 LSIState
*s
= opaque
;
1825 lsi_reg_writeb(s
, addr
, val
& 0xff);
1826 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1829 static void lsi_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1831 LSIState
*s
= opaque
;
1834 lsi_reg_writeb(s
, addr
, val
& 0xff);
1835 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
1836 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
1837 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
1840 static uint32_t lsi_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1842 LSIState
*s
= opaque
;
1844 return lsi_reg_readb(s
, addr
& 0xff);
1847 static uint32_t lsi_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1849 LSIState
*s
= opaque
;
1853 val
= lsi_reg_readb(s
, addr
);
1854 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1858 static uint32_t lsi_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1860 LSIState
*s
= opaque
;
1863 val
= lsi_reg_readb(s
, addr
);
1864 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1865 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1866 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1870 static CPUReadMemoryFunc
* const lsi_mmio_readfn
[3] = {
1876 static CPUWriteMemoryFunc
* const lsi_mmio_writefn
[3] = {
1882 static void lsi_ram_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1884 LSIState
*s
= opaque
;
1889 newval
= s
->script_ram
[addr
>> 2];
1890 shift
= (addr
& 3) * 8;
1891 newval
&= ~(0xff << shift
);
1892 newval
|= val
<< shift
;
1893 s
->script_ram
[addr
>> 2] = newval
;
1896 static void lsi_ram_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1898 LSIState
*s
= opaque
;
1902 newval
= s
->script_ram
[addr
>> 2];
1904 newval
= (newval
& 0xffff) | (val
<< 16);
1906 newval
= (newval
& 0xffff0000) | val
;
1908 s
->script_ram
[addr
>> 2] = newval
;
1912 static void lsi_ram_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1914 LSIState
*s
= opaque
;
1917 s
->script_ram
[addr
>> 2] = val
;
1920 static uint32_t lsi_ram_readb(void *opaque
, target_phys_addr_t addr
)
1922 LSIState
*s
= opaque
;
1926 val
= s
->script_ram
[addr
>> 2];
1927 val
>>= (addr
& 3) * 8;
1931 static uint32_t lsi_ram_readw(void *opaque
, target_phys_addr_t addr
)
1933 LSIState
*s
= opaque
;
1937 val
= s
->script_ram
[addr
>> 2];
1943 static uint32_t lsi_ram_readl(void *opaque
, target_phys_addr_t addr
)
1945 LSIState
*s
= opaque
;
1948 return s
->script_ram
[addr
>> 2];
1951 static CPUReadMemoryFunc
* const lsi_ram_readfn
[3] = {
1957 static CPUWriteMemoryFunc
* const lsi_ram_writefn
[3] = {
1963 static uint32_t lsi_io_readb(void *opaque
, uint32_t addr
)
1965 LSIState
*s
= opaque
;
1966 return lsi_reg_readb(s
, addr
& 0xff);
1969 static uint32_t lsi_io_readw(void *opaque
, uint32_t addr
)
1971 LSIState
*s
= opaque
;
1974 val
= lsi_reg_readb(s
, addr
);
1975 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1979 static uint32_t lsi_io_readl(void *opaque
, uint32_t addr
)
1981 LSIState
*s
= opaque
;
1984 val
= lsi_reg_readb(s
, addr
);
1985 val
|= lsi_reg_readb(s
, addr
+ 1) << 8;
1986 val
|= lsi_reg_readb(s
, addr
+ 2) << 16;
1987 val
|= lsi_reg_readb(s
, addr
+ 3) << 24;
1991 static void lsi_io_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
1993 LSIState
*s
= opaque
;
1994 lsi_reg_writeb(s
, addr
& 0xff, val
);
1997 static void lsi_io_writew(void *opaque
, uint32_t addr
, uint32_t val
)
1999 LSIState
*s
= opaque
;
2001 lsi_reg_writeb(s
, addr
, val
& 0xff);
2002 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
2005 static void lsi_io_writel(void *opaque
, uint32_t addr
, uint32_t val
)
2007 LSIState
*s
= opaque
;
2009 lsi_reg_writeb(s
, addr
, val
& 0xff);
2010 lsi_reg_writeb(s
, addr
+ 1, (val
>> 8) & 0xff);
2011 lsi_reg_writeb(s
, addr
+ 2, (val
>> 16) & 0xff);
2012 lsi_reg_writeb(s
, addr
+ 3, (val
>> 24) & 0xff);
2015 static void lsi_io_mapfunc(PCIDevice
*pci_dev
, int region_num
,
2016 pcibus_t addr
, pcibus_t size
, int type
)
2018 LSIState
*s
= DO_UPCAST(LSIState
, dev
, pci_dev
);
2020 DPRINTF("Mapping IO at %08"FMT_PCIBUS
"\n", addr
);
2022 register_ioport_write(addr
, 256, 1, lsi_io_writeb
, s
);
2023 register_ioport_read(addr
, 256, 1, lsi_io_readb
, s
);
2024 register_ioport_write(addr
, 256, 2, lsi_io_writew
, s
);
2025 register_ioport_read(addr
, 256, 2, lsi_io_readw
, s
);
2026 register_ioport_write(addr
, 256, 4, lsi_io_writel
, s
);
2027 register_ioport_read(addr
, 256, 4, lsi_io_readl
, s
);
2030 static void lsi_ram_mapfunc(PCIDevice
*pci_dev
, int region_num
,
2031 pcibus_t addr
, pcibus_t size
, int type
)
2033 LSIState
*s
= DO_UPCAST(LSIState
, dev
, pci_dev
);
2035 DPRINTF("Mapping ram at %08"FMT_PCIBUS
"\n", addr
);
2036 s
->script_ram_base
= addr
;
2037 cpu_register_physical_memory(addr
+ 0, 0x2000, s
->ram_io_addr
);
2040 static void lsi_scsi_reset(DeviceState
*dev
)
2042 LSIState
*s
= DO_UPCAST(LSIState
, dev
.qdev
, dev
);
2047 static void lsi_pre_save(void *opaque
)
2049 LSIState
*s
= opaque
;
2052 assert(s
->current
->dma_buf
== NULL
);
2053 assert(s
->current
->dma_len
== 0);
2055 assert(QTAILQ_EMPTY(&s
->queue
));
2058 static const VMStateDescription vmstate_lsi_scsi
= {
2061 .minimum_version_id
= 0,
2062 .minimum_version_id_old
= 0,
2063 .pre_save
= lsi_pre_save
,
2064 .fields
= (VMStateField
[]) {
2065 VMSTATE_PCI_DEVICE(dev
, LSIState
),
2067 VMSTATE_INT32(carry
, LSIState
),
2068 VMSTATE_INT32(sense
, LSIState
),
2069 VMSTATE_INT32(msg_action
, LSIState
),
2070 VMSTATE_INT32(msg_len
, LSIState
),
2071 VMSTATE_BUFFER(msg
, LSIState
),
2072 VMSTATE_INT32(waiting
, LSIState
),
2074 VMSTATE_UINT32(dsa
, LSIState
),
2075 VMSTATE_UINT32(temp
, LSIState
),
2076 VMSTATE_UINT32(dnad
, LSIState
),
2077 VMSTATE_UINT32(dbc
, LSIState
),
2078 VMSTATE_UINT8(istat0
, LSIState
),
2079 VMSTATE_UINT8(istat1
, LSIState
),
2080 VMSTATE_UINT8(dcmd
, LSIState
),
2081 VMSTATE_UINT8(dstat
, LSIState
),
2082 VMSTATE_UINT8(dien
, LSIState
),
2083 VMSTATE_UINT8(sist0
, LSIState
),
2084 VMSTATE_UINT8(sist1
, LSIState
),
2085 VMSTATE_UINT8(sien0
, LSIState
),
2086 VMSTATE_UINT8(sien1
, LSIState
),
2087 VMSTATE_UINT8(mbox0
, LSIState
),
2088 VMSTATE_UINT8(mbox1
, LSIState
),
2089 VMSTATE_UINT8(dfifo
, LSIState
),
2090 VMSTATE_UINT8(ctest2
, LSIState
),
2091 VMSTATE_UINT8(ctest3
, LSIState
),
2092 VMSTATE_UINT8(ctest4
, LSIState
),
2093 VMSTATE_UINT8(ctest5
, LSIState
),
2094 VMSTATE_UINT8(ccntl0
, LSIState
),
2095 VMSTATE_UINT8(ccntl1
, LSIState
),
2096 VMSTATE_UINT32(dsp
, LSIState
),
2097 VMSTATE_UINT32(dsps
, LSIState
),
2098 VMSTATE_UINT8(dmode
, LSIState
),
2099 VMSTATE_UINT8(dcntl
, LSIState
),
2100 VMSTATE_UINT8(scntl0
, LSIState
),
2101 VMSTATE_UINT8(scntl1
, LSIState
),
2102 VMSTATE_UINT8(scntl2
, LSIState
),
2103 VMSTATE_UINT8(scntl3
, LSIState
),
2104 VMSTATE_UINT8(sstat0
, LSIState
),
2105 VMSTATE_UINT8(sstat1
, LSIState
),
2106 VMSTATE_UINT8(scid
, LSIState
),
2107 VMSTATE_UINT8(sxfer
, LSIState
),
2108 VMSTATE_UINT8(socl
, LSIState
),
2109 VMSTATE_UINT8(sdid
, LSIState
),
2110 VMSTATE_UINT8(ssid
, LSIState
),
2111 VMSTATE_UINT8(sfbr
, LSIState
),
2112 VMSTATE_UINT8(stest1
, LSIState
),
2113 VMSTATE_UINT8(stest2
, LSIState
),
2114 VMSTATE_UINT8(stest3
, LSIState
),
2115 VMSTATE_UINT8(sidl
, LSIState
),
2116 VMSTATE_UINT8(stime0
, LSIState
),
2117 VMSTATE_UINT8(respid0
, LSIState
),
2118 VMSTATE_UINT8(respid1
, LSIState
),
2119 VMSTATE_UINT32(mmrs
, LSIState
),
2120 VMSTATE_UINT32(mmws
, LSIState
),
2121 VMSTATE_UINT32(sfs
, LSIState
),
2122 VMSTATE_UINT32(drs
, LSIState
),
2123 VMSTATE_UINT32(sbms
, LSIState
),
2124 VMSTATE_UINT32(dbms
, LSIState
),
2125 VMSTATE_UINT32(dnad64
, LSIState
),
2126 VMSTATE_UINT32(pmjad1
, LSIState
),
2127 VMSTATE_UINT32(pmjad2
, LSIState
),
2128 VMSTATE_UINT32(rbc
, LSIState
),
2129 VMSTATE_UINT32(ua
, LSIState
),
2130 VMSTATE_UINT32(ia
, LSIState
),
2131 VMSTATE_UINT32(sbc
, LSIState
),
2132 VMSTATE_UINT32(csbc
, LSIState
),
2133 VMSTATE_BUFFER_UNSAFE(scratch
, LSIState
, 0, 18 * sizeof(uint32_t)),
2134 VMSTATE_UINT8(sbr
, LSIState
),
2136 VMSTATE_BUFFER_UNSAFE(script_ram
, LSIState
, 0, 2048 * sizeof(uint32_t)),
2137 VMSTATE_END_OF_LIST()
2141 static int lsi_scsi_uninit(PCIDevice
*d
)
2143 LSIState
*s
= DO_UPCAST(LSIState
, dev
, d
);
2145 cpu_unregister_io_memory(s
->mmio_io_addr
);
2146 cpu_unregister_io_memory(s
->ram_io_addr
);
2151 static int lsi_scsi_init(PCIDevice
*dev
)
2153 LSIState
*s
= DO_UPCAST(LSIState
, dev
, dev
);
2156 pci_conf
= s
->dev
.config
;
2158 /* PCI Vendor ID (word) */
2159 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_LSI_LOGIC
);
2160 /* PCI device ID (word) */
2161 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_LSI_53C895A
);
2162 /* PCI base class code */
2163 pci_config_set_class(pci_conf
, PCI_CLASS_STORAGE_SCSI
);
2164 /* PCI subsystem ID */
2165 pci_conf
[PCI_SUBSYSTEM_ID
] = 0x00;
2166 pci_conf
[PCI_SUBSYSTEM_ID
+ 1] = 0x10;
2167 /* PCI latency timer = 255 */
2168 pci_conf
[PCI_LATENCY_TIMER
] = 0xff;
2169 /* TODO: RST# value should be 0 */
2170 /* Interrupt pin 1 */
2171 pci_conf
[PCI_INTERRUPT_PIN
] = 0x01;
2173 s
->mmio_io_addr
= cpu_register_io_memory(lsi_mmio_readfn
,
2174 lsi_mmio_writefn
, s
,
2175 DEVICE_NATIVE_ENDIAN
);
2176 s
->ram_io_addr
= cpu_register_io_memory(lsi_ram_readfn
,
2178 DEVICE_NATIVE_ENDIAN
);
2180 pci_register_bar(&s
->dev
, 0, 256,
2181 PCI_BASE_ADDRESS_SPACE_IO
, lsi_io_mapfunc
);
2182 pci_register_bar_simple(&s
->dev
, 1, 0x400, 0, s
->mmio_io_addr
);
2183 pci_register_bar(&s
->dev
, 2, 0x2000,
2184 PCI_BASE_ADDRESS_SPACE_MEMORY
, lsi_ram_mapfunc
);
2185 QTAILQ_INIT(&s
->queue
);
2187 scsi_bus_new(&s
->bus
, &dev
->qdev
, 1, LSI_MAX_DEVS
, lsi_command_complete
);
2188 if (!dev
->qdev
.hotplugged
) {
2189 return scsi_bus_legacy_handle_cmdline(&s
->bus
);
2194 static PCIDeviceInfo lsi_info
= {
2195 .qdev
.name
= "lsi53c895a",
2196 .qdev
.alias
= "lsi",
2197 .qdev
.size
= sizeof(LSIState
),
2198 .qdev
.reset
= lsi_scsi_reset
,
2199 .qdev
.vmsd
= &vmstate_lsi_scsi
,
2200 .init
= lsi_scsi_init
,
2201 .exit
= lsi_scsi_uninit
,
2204 static void lsi53c895a_register_devices(void)
2206 pci_qdev_register(&lsi_info
);
2209 device_init(lsi53c895a_register_devices
);