hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  96
  97 #define XMIT_FIFO           0
  98 #define RECV_FIFO           1
  99 #define MAX_XMIT_RETRY      4
 100
 101 typedef struct SerialFIFO {
 102     uint8_t data[UART_FIFO_LENGTH];
 103     uint8_t count;
 104     uint8_t itl;                        /* Interrupt Trigger Level */
 105     uint8_t tail;
 106     uint8_t head;
 107 } SerialFIFO;
 108
 109 struct SerialState {
 110     uint16_t divider;
 111     uint8_t rbr; /* receive register */
 112     uint8_t thr; /* transmit holding register */
 113     uint8_t tsr; /* transmit shift register */
 114     uint8_t ier;
 115     uint8_t iir; /* read only */
 116     uint8_t lcr;
 117     uint8_t mcr;
 118     uint8_t lsr; /* read only */
 119     uint8_t msr; /* read only */
 120     uint8_t scr;
 121     uint8_t fcr;
 122     uint8_t fcr_vmstate; /* we can't write directly this value
 123                             it has side effects */
 124     /* NOTE: this hidden state is necessary for tx irq generation as
 125        it can be reset while reading iir */
 126     int thr_ipending;
 127     qemu_irq irq;
 128     CharDriverState *chr;
 129     int last_break_enable;
 130     int it_shift;
 131     int baudbase;
 132     int tsr_retry;
 133
 134     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 135     SerialFIFO recv_fifo;
 136     SerialFIFO xmit_fifo;
 137
 138     struct QEMUTimer *fifo_timeout_timer;
 139     int timeout_ipending;                   /* timeout interrupt pending state */
 140     struct QEMUTimer *transmit_timer;
 141
 142
 143     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 144     int poll_msl;
 145
 146     struct QEMUTimer *modem_status_poll;
 147 };
 148
 149 typedef struct ISASerialState {
 150     ISADevice dev;
 151     uint32_t index;
 152     uint32_t iobase;
 153     uint32_t isairq;
 154     SerialState state;
 155 } ISASerialState;
 156
 157 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 158
 159 static void fifo_clear(SerialState *s, int fifo)
 160 {
 161     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 162     memset(f->data, 0, UART_FIFO_LENGTH);
 163     f->count = 0;
 164     f->head = 0;
 165     f->tail = 0;
 166 }
 167
 168 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 169 {
 170     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 171
 172     /* Receive overruns do not overwrite FIFO contents. */
 173     if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
 174
 175         f->data[f->head++] = chr;
 176
 177         if (f->head == UART_FIFO_LENGTH)
 178             f->head = 0;
 179     }
 180
 181     if (f->count < UART_FIFO_LENGTH)
 182         f->count++;
 183     else if (fifo == RECV_FIFO)
 184         s->lsr |= UART_LSR_OE;
 185
 186     return 1;
 187 }
 188
 189 static uint8_t fifo_get(SerialState *s, int fifo)
 190 {
 191     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 192     uint8_t c;
 193
 194     if(f->count == 0)
 195         return 0;
 196
 197     c = f->data[f->tail++];
 198     if (f->tail == UART_FIFO_LENGTH)
 199         f->tail = 0;
 200     f->count--;
 201
 202     return c;
 203 }
 204
 205 static void serial_update_irq(SerialState *s)
 206 {
 207     uint8_t tmp_iir = UART_IIR_NO_INT;
 208
 209     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 210         tmp_iir = UART_IIR_RLSI;
 211     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 212         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 213          * this is not in the specification but is observed on existing
 214          * hardware.  */
 215         tmp_iir = UART_IIR_CTI;
 216     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 217                (!(s->fcr & UART_FCR_FE) ||
 218                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 219         tmp_iir = UART_IIR_RDI;
 220     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 221         tmp_iir = UART_IIR_THRI;
 222     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 223         tmp_iir = UART_IIR_MSI;
 224     }
 225
 226     s->iir = tmp_iir | (s->iir & 0xF0);
 227
 228     if (tmp_iir != UART_IIR_NO_INT) {
 229         qemu_irq_raise(s->irq);
 230     } else {
 231         qemu_irq_lower(s->irq);
 232     }
 233 }
 234
 235 static void serial_update_parameters(SerialState *s)
 236 {
 237     int speed, parity, data_bits, stop_bits, frame_size;
 238     QEMUSerialSetParams ssp;
 239
 240     if (s->divider == 0)
 241         return;
 242
 243     /* Start bit. */
 244     frame_size = 1;
 245     if (s->lcr & 0x08) {
 246         /* Parity bit. */
 247         frame_size++;
 248         if (s->lcr & 0x10)
 249             parity = 'E';
 250         else
 251             parity = 'O';
 252     } else {
 253             parity = 'N';
 254     }
 255     if (s->lcr & 0x04)
 256         stop_bits = 2;
 257     else
 258         stop_bits = 1;
 259
 260     data_bits = (s->lcr & 0x03) + 5;
 261     frame_size += data_bits + stop_bits;
 262     speed = s->baudbase / s->divider;
 263     ssp.speed = speed;
 264     ssp.parity = parity;
 265     ssp.data_bits = data_bits;
 266     ssp.stop_bits = stop_bits;
 267     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 268     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 269 #if 0
 270     printf("speed=%d parity=%c data=%d stop=%d\n",
 271            speed, parity, data_bits, stop_bits);
 272 #endif
 273 }
 274
 275 static void serial_update_msl(SerialState *s)
 276 {
 277     uint8_t omsr;
 278     int flags;
 279
 280     qemu_del_timer(s->modem_status_poll);
 281
 282     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 283         s->poll_msl = -1;
 284         return;
 285     }
 286
 287     omsr = s->msr;
 288
 289     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 290     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 291     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 292     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 293
 294     if (s->msr != omsr) {
 295          /* Set delta bits */
 296          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 297          /* UART_MSR_TERI only if change was from 1 -> 0 */
 298          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 299              s->msr &= ~UART_MSR_TERI;
 300          serial_update_irq(s);
 301     }
 302
 303     /* The real 16550A apparently has a 250ns response latency to line status changes.
 304        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 305
 306     if (s->poll_msl)
 307         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
 308 }
 309
 310 static void serial_xmit(void *opaque)
 311 {
 312     SerialState *s = opaque;
 313     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 314
 315     if (s->tsr_retry <= 0) {
 316         if (s->fcr & UART_FCR_FE) {
 317             s->tsr = fifo_get(s,XMIT_FIFO);
 318             if (!s->xmit_fifo.count)
 319                 s->lsr |= UART_LSR_THRE;
 320         } else {
 321             s->tsr = s->thr;
 322             s->lsr |= UART_LSR_THRE;
 323         }
 324     }
 325
 326     if (s->mcr & UART_MCR_LOOP) {
 327         /* in loopback mode, say that we just received a char */
 328         serial_receive1(s, &s->tsr, 1);
 329     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 330         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 331             s->tsr_retry++;
 332             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 333             return;
 334         } else if (s->poll_msl < 0) {
 335             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 336             drop any further failed writes instantly, until we get one that goes through.
 337             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 338             s->tsr_retry = -1;
 339         }
 340     }
 341     else {
 342         s->tsr_retry = 0;
 343     }
 344
 345     s->last_xmit_ts = qemu_get_clock(vm_clock);
 346     if (!(s->lsr & UART_LSR_THRE))
 347         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 348
 349     if (s->lsr & UART_LSR_THRE) {
 350         s->lsr |= UART_LSR_TEMT;
 351         s->thr_ipending = 1;
 352         serial_update_irq(s);
 353     }
 354 }
 355
 356
 357 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 358 {
 359     SerialState *s = opaque;
 360
 361     addr &= 7;
 362 #ifdef DEBUG_SERIAL
 363     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 364 #endif
 365     switch(addr) {
 366     default:
 367     case 0:
 368         if (s->lcr & UART_LCR_DLAB) {
 369             s->divider = (s->divider & 0xff00) | val;
 370             serial_update_parameters(s);
 371         } else {
 372             s->thr = (uint8_t) val;
 373             if(s->fcr & UART_FCR_FE) {
 374                 fifo_put(s, XMIT_FIFO, s->thr);
 375                 s->thr_ipending = 0;
 376                 s->lsr &= ~UART_LSR_TEMT;
 377                 s->lsr &= ~UART_LSR_THRE;
 378                 serial_update_irq(s);
 379             } else {
 380                 s->thr_ipending = 0;
 381                 s->lsr &= ~UART_LSR_THRE;
 382                 serial_update_irq(s);
 383             }
 384             serial_xmit(s);
 385         }
 386         break;
 387     case 1:
 388         if (s->lcr & UART_LCR_DLAB) {
 389             s->divider = (s->divider & 0x00ff) | (val << 8);
 390             serial_update_parameters(s);
 391         } else {
 392             s->ier = val & 0x0f;
 393             /* If the backend device is a real serial port, turn polling of the modem
 394                status lines on physical port on or off depending on UART_IER_MSI state */
 395             if (s->poll_msl >= 0) {
 396                 if (s->ier & UART_IER_MSI) {
 397                      s->poll_msl = 1;
 398                      serial_update_msl(s);
 399                 } else {
 400                      qemu_del_timer(s->modem_status_poll);
 401                      s->poll_msl = 0;
 402                 }
 403             }
 404             if (s->lsr & UART_LSR_THRE) {
 405                 s->thr_ipending = 1;
 406                 serial_update_irq(s);
 407             }
 408         }
 409         break;
 410     case 2:
 411         val = val & 0xFF;
 412
 413         if (s->fcr == val)
 414             break;
 415
 416         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 417         if ((val ^ s->fcr) & UART_FCR_FE)
 418             val |= UART_FCR_XFR | UART_FCR_RFR;
 419
 420         /* FIFO clear */
 421
 422         if (val & UART_FCR_RFR) {
 423             qemu_del_timer(s->fifo_timeout_timer);
 424             s->timeout_ipending=0;
 425             fifo_clear(s,RECV_FIFO);
 426         }
 427
 428         if (val & UART_FCR_XFR) {
 429             fifo_clear(s,XMIT_FIFO);
 430         }
 431
 432         if (val & UART_FCR_FE) {
 433             s->iir |= UART_IIR_FE;
 434             /* Set RECV_FIFO trigger Level */
 435             switch (val & 0xC0) {
 436             case UART_FCR_ITL_1:
 437                 s->recv_fifo.itl = 1;
 438                 break;
 439             case UART_FCR_ITL_2:
 440                 s->recv_fifo.itl = 4;
 441                 break;
 442             case UART_FCR_ITL_3:
 443                 s->recv_fifo.itl = 8;
 444                 break;
 445             case UART_FCR_ITL_4:
 446                 s->recv_fifo.itl = 14;
 447                 break;
 448             }
 449         } else
 450             s->iir &= ~UART_IIR_FE;
 451
 452         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 453         s->fcr = val & 0xC9;
 454         serial_update_irq(s);
 455         break;
 456     case 3:
 457         {
 458             int break_enable;
 459             s->lcr = val;
 460             serial_update_parameters(s);
 461             break_enable = (val >> 6) & 1;
 462             if (break_enable != s->last_break_enable) {
 463                 s->last_break_enable = break_enable;
 464                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 465                                &break_enable);
 466             }
 467         }
 468         break;
 469     case 4:
 470         {
 471             int flags;
 472             int old_mcr = s->mcr;
 473             s->mcr = val & 0x1f;
 474             if (val & UART_MCR_LOOP)
 475                 break;
 476
 477             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 478
 479                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 480
 481                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 482
 483                 if (val & UART_MCR_RTS)
 484                     flags |= CHR_TIOCM_RTS;
 485                 if (val & UART_MCR_DTR)
 486                     flags |= CHR_TIOCM_DTR;
 487
 488                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 489                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 490                    from the device/computer at the other end of the serial line */
 491                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 492             }
 493         }
 494         break;
 495     case 5:
 496         break;
 497     case 6:
 498         break;
 499     case 7:
 500         s->scr = val;
 501         break;
 502     }
 503 }
 504
 505 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 506 {
 507     SerialState *s = opaque;
 508     uint32_t ret;
 509
 510     addr &= 7;
 511     switch(addr) {
 512     default:
 513     case 0:
 514         if (s->lcr & UART_LCR_DLAB) {
 515             ret = s->divider & 0xff;
 516         } else {
 517             if(s->fcr & UART_FCR_FE) {
 518                 ret = fifo_get(s,RECV_FIFO);
 519                 if (s->recv_fifo.count == 0)
 520                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 521                 else
 522                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 523                 s->timeout_ipending = 0;
 524             } else {
 525                 ret = s->rbr;
 526                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 527             }
 528             serial_update_irq(s);
 529             if (!(s->mcr & UART_MCR_LOOP)) {
 530                 /* in loopback mode, don't receive any data */
 531                 qemu_chr_accept_input(s->chr);
 532             }
 533         }
 534         break;
 535     case 1:
 536         if (s->lcr & UART_LCR_DLAB) {
 537             ret = (s->divider >> 8) & 0xff;
 538         } else {
 539             ret = s->ier;
 540         }
 541         break;
 542     case 2:
 543         ret = s->iir;
 544         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 545             s->thr_ipending = 0;
 546             serial_update_irq(s);
 547         }
 548         break;
 549     case 3:
 550         ret = s->lcr;
 551         break;
 552     case 4:
 553         ret = s->mcr;
 554         break;
 555     case 5:
 556         ret = s->lsr;
 557         /* Clear break and overrun interrupts */
 558         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 559             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 560             serial_update_irq(s);
 561         }
 562         break;
 563     case 6:
 564         if (s->mcr & UART_MCR_LOOP) {
 565             /* in loopback, the modem output pins are connected to the
 566                inputs */
 567             ret = (s->mcr & 0x0c) << 4;
 568             ret |= (s->mcr & 0x02) << 3;
 569             ret |= (s->mcr & 0x01) << 5;
 570         } else {
 571             if (s->poll_msl >= 0)
 572                 serial_update_msl(s);
 573             ret = s->msr;
 574             /* Clear delta bits & msr int after read, if they were set */
 575             if (s->msr & UART_MSR_ANY_DELTA) {
 576                 s->msr &= 0xF0;
 577                 serial_update_irq(s);
 578             }
 579         }
 580         break;
 581     case 7:
 582         ret = s->scr;
 583         break;
 584     }
 585 #ifdef DEBUG_SERIAL
 586     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 587 #endif
 588     return ret;
 589 }
 590
 591 static int serial_can_receive(SerialState *s)
 592 {
 593     if(s->fcr & UART_FCR_FE) {
 594         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 595         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 596         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 597         effectively overriding the ITL that the guest has set. */
 598              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 599         else
 600              return 0;
 601     } else {
 602     return !(s->lsr & UART_LSR_DR);
 603     }
 604 }
 605
 606 static void serial_receive_break(SerialState *s)
 607 {
 608     s->rbr = 0;
 609     /* When the LSR_DR is set a null byte is pushed into the fifo */
 610     fifo_put(s, RECV_FIFO, '\0');
 611     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 612     serial_update_irq(s);
 613 }
 614
 615 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 616 static void fifo_timeout_int (void *opaque) {
 617     SerialState *s = opaque;
 618     if (s->recv_fifo.count) {
 619         s->timeout_ipending = 1;
 620         serial_update_irq(s);
 621     }
 622 }
 623
 624 static int serial_can_receive1(void *opaque)
 625 {
 626     SerialState *s = opaque;
 627     return serial_can_receive(s);
 628 }
 629
 630 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 631 {
 632     SerialState *s = opaque;
 633     if(s->fcr & UART_FCR_FE) {
 634         int i;
 635         for (i = 0; i < size; i++) {
 636             fifo_put(s, RECV_FIFO, buf[i]);
 637         }
 638         s->lsr |= UART_LSR_DR;
 639         /* call the timeout receive callback in 4 char transmit time */
 640         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 641     } else {
 642         if (s->lsr & UART_LSR_DR)
 643             s->lsr |= UART_LSR_OE;
 644         s->rbr = buf[0];
 645         s->lsr |= UART_LSR_DR;
 646     }
 647     serial_update_irq(s);
 648 }
 649
 650 static void serial_event(void *opaque, int event)
 651 {
 652     SerialState *s = opaque;
 653 #ifdef DEBUG_SERIAL
 654     printf("serial: event %x\n", event);
 655 #endif
 656     if (event == CHR_EVENT_BREAK)
 657         serial_receive_break(s);
 658 }
 659
 660 static void serial_pre_save(void *opaque)
 661 {
 662     SerialState *s = opaque;
 663     s->fcr_vmstate = s->fcr;
 664 }
 665
 666 static int serial_post_load(void *opaque, int version_id)
 667 {
 668     SerialState *s = opaque;
 669
 670     if (version_id < 3) {
 671         s->fcr_vmstate = 0;
 672     }
 673     /* Initialize fcr via setter to perform essential side-effects */
 674     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 675     return 0;
 676 }
 677
 678 static const VMStateDescription vmstate_serial = {
 679     .name = "serial",
 680     .version_id = 3,
 681     .minimum_version_id = 2,
 682     .pre_save = serial_pre_save,
 683     .post_load = serial_post_load,
 684     .fields      = (VMStateField []) {
 685         VMSTATE_UINT16_V(divider, SerialState, 2),
 686         VMSTATE_UINT8(rbr, SerialState),
 687         VMSTATE_UINT8(ier, SerialState),
 688         VMSTATE_UINT8(iir, SerialState),
 689         VMSTATE_UINT8(lcr, SerialState),
 690         VMSTATE_UINT8(mcr, SerialState),
 691         VMSTATE_UINT8(lsr, SerialState),
 692         VMSTATE_UINT8(msr, SerialState),
 693         VMSTATE_UINT8(scr, SerialState),
 694         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 695         VMSTATE_END_OF_LIST()
 696     }
 697 };
 698
 699 static void serial_reset(void *opaque)
 700 {
 701     SerialState *s = opaque;
 702
 703     s->rbr = 0;
 704     s->ier = 0;
 705     s->iir = UART_IIR_NO_INT;
 706     s->lcr = 0;
 707     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 708     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 709     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 710     s->divider = 0x0C;
 711     s->mcr = UART_MCR_OUT2;
 712     s->scr = 0;
 713     s->tsr_retry = 0;
 714     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 715     s->poll_msl = 0;
 716
 717     fifo_clear(s,RECV_FIFO);
 718     fifo_clear(s,XMIT_FIFO);
 719
 720     s->last_xmit_ts = qemu_get_clock(vm_clock);
 721
 722     s->thr_ipending = 0;
 723     s->last_break_enable = 0;
 724     qemu_irq_lower(s->irq);
 725 }
 726
 727 static void serial_init_core(SerialState *s)
 728 {
 729     if (!s->chr) {
 730         fprintf(stderr, "Can't create serial device, empty char device\n");
 731         exit(1);
 732     }
 733
 734     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 735
 736     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 737     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 738
 739     qemu_register_reset(serial_reset, s);
 740
 741     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 742                           serial_event, s);
 743 }
 744
 745 /* Change the main reference oscillator frequency. */
 746 void serial_set_frequency(SerialState *s, uint32_t frequency)
 747 {
 748     s->baudbase = frequency;
 749     serial_update_parameters(s);
 750 }
 751
 752 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 753 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 754
 755 static int serial_isa_initfn(ISADevice *dev)
 756 {
 757     static int index;
 758     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 759     SerialState *s = &isa->state;
 760
 761     if (isa->index == -1)
 762         isa->index = index;
 763     if (isa->index >= MAX_SERIAL_PORTS)
 764         return -1;
 765     if (isa->iobase == -1)
 766         isa->iobase = isa_serial_io[isa->index];
 767     if (isa->isairq == -1)
 768         isa->isairq = isa_serial_irq[isa->index];
 769     index++;
 770
 771     s->baudbase = 115200;
 772     isa_init_irq(dev, &s->irq, isa->isairq);
 773     serial_init_core(s);
 774     qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
 775
 776     register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
 777     register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
 778     return 0;
 779 }
 780
 781 SerialState *serial_isa_init(int index, CharDriverState *chr)
 782 {
 783     ISADevice *dev;
 784
 785     dev = isa_create("isa-serial");
 786     qdev_prop_set_uint32(&dev->qdev, "index", index);
 787     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
 788     if (qdev_init(&dev->qdev) < 0)
 789         return NULL;
 790     return &DO_UPCAST(ISASerialState, dev, dev)->state;
 791 }
 792
 793 static const VMStateDescription vmstate_isa_serial = {
 794     .name = "serial",
 795     .version_id = 3,
 796     .minimum_version_id = 2,
 797     .fields      = (VMStateField []) {
 798         VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
 799         VMSTATE_END_OF_LIST()
 800     }
 801 };
 802
 803 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 804                          CharDriverState *chr)
 805 {
 806     SerialState *s;
 807
 808     s = qemu_mallocz(sizeof(SerialState));
 809
 810     s->irq = irq;
 811     s->baudbase = baudbase;
 812     s->chr = chr;
 813     serial_init_core(s);
 814
 815     vmstate_register(base, &vmstate_serial, s);
 816
 817     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 818     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 819     return s;
 820 }
 821
 822 /* Memory mapped interface */
 823 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 824 {
 825     SerialState *s = opaque;
 826
 827     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 828 }
 829
 830 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 831                              uint32_t value)
 832 {
 833     SerialState *s = opaque;
 834
 835     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 836 }
 837
 838 static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
 839 {
 840     SerialState *s = opaque;
 841     uint32_t val;
 842
 843     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 844     val = bswap16(val);
 845     return val;
 846 }
 847
 848 static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
 849 {
 850     SerialState *s = opaque;
 851     uint32_t val;
 852
 853     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 854     return val;
 855 }
 856
 857 static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
 858                                 uint32_t value)
 859 {
 860     SerialState *s = opaque;
 861
 862     value = bswap16(value);
 863     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 864 }
 865
 866 static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
 867                                 uint32_t value)
 868 {
 869     SerialState *s = opaque;
 870
 871     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 872 }
 873
 874 static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
 875 {
 876     SerialState *s = opaque;
 877     uint32_t val;
 878
 879     val = serial_ioport_read(s, addr >> s->it_shift);
 880     val = bswap32(val);
 881     return val;
 882 }
 883
 884 static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
 885 {
 886     SerialState *s = opaque;
 887     uint32_t val;
 888
 889     val = serial_ioport_read(s, addr >> s->it_shift);
 890     return val;
 891 }
 892
 893 static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
 894                                 uint32_t value)
 895 {
 896     SerialState *s = opaque;
 897
 898     value = bswap32(value);
 899     serial_ioport_write(s, addr >> s->it_shift, value);
 900 }
 901
 902 static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
 903                                 uint32_t value)
 904 {
 905     SerialState *s = opaque;
 906
 907     serial_ioport_write(s, addr >> s->it_shift, value);
 908 }
 909
 910 static CPUReadMemoryFunc * const serial_mm_read_be[] = {
 911     &serial_mm_readb,
 912     &serial_mm_readw_be,
 913     &serial_mm_readl_be,
 914 };
 915
 916 static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
 917     &serial_mm_writeb,
 918     &serial_mm_writew_be,
 919     &serial_mm_writel_be,
 920 };
 921
 922 static CPUReadMemoryFunc * const serial_mm_read_le[] = {
 923     &serial_mm_readb,
 924     &serial_mm_readw_le,
 925     &serial_mm_readl_le,
 926 };
 927
 928 static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
 929     &serial_mm_writeb,
 930     &serial_mm_writew_le,
 931     &serial_mm_writel_le,
 932 };
 933
 934 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 935                              qemu_irq irq, int baudbase,
 936                              CharDriverState *chr, int ioregister,
 937                              int be)
 938 {
 939     SerialState *s;
 940     int s_io_memory;
 941
 942     s = qemu_mallocz(sizeof(SerialState));
 943
 944     s->it_shift = it_shift;
 945     s->irq = irq;
 946     s->baudbase = baudbase;
 947     s->chr = chr;
 948
 949     serial_init_core(s);
 950     vmstate_register(base, &vmstate_serial, s);
 951
 952     if (ioregister) {
 953         if (be) {
 954             s_io_memory = cpu_register_io_memory(serial_mm_read_be,
 955                                                  serial_mm_write_be, s);
 956         } else {
 957             s_io_memory = cpu_register_io_memory(serial_mm_read_le,
 958                                                  serial_mm_write_le, s);
 959         }
 960         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 961     }
 962     serial_update_msl(s);
 963     return s;
 964 }
 965
 966 static ISADeviceInfo serial_isa_info = {
 967     .qdev.name  = "isa-serial",
 968     .qdev.size  = sizeof(ISASerialState),
 969     .qdev.vmsd  = &vmstate_isa_serial,
 970     .init       = serial_isa_initfn,
 971     .qdev.props = (Property[]) {
 972         DEFINE_PROP_UINT32("index", ISASerialState, index,   -1),
 973         DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  -1),
 974         DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  -1),
 975         DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 976         DEFINE_PROP_END_OF_LIST(),
 977     },
 978 };
 979
 980 static void serial_register_devices(void)
 981 {
 982     isa_qdev_register(&serial_isa_info);
 983 }
 984
 985 device_init(serial_register_devices)