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block: Change bdrv_eject() not to drop the image
[qemu/stefanha.git] / hw / fdc.c
blob2d50bd6a3952ab55ed3c3a13fbc83b5aaccdb0a5
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum FDiskType {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } FDiskType;
71
72 typedef enum FDriveType {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } FDriveType;
78
79 typedef enum FDiskFlags {
80 FDISK_DBL_SIDES = 0x01,
81 } FDiskFlags;
82
83 typedef struct FDrive {
84 BlockDriverState *bs;
85 /* Drive status */
86 FDriveType drive;
87 uint8_t perpendicular; /* 2.88 MB access mode */
88 /* Position */
89 uint8_t head;
90 uint8_t track;
91 uint8_t sect;
92 /* Media */
93 FDiskFlags flags;
94 uint8_t last_sect; /* Nb sector per track */
95 uint8_t max_track; /* Nb of tracks */
96 uint16_t bps; /* Bytes per sector */
97 uint8_t ro; /* Is read-only */
98 } FDrive;
99
100 static void fd_init(FDrive *drv)
101 {
102 /* Drive */
103 drv->drive = FDRIVE_DRV_NONE;
104 drv->perpendicular = 0;
105 /* Disk */
106 drv->last_sect = 0;
107 drv->max_track = 0;
108 }
109
110 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
111 uint8_t last_sect)
112 {
113 return (((track * 2) + head) * last_sect) + sect - 1;
114 }
115
116 /* Returns current position, in sectors, for given drive */
117 static int fd_sector(FDrive *drv)
118 {
119 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
120 }
121
122 /* Seek to a new position:
123 * returns 0 if already on right track
124 * returns 1 if track changed
125 * returns 2 if track is invalid
126 * returns 3 if sector is invalid
127 * returns 4 if seek is disabled
128 */
129 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
130 int enable_seek)
131 {
132 uint32_t sector;
133 int ret;
134
135 if (track > drv->max_track ||
136 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
141 return 2;
142 }
143 if (sect > drv->last_sect) {
144 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
145 head, track, sect, 1,
146 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
147 drv->max_track, drv->last_sect);
148 return 3;
149 }
150 sector = fd_sector_calc(head, track, sect, drv->last_sect);
151 ret = 0;
152 if (sector != fd_sector(drv)) {
153 #if 0
154 if (!enable_seek) {
155 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
156 head, track, sect, 1, drv->max_track, drv->last_sect);
157 return 4;
158 }
159 #endif
160 drv->head = head;
161 if (drv->track != track)
162 ret = 1;
163 drv->track = track;
164 drv->sect = sect;
165 }
166
167 return ret;
168 }
169
170 /* Set drive back to track 0 */
171 static void fd_recalibrate(FDrive *drv)
172 {
173 FLOPPY_DPRINTF("recalibrate\n");
174 drv->head = 0;
175 drv->track = 0;
176 drv->sect = 1;
177 }
178
179 /* Recognize floppy formats */
180 typedef struct FDFormat {
181 FDriveType drive;
182 FDiskType disk;
183 uint8_t last_sect;
184 uint8_t max_track;
185 uint8_t max_head;
186 const char *str;
187 } FDFormat;
188
189 static const FDFormat fd_formats[] = {
190 /* First entry is default format */
191 /* 1.44 MB 3"1/2 floppy disks */
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
200 /* 2.88 MB 3"1/2 floppy disks */
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
206 /* 720 kB 3"1/2 floppy disks */
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
213 /* 1.2 MB 5"1/4 floppy disks */
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
219 /* 720 kB 5"1/4 floppy disks */
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
222 /* 360 kB 5"1/4 floppy disks */
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
227 /* 320 kB 5"1/4 floppy disks */
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
229 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
230 /* 360 kB must match 5"1/4 better than 3"1/2... */
231 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
232 /* end */
233 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
234 };
235
236 /* Revalidate a disk drive after a disk change */
237 static void fd_revalidate(FDrive *drv)
238 {
239 const FDFormat *parse;
240 uint64_t nb_sectors, size;
241 int i, first_match, match;
242 int nb_heads, max_track, last_sect, ro;
243
244 FLOPPY_DPRINTF("revalidate\n");
245 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
246 ro = bdrv_is_read_only(drv->bs);
247 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
248 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
249 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
250 nb_heads - 1, max_track, last_sect);
251 } else {
252 bdrv_get_geometry(drv->bs, &nb_sectors);
253 match = -1;
254 first_match = -1;
255 for (i = 0;; i++) {
256 parse = &fd_formats[i];
257 if (parse->drive == FDRIVE_DRV_NONE)
258 break;
259 if (drv->drive == parse->drive ||
260 drv->drive == FDRIVE_DRV_NONE) {
261 size = (parse->max_head + 1) * parse->max_track *
262 parse->last_sect;
263 if (nb_sectors == size) {
264 match = i;
265 break;
266 }
267 if (first_match == -1)
268 first_match = i;
269 }
270 }
271 if (match == -1) {
272 if (first_match == -1)
273 match = 1;
274 else
275 match = first_match;
276 parse = &fd_formats[match];
277 }
278 nb_heads = parse->max_head + 1;
279 max_track = parse->max_track;
280 last_sect = parse->last_sect;
281 drv->drive = parse->drive;
282 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
283 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
284 }
285 if (nb_heads == 1) {
286 drv->flags &= ~FDISK_DBL_SIDES;
287 } else {
288 drv->flags |= FDISK_DBL_SIDES;
289 }
290 drv->max_track = max_track;
291 drv->last_sect = last_sect;
292 drv->ro = ro;
293 } else {
294 FLOPPY_DPRINTF("No disk in drive\n");
295 drv->last_sect = 0;
296 drv->max_track = 0;
297 drv->flags &= ~FDISK_DBL_SIDES;
298 }
299 }
300
301 /********************************************************/
302 /* Intel 82078 floppy disk controller emulation */
303
304 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
305 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
306 static int fdctrl_transfer_handler (void *opaque, int nchan,
307 int dma_pos, int dma_len);
308 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
309
310 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
311 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
312 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
313 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
314 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
315 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
317 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
319 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
321
322 enum {
323 FD_DIR_WRITE = 0,
324 FD_DIR_READ = 1,
325 FD_DIR_SCANE = 2,
326 FD_DIR_SCANL = 3,
327 FD_DIR_SCANH = 4,
328 };
329
330 enum {
331 FD_STATE_MULTI = 0x01, /* multi track flag */
332 FD_STATE_FORMAT = 0x02, /* format flag */
333 FD_STATE_SEEK = 0x04, /* seek flag */
334 };
335
336 enum {
337 FD_REG_SRA = 0x00,
338 FD_REG_SRB = 0x01,
339 FD_REG_DOR = 0x02,
340 FD_REG_TDR = 0x03,
341 FD_REG_MSR = 0x04,
342 FD_REG_DSR = 0x04,
343 FD_REG_FIFO = 0x05,
344 FD_REG_DIR = 0x07,
345 };
346
347 enum {
348 FD_CMD_READ_TRACK = 0x02,
349 FD_CMD_SPECIFY = 0x03,
350 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
351 FD_CMD_WRITE = 0x05,
352 FD_CMD_READ = 0x06,
353 FD_CMD_RECALIBRATE = 0x07,
354 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
355 FD_CMD_WRITE_DELETED = 0x09,
356 FD_CMD_READ_ID = 0x0a,
357 FD_CMD_READ_DELETED = 0x0c,
358 FD_CMD_FORMAT_TRACK = 0x0d,
359 FD_CMD_DUMPREG = 0x0e,
360 FD_CMD_SEEK = 0x0f,
361 FD_CMD_VERSION = 0x10,
362 FD_CMD_SCAN_EQUAL = 0x11,
363 FD_CMD_PERPENDICULAR_MODE = 0x12,
364 FD_CMD_CONFIGURE = 0x13,
365 FD_CMD_LOCK = 0x14,
366 FD_CMD_VERIFY = 0x16,
367 FD_CMD_POWERDOWN_MODE = 0x17,
368 FD_CMD_PART_ID = 0x18,
369 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
370 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
371 FD_CMD_SAVE = 0x2e,
372 FD_CMD_OPTION = 0x33,
373 FD_CMD_RESTORE = 0x4e,
374 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
375 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
376 FD_CMD_FORMAT_AND_WRITE = 0xcd,
377 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
378 };
379
380 enum {
381 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
382 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
383 FD_CONFIG_POLL = 0x10, /* Poll enabled */
384 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
385 FD_CONFIG_EIS = 0x40, /* No implied seeks */
386 };
387
388 enum {
389 FD_SR0_EQPMT = 0x10,
390 FD_SR0_SEEK = 0x20,
391 FD_SR0_ABNTERM = 0x40,
392 FD_SR0_INVCMD = 0x80,
393 FD_SR0_RDYCHG = 0xc0,
394 };
395
396 enum {
397 FD_SR1_EC = 0x80, /* End of cylinder */
398 };
399
400 enum {
401 FD_SR2_SNS = 0x04, /* Scan not satisfied */
402 FD_SR2_SEH = 0x08, /* Scan equal hit */
403 };
404
405 enum {
406 FD_SRA_DIR = 0x01,
407 FD_SRA_nWP = 0x02,
408 FD_SRA_nINDX = 0x04,
409 FD_SRA_HDSEL = 0x08,
410 FD_SRA_nTRK0 = 0x10,
411 FD_SRA_STEP = 0x20,
412 FD_SRA_nDRV2 = 0x40,
413 FD_SRA_INTPEND = 0x80,
414 };
415
416 enum {
417 FD_SRB_MTR0 = 0x01,
418 FD_SRB_MTR1 = 0x02,
419 FD_SRB_WGATE = 0x04,
420 FD_SRB_RDATA = 0x08,
421 FD_SRB_WDATA = 0x10,
422 FD_SRB_DR0 = 0x20,
423 };
424
425 enum {
426 #if MAX_FD == 4
427 FD_DOR_SELMASK = 0x03,
428 #else
429 FD_DOR_SELMASK = 0x01,
430 #endif
431 FD_DOR_nRESET = 0x04,
432 FD_DOR_DMAEN = 0x08,
433 FD_DOR_MOTEN0 = 0x10,
434 FD_DOR_MOTEN1 = 0x20,
435 FD_DOR_MOTEN2 = 0x40,
436 FD_DOR_MOTEN3 = 0x80,
437 };
438
439 enum {
440 #if MAX_FD == 4
441 FD_TDR_BOOTSEL = 0x0c,
442 #else
443 FD_TDR_BOOTSEL = 0x04,
444 #endif
445 };
446
447 enum {
448 FD_DSR_DRATEMASK= 0x03,
449 FD_DSR_PWRDOWN = 0x40,
450 FD_DSR_SWRESET = 0x80,
451 };
452
453 enum {
454 FD_MSR_DRV0BUSY = 0x01,
455 FD_MSR_DRV1BUSY = 0x02,
456 FD_MSR_DRV2BUSY = 0x04,
457 FD_MSR_DRV3BUSY = 0x08,
458 FD_MSR_CMDBUSY = 0x10,
459 FD_MSR_NONDMA = 0x20,
460 FD_MSR_DIO = 0x40,
461 FD_MSR_RQM = 0x80,
462 };
463
464 enum {
465 FD_DIR_DSKCHG = 0x80,
466 };
467
468 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
469 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
470 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
471
472 struct FDCtrl {
473 /* Controller's identification */
474 uint8_t version;
475 /* HW */
476 qemu_irq irq;
477 int dma_chann;
478 /* Controller state */
479 QEMUTimer *result_timer;
480 uint8_t sra;
481 uint8_t srb;
482 uint8_t dor;
483 uint8_t dor_vmstate; /* only used as temp during vmstate */
484 uint8_t tdr;
485 uint8_t dsr;
486 uint8_t msr;
487 uint8_t cur_drv;
488 uint8_t status0;
489 uint8_t status1;
490 uint8_t status2;
491 /* Command FIFO */
492 uint8_t *fifo;
493 int32_t fifo_size;
494 uint32_t data_pos;
495 uint32_t data_len;
496 uint8_t data_state;
497 uint8_t data_dir;
498 uint8_t eot; /* last wanted sector */
499 /* States kept only to be returned back */
500 /* Timers state */
501 uint8_t timer0;
502 uint8_t timer1;
503 /* precompensation */
504 uint8_t precomp_trk;
505 uint8_t config;
506 uint8_t lock;
507 /* Power down config (also with status regB access mode */
508 uint8_t pwrd;
509 /* Sun4m quirks? */
510 int sun4m;
511 /* Floppy drives */
512 uint8_t num_floppies;
513 FDrive drives[MAX_FD];
514 int reset_sensei;
515 };
516
517 typedef struct FDCtrlSysBus {
518 SysBusDevice busdev;
519 struct FDCtrl state;
520 } FDCtrlSysBus;
521
522 typedef struct FDCtrlISABus {
523 ISADevice busdev;
524 struct FDCtrl state;
525 } FDCtrlISABus;
526
527 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
528 {
529 FDCtrl *fdctrl = opaque;
530 uint32_t retval;
531
532 switch (reg) {
533 case FD_REG_SRA:
534 retval = fdctrl_read_statusA(fdctrl);
535 break;
536 case FD_REG_SRB:
537 retval = fdctrl_read_statusB(fdctrl);
538 break;
539 case FD_REG_DOR:
540 retval = fdctrl_read_dor(fdctrl);
541 break;
542 case FD_REG_TDR:
543 retval = fdctrl_read_tape(fdctrl);
544 break;
545 case FD_REG_MSR:
546 retval = fdctrl_read_main_status(fdctrl);
547 break;
548 case FD_REG_FIFO:
549 retval = fdctrl_read_data(fdctrl);
550 break;
551 case FD_REG_DIR:
552 retval = fdctrl_read_dir(fdctrl);
553 break;
554 default:
555 retval = (uint32_t)(-1);
556 break;
557 }
558 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
559
560 return retval;
561 }
562
563 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
564 {
565 FDCtrl *fdctrl = opaque;
566
567 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
568
569 switch (reg) {
570 case FD_REG_DOR:
571 fdctrl_write_dor(fdctrl, value);
572 break;
573 case FD_REG_TDR:
574 fdctrl_write_tape(fdctrl, value);
575 break;
576 case FD_REG_DSR:
577 fdctrl_write_rate(fdctrl, value);
578 break;
579 case FD_REG_FIFO:
580 fdctrl_write_data(fdctrl, value);
581 break;
582 default:
583 break;
584 }
585 }
586
587 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
588 {
589 return fdctrl_read(opaque, reg & 7);
590 }
591
592 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
593 {
594 fdctrl_write(opaque, reg & 7, value);
595 }
596
597 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
598 {
599 return fdctrl_read(opaque, (uint32_t)reg);
600 }
601
602 static void fdctrl_write_mem (void *opaque,
603 target_phys_addr_t reg, uint32_t value)
604 {
605 fdctrl_write(opaque, (uint32_t)reg, value);
606 }
607
608 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
609 fdctrl_read_mem,
610 fdctrl_read_mem,
611 fdctrl_read_mem,
612 };
613
614 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
615 fdctrl_write_mem,
616 fdctrl_write_mem,
617 fdctrl_write_mem,
618 };
619
620 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
621 fdctrl_read_mem,
622 NULL,
623 NULL,
624 };
625
626 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
627 fdctrl_write_mem,
628 NULL,
629 NULL,
630 };
631
632 static const VMStateDescription vmstate_fdrive = {
633 .name = "fdrive",
634 .version_id = 1,
635 .minimum_version_id = 1,
636 .minimum_version_id_old = 1,
637 .fields = (VMStateField []) {
638 VMSTATE_UINT8(head, FDrive),
639 VMSTATE_UINT8(track, FDrive),
640 VMSTATE_UINT8(sect, FDrive),
641 VMSTATE_END_OF_LIST()
642 }
643 };
644
645 static void fdc_pre_save(void *opaque)
646 {
647 FDCtrl *s = opaque;
648
649 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
650 }
651
652 static int fdc_post_load(void *opaque, int version_id)
653 {
654 FDCtrl *s = opaque;
655
656 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
657 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
658 return 0;
659 }
660
661 static const VMStateDescription vmstate_fdc = {
662 .name = "fdc",
663 .version_id = 2,
664 .minimum_version_id = 2,
665 .minimum_version_id_old = 2,
666 .pre_save = fdc_pre_save,
667 .post_load = fdc_post_load,
668 .fields = (VMStateField []) {
669 /* Controller State */
670 VMSTATE_UINT8(sra, FDCtrl),
671 VMSTATE_UINT8(srb, FDCtrl),
672 VMSTATE_UINT8(dor_vmstate, FDCtrl),
673 VMSTATE_UINT8(tdr, FDCtrl),
674 VMSTATE_UINT8(dsr, FDCtrl),
675 VMSTATE_UINT8(msr, FDCtrl),
676 VMSTATE_UINT8(status0, FDCtrl),
677 VMSTATE_UINT8(status1, FDCtrl),
678 VMSTATE_UINT8(status2, FDCtrl),
679 /* Command FIFO */
680 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
681 uint8_t),
682 VMSTATE_UINT32(data_pos, FDCtrl),
683 VMSTATE_UINT32(data_len, FDCtrl),
684 VMSTATE_UINT8(data_state, FDCtrl),
685 VMSTATE_UINT8(data_dir, FDCtrl),
686 VMSTATE_UINT8(eot, FDCtrl),
687 /* States kept only to be returned back */
688 VMSTATE_UINT8(timer0, FDCtrl),
689 VMSTATE_UINT8(timer1, FDCtrl),
690 VMSTATE_UINT8(precomp_trk, FDCtrl),
691 VMSTATE_UINT8(config, FDCtrl),
692 VMSTATE_UINT8(lock, FDCtrl),
693 VMSTATE_UINT8(pwrd, FDCtrl),
694 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
695 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
696 vmstate_fdrive, FDrive),
697 VMSTATE_END_OF_LIST()
698 }
699 };
700
701 static void fdctrl_external_reset_sysbus(DeviceState *d)
702 {
703 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
704 FDCtrl *s = &sys->state;
705
706 fdctrl_reset(s, 0);
707 }
708
709 static void fdctrl_external_reset_isa(DeviceState *d)
710 {
711 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
712 FDCtrl *s = &isa->state;
713
714 fdctrl_reset(s, 0);
715 }
716
717 static void fdctrl_handle_tc(void *opaque, int irq, int level)
718 {
719 //FDCtrl *s = opaque;
720
721 if (level) {
722 // XXX
723 FLOPPY_DPRINTF("TC pulsed\n");
724 }
725 }
726
727 /* XXX: may change if moved to bdrv */
728 int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
729 {
730 return fdctrl->drives[drive_num].drive;
731 }
732
733 /* Change IRQ state */
734 static void fdctrl_reset_irq(FDCtrl *fdctrl)
735 {
736 if (!(fdctrl->sra & FD_SRA_INTPEND))
737 return;
738 FLOPPY_DPRINTF("Reset interrupt\n");
739 qemu_set_irq(fdctrl->irq, 0);
740 fdctrl->sra &= ~FD_SRA_INTPEND;
741 }
742
743 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
744 {
745 /* Sparc mutation */
746 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
747 /* XXX: not sure */
748 fdctrl->msr &= ~FD_MSR_CMDBUSY;
749 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
750 fdctrl->status0 = status0;
751 return;
752 }
753 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
754 qemu_set_irq(fdctrl->irq, 1);
755 fdctrl->sra |= FD_SRA_INTPEND;
756 }
757 fdctrl->reset_sensei = 0;
758 fdctrl->status0 = status0;
759 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
760 }
761
762 /* Reset controller */
763 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
764 {
765 int i;
766
767 FLOPPY_DPRINTF("reset controller\n");
768 fdctrl_reset_irq(fdctrl);
769 /* Initialise controller */
770 fdctrl->sra = 0;
771 fdctrl->srb = 0xc0;
772 if (!fdctrl->drives[1].bs)
773 fdctrl->sra |= FD_SRA_nDRV2;
774 fdctrl->cur_drv = 0;
775 fdctrl->dor = FD_DOR_nRESET;
776 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
777 fdctrl->msr = FD_MSR_RQM;
778 /* FIFO state */
779 fdctrl->data_pos = 0;
780 fdctrl->data_len = 0;
781 fdctrl->data_state = 0;
782 fdctrl->data_dir = FD_DIR_WRITE;
783 for (i = 0; i < MAX_FD; i++)
784 fd_recalibrate(&fdctrl->drives[i]);
785 fdctrl_reset_fifo(fdctrl);
786 if (do_irq) {
787 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
788 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
789 }
790 }
791
792 static inline FDrive *drv0(FDCtrl *fdctrl)
793 {
794 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
795 }
796
797 static inline FDrive *drv1(FDCtrl *fdctrl)
798 {
799 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
800 return &fdctrl->drives[1];
801 else
802 return &fdctrl->drives[0];
803 }
804
805 #if MAX_FD == 4
806 static inline FDrive *drv2(FDCtrl *fdctrl)
807 {
808 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
809 return &fdctrl->drives[2];
810 else
811 return &fdctrl->drives[1];
812 }
813
814 static inline FDrive *drv3(FDCtrl *fdctrl)
815 {
816 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
817 return &fdctrl->drives[3];
818 else
819 return &fdctrl->drives[2];
820 }
821 #endif
822
823 static FDrive *get_cur_drv(FDCtrl *fdctrl)
824 {
825 switch (fdctrl->cur_drv) {
826 case 0: return drv0(fdctrl);
827 case 1: return drv1(fdctrl);
828 #if MAX_FD == 4
829 case 2: return drv2(fdctrl);
830 case 3: return drv3(fdctrl);
831 #endif
832 default: return NULL;
833 }
834 }
835
836 /* Status A register : 0x00 (read-only) */
837 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
838 {
839 uint32_t retval = fdctrl->sra;
840
841 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
842
843 return retval;
844 }
845
846 /* Status B register : 0x01 (read-only) */
847 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
848 {
849 uint32_t retval = fdctrl->srb;
850
851 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
852
853 return retval;
854 }
855
856 /* Digital output register : 0x02 */
857 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
858 {
859 uint32_t retval = fdctrl->dor;
860
861 /* Selected drive */
862 retval |= fdctrl->cur_drv;
863 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
864
865 return retval;
866 }
867
868 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
869 {
870 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
871
872 /* Motors */
873 if (value & FD_DOR_MOTEN0)
874 fdctrl->srb |= FD_SRB_MTR0;
875 else
876 fdctrl->srb &= ~FD_SRB_MTR0;
877 if (value & FD_DOR_MOTEN1)
878 fdctrl->srb |= FD_SRB_MTR1;
879 else
880 fdctrl->srb &= ~FD_SRB_MTR1;
881
882 /* Drive */
883 if (value & 1)
884 fdctrl->srb |= FD_SRB_DR0;
885 else
886 fdctrl->srb &= ~FD_SRB_DR0;
887
888 /* Reset */
889 if (!(value & FD_DOR_nRESET)) {
890 if (fdctrl->dor & FD_DOR_nRESET) {
891 FLOPPY_DPRINTF("controller enter RESET state\n");
892 }
893 } else {
894 if (!(fdctrl->dor & FD_DOR_nRESET)) {
895 FLOPPY_DPRINTF("controller out of RESET state\n");
896 fdctrl_reset(fdctrl, 1);
897 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
898 }
899 }
900 /* Selected drive */
901 fdctrl->cur_drv = value & FD_DOR_SELMASK;
902
903 fdctrl->dor = value;
904 }
905
906 /* Tape drive register : 0x03 */
907 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
908 {
909 uint32_t retval = fdctrl->tdr;
910
911 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
912
913 return retval;
914 }
915
916 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
917 {
918 /* Reset mode */
919 if (!(fdctrl->dor & FD_DOR_nRESET)) {
920 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
921 return;
922 }
923 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
924 /* Disk boot selection indicator */
925 fdctrl->tdr = value & FD_TDR_BOOTSEL;
926 /* Tape indicators: never allow */
927 }
928
929 /* Main status register : 0x04 (read) */
930 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
931 {
932 uint32_t retval = fdctrl->msr;
933
934 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
935 fdctrl->dor |= FD_DOR_nRESET;
936
937 /* Sparc mutation */
938 if (fdctrl->sun4m) {
939 retval |= FD_MSR_DIO;
940 fdctrl_reset_irq(fdctrl);
941 };
942
943 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
944
945 return retval;
946 }
947
948 /* Data select rate register : 0x04 (write) */
949 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
950 {
951 /* Reset mode */
952 if (!(fdctrl->dor & FD_DOR_nRESET)) {
953 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
954 return;
955 }
956 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
957 /* Reset: autoclear */
958 if (value & FD_DSR_SWRESET) {
959 fdctrl->dor &= ~FD_DOR_nRESET;
960 fdctrl_reset(fdctrl, 1);
961 fdctrl->dor |= FD_DOR_nRESET;
962 }
963 if (value & FD_DSR_PWRDOWN) {
964 fdctrl_reset(fdctrl, 1);
965 }
966 fdctrl->dsr = value;
967 }
968
969 static int fdctrl_media_changed(FDrive *drv)
970 {
971 int ret;
972
973 if (!drv->bs)
974 return 0;
975 ret = bdrv_media_changed(drv->bs);
976 if (ret) {
977 fd_revalidate(drv);
978 }
979 return ret;
980 }
981
982 /* Digital input register : 0x07 (read-only) */
983 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
984 {
985 uint32_t retval = 0;
986
987 if (fdctrl_media_changed(drv0(fdctrl))
988 || fdctrl_media_changed(drv1(fdctrl))
989 #if MAX_FD == 4
990 || fdctrl_media_changed(drv2(fdctrl))
991 || fdctrl_media_changed(drv3(fdctrl))
992 #endif
993 )
994 retval |= FD_DIR_DSKCHG;
995 if (retval != 0) {
996 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
997 }
998
999 return retval;
1000 }
1001
1002 /* FIFO state control */
1003 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1004 {
1005 fdctrl->data_dir = FD_DIR_WRITE;
1006 fdctrl->data_pos = 0;
1007 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1008 }
1009
1010 /* Set FIFO status for the host to read */
1011 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
1012 {
1013 fdctrl->data_dir = FD_DIR_READ;
1014 fdctrl->data_len = fifo_len;
1015 fdctrl->data_pos = 0;
1016 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1017 if (do_irq)
1018 fdctrl_raise_irq(fdctrl, 0x00);
1019 }
1020
1021 /* Set an error: unimplemented/unknown command */
1022 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1023 {
1024 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1025 fdctrl->fifo[0] = FD_SR0_INVCMD;
1026 fdctrl_set_fifo(fdctrl, 1, 0);
1027 }
1028
1029 /* Seek to next sector */
1030 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1031 {
1032 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1033 cur_drv->head, cur_drv->track, cur_drv->sect,
1034 fd_sector(cur_drv));
1035 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1036 error in fact */
1037 if (cur_drv->sect >= cur_drv->last_sect ||
1038 cur_drv->sect == fdctrl->eot) {
1039 cur_drv->sect = 1;
1040 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1041 if (cur_drv->head == 0 &&
1042 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1043 cur_drv->head = 1;
1044 } else {
1045 cur_drv->head = 0;
1046 cur_drv->track++;
1047 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1048 return 0;
1049 }
1050 } else {
1051 cur_drv->track++;
1052 return 0;
1053 }
1054 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1055 cur_drv->head, cur_drv->track,
1056 cur_drv->sect, fd_sector(cur_drv));
1057 } else {
1058 cur_drv->sect++;
1059 }
1060 return 1;
1061 }
1062
1063 /* Callback for transfer end (stop or abort) */
1064 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1065 uint8_t status1, uint8_t status2)
1066 {
1067 FDrive *cur_drv;
1068
1069 cur_drv = get_cur_drv(fdctrl);
1070 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1071 status0, status1, status2,
1072 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1073 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1074 fdctrl->fifo[1] = status1;
1075 fdctrl->fifo[2] = status2;
1076 fdctrl->fifo[3] = cur_drv->track;
1077 fdctrl->fifo[4] = cur_drv->head;
1078 fdctrl->fifo[5] = cur_drv->sect;
1079 fdctrl->fifo[6] = FD_SECTOR_SC;
1080 fdctrl->data_dir = FD_DIR_READ;
1081 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1082 DMA_release_DREQ(fdctrl->dma_chann);
1083 }
1084 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1085 fdctrl->msr &= ~FD_MSR_NONDMA;
1086 fdctrl_set_fifo(fdctrl, 7, 1);
1087 }
1088
1089 /* Prepare a data transfer (either DMA or FIFO) */
1090 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1091 {
1092 FDrive *cur_drv;
1093 uint8_t kh, kt, ks;
1094 int did_seek = 0;
1095
1096 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1097 cur_drv = get_cur_drv(fdctrl);
1098 kt = fdctrl->fifo[2];
1099 kh = fdctrl->fifo[3];
1100 ks = fdctrl->fifo[4];
1101 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1102 GET_CUR_DRV(fdctrl), kh, kt, ks,
1103 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1104 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1105 case 2:
1106 /* sect too big */
1107 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1108 fdctrl->fifo[3] = kt;
1109 fdctrl->fifo[4] = kh;
1110 fdctrl->fifo[5] = ks;
1111 return;
1112 case 3:
1113 /* track too big */
1114 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1115 fdctrl->fifo[3] = kt;
1116 fdctrl->fifo[4] = kh;
1117 fdctrl->fifo[5] = ks;
1118 return;
1119 case 4:
1120 /* No seek enabled */
1121 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1122 fdctrl->fifo[3] = kt;
1123 fdctrl->fifo[4] = kh;
1124 fdctrl->fifo[5] = ks;
1125 return;
1126 case 1:
1127 did_seek = 1;
1128 break;
1129 default:
1130 break;
1131 }
1132
1133 /* Set the FIFO state */
1134 fdctrl->data_dir = direction;
1135 fdctrl->data_pos = 0;
1136 fdctrl->msr |= FD_MSR_CMDBUSY;
1137 if (fdctrl->fifo[0] & 0x80)
1138 fdctrl->data_state |= FD_STATE_MULTI;
1139 else
1140 fdctrl->data_state &= ~FD_STATE_MULTI;
1141 if (did_seek)
1142 fdctrl->data_state |= FD_STATE_SEEK;
1143 else
1144 fdctrl->data_state &= ~FD_STATE_SEEK;
1145 if (fdctrl->fifo[5] == 00) {
1146 fdctrl->data_len = fdctrl->fifo[8];
1147 } else {
1148 int tmp;
1149 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1150 tmp = (fdctrl->fifo[6] - ks + 1);
1151 if (fdctrl->fifo[0] & 0x80)
1152 tmp += fdctrl->fifo[6];
1153 fdctrl->data_len *= tmp;
1154 }
1155 fdctrl->eot = fdctrl->fifo[6];
1156 if (fdctrl->dor & FD_DOR_DMAEN) {
1157 int dma_mode;
1158 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1159 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1160 dma_mode = (dma_mode >> 2) & 3;
1161 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1162 dma_mode, direction,
1163 (128 << fdctrl->fifo[5]) *
1164 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1165 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1166 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1167 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1168 (direction == FD_DIR_READ && dma_mode == 1)) {
1169 /* No access is allowed until DMA transfer has completed */
1170 fdctrl->msr &= ~FD_MSR_RQM;
1171 /* Now, we just have to wait for the DMA controller to
1172 * recall us...
1173 */
1174 DMA_hold_DREQ(fdctrl->dma_chann);
1175 DMA_schedule(fdctrl->dma_chann);
1176 return;
1177 } else {
1178 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1179 }
1180 }
1181 FLOPPY_DPRINTF("start non-DMA transfer\n");
1182 fdctrl->msr |= FD_MSR_NONDMA;
1183 if (direction != FD_DIR_WRITE)
1184 fdctrl->msr |= FD_MSR_DIO;
1185 /* IO based transfer: calculate len */
1186 fdctrl_raise_irq(fdctrl, 0x00);
1187
1188 return;
1189 }
1190
1191 /* Prepare a transfer of deleted data */
1192 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1193 {
1194 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1195
1196 /* We don't handle deleted data,
1197 * so we don't return *ANYTHING*
1198 */
1199 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1200 }
1201
1202 /* handlers for DMA transfers */
1203 static int fdctrl_transfer_handler (void *opaque, int nchan,
1204 int dma_pos, int dma_len)
1205 {
1206 FDCtrl *fdctrl;
1207 FDrive *cur_drv;
1208 int len, start_pos, rel_pos;
1209 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1210
1211 fdctrl = opaque;
1212 if (fdctrl->msr & FD_MSR_RQM) {
1213 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1214 return 0;
1215 }
1216 cur_drv = get_cur_drv(fdctrl);
1217 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1218 fdctrl->data_dir == FD_DIR_SCANH)
1219 status2 = FD_SR2_SNS;
1220 if (dma_len > fdctrl->data_len)
1221 dma_len = fdctrl->data_len;
1222 if (cur_drv->bs == NULL) {
1223 if (fdctrl->data_dir == FD_DIR_WRITE)
1224 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1225 else
1226 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1227 len = 0;
1228 goto transfer_error;
1229 }
1230 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1231 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1232 len = dma_len - fdctrl->data_pos;
1233 if (len + rel_pos > FD_SECTOR_LEN)
1234 len = FD_SECTOR_LEN - rel_pos;
1235 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1236 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1237 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1238 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1239 fd_sector(cur_drv) * FD_SECTOR_LEN);
1240 if (fdctrl->data_dir != FD_DIR_WRITE ||
1241 len < FD_SECTOR_LEN || rel_pos != 0) {
1242 /* READ & SCAN commands and realign to a sector for WRITE */
1243 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1244 fdctrl->fifo, 1) < 0) {
1245 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1246 fd_sector(cur_drv));
1247 /* Sure, image size is too small... */
1248 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1249 }
1250 }
1251 switch (fdctrl->data_dir) {
1252 case FD_DIR_READ:
1253 /* READ commands */
1254 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1255 fdctrl->data_pos, len);
1256 break;
1257 case FD_DIR_WRITE:
1258 /* WRITE commands */
1259 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1260 fdctrl->data_pos, len);
1261 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1262 fdctrl->fifo, 1) < 0) {
1263 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1264 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1265 goto transfer_error;
1266 }
1267 break;
1268 default:
1269 /* SCAN commands */
1270 {
1271 uint8_t tmpbuf[FD_SECTOR_LEN];
1272 int ret;
1273 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1274 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1275 if (ret == 0) {
1276 status2 = FD_SR2_SEH;
1277 goto end_transfer;
1278 }
1279 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1280 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1281 status2 = 0x00;
1282 goto end_transfer;
1283 }
1284 }
1285 break;
1286 }
1287 fdctrl->data_pos += len;
1288 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1289 if (rel_pos == 0) {
1290 /* Seek to next sector */
1291 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1292 break;
1293 }
1294 }
1295 end_transfer:
1296 len = fdctrl->data_pos - start_pos;
1297 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1298 fdctrl->data_pos, len, fdctrl->data_len);
1299 if (fdctrl->data_dir == FD_DIR_SCANE ||
1300 fdctrl->data_dir == FD_DIR_SCANL ||
1301 fdctrl->data_dir == FD_DIR_SCANH)
1302 status2 = FD_SR2_SEH;
1303 if (FD_DID_SEEK(fdctrl->data_state))
1304 status0 |= FD_SR0_SEEK;
1305 fdctrl->data_len -= len;
1306 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1307 transfer_error:
1308
1309 return len;
1310 }
1311
1312 /* Data register : 0x05 */
1313 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1314 {
1315 FDrive *cur_drv;
1316 uint32_t retval = 0;
1317 int pos;
1318
1319 cur_drv = get_cur_drv(fdctrl);
1320 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1321 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1322 FLOPPY_ERROR("controller not ready for reading\n");
1323 return 0;
1324 }
1325 pos = fdctrl->data_pos;
1326 if (fdctrl->msr & FD_MSR_NONDMA) {
1327 pos %= FD_SECTOR_LEN;
1328 if (pos == 0) {
1329 if (fdctrl->data_pos != 0)
1330 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1331 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1332 fd_sector(cur_drv));
1333 return 0;
1334 }
1335 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1336 FLOPPY_DPRINTF("error getting sector %d\n",
1337 fd_sector(cur_drv));
1338 /* Sure, image size is too small... */
1339 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1340 }
1341 }
1342 }
1343 retval = fdctrl->fifo[pos];
1344 if (++fdctrl->data_pos == fdctrl->data_len) {
1345 fdctrl->data_pos = 0;
1346 /* Switch from transfer mode to status mode
1347 * then from status mode to command mode
1348 */
1349 if (fdctrl->msr & FD_MSR_NONDMA) {
1350 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1351 } else {
1352 fdctrl_reset_fifo(fdctrl);
1353 fdctrl_reset_irq(fdctrl);
1354 }
1355 }
1356 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1357
1358 return retval;
1359 }
1360
1361 static void fdctrl_format_sector(FDCtrl *fdctrl)
1362 {
1363 FDrive *cur_drv;
1364 uint8_t kh, kt, ks;
1365
1366 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1367 cur_drv = get_cur_drv(fdctrl);
1368 kt = fdctrl->fifo[6];
1369 kh = fdctrl->fifo[7];
1370 ks = fdctrl->fifo[8];
1371 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1372 GET_CUR_DRV(fdctrl), kh, kt, ks,
1373 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1374 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1375 case 2:
1376 /* sect too big */
1377 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1378 fdctrl->fifo[3] = kt;
1379 fdctrl->fifo[4] = kh;
1380 fdctrl->fifo[5] = ks;
1381 return;
1382 case 3:
1383 /* track too big */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 4:
1390 /* No seek enabled */
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1392 fdctrl->fifo[3] = kt;
1393 fdctrl->fifo[4] = kh;
1394 fdctrl->fifo[5] = ks;
1395 return;
1396 case 1:
1397 fdctrl->data_state |= FD_STATE_SEEK;
1398 break;
1399 default:
1400 break;
1401 }
1402 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1403 if (cur_drv->bs == NULL ||
1404 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1405 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1406 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1407 } else {
1408 if (cur_drv->sect == cur_drv->last_sect) {
1409 fdctrl->data_state &= ~FD_STATE_FORMAT;
1410 /* Last sector done */
1411 if (FD_DID_SEEK(fdctrl->data_state))
1412 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1413 else
1414 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1415 } else {
1416 /* More to do */
1417 fdctrl->data_pos = 0;
1418 fdctrl->data_len = 4;
1419 }
1420 }
1421 }
1422
1423 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1424 {
1425 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1426 fdctrl->fifo[0] = fdctrl->lock << 4;
1427 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1428 }
1429
1430 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1431 {
1432 FDrive *cur_drv = get_cur_drv(fdctrl);
1433
1434 /* Drives position */
1435 fdctrl->fifo[0] = drv0(fdctrl)->track;
1436 fdctrl->fifo[1] = drv1(fdctrl)->track;
1437 #if MAX_FD == 4
1438 fdctrl->fifo[2] = drv2(fdctrl)->track;
1439 fdctrl->fifo[3] = drv3(fdctrl)->track;
1440 #else
1441 fdctrl->fifo[2] = 0;
1442 fdctrl->fifo[3] = 0;
1443 #endif
1444 /* timers */
1445 fdctrl->fifo[4] = fdctrl->timer0;
1446 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1447 fdctrl->fifo[6] = cur_drv->last_sect;
1448 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1449 (cur_drv->perpendicular << 2);
1450 fdctrl->fifo[8] = fdctrl->config;
1451 fdctrl->fifo[9] = fdctrl->precomp_trk;
1452 fdctrl_set_fifo(fdctrl, 10, 0);
1453 }
1454
1455 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1456 {
1457 /* Controller's version */
1458 fdctrl->fifo[0] = fdctrl->version;
1459 fdctrl_set_fifo(fdctrl, 1, 1);
1460 }
1461
1462 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1463 {
1464 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1465 fdctrl_set_fifo(fdctrl, 1, 0);
1466 }
1467
1468 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1469 {
1470 FDrive *cur_drv = get_cur_drv(fdctrl);
1471
1472 /* Drives position */
1473 drv0(fdctrl)->track = fdctrl->fifo[3];
1474 drv1(fdctrl)->track = fdctrl->fifo[4];
1475 #if MAX_FD == 4
1476 drv2(fdctrl)->track = fdctrl->fifo[5];
1477 drv3(fdctrl)->track = fdctrl->fifo[6];
1478 #endif
1479 /* timers */
1480 fdctrl->timer0 = fdctrl->fifo[7];
1481 fdctrl->timer1 = fdctrl->fifo[8];
1482 cur_drv->last_sect = fdctrl->fifo[9];
1483 fdctrl->lock = fdctrl->fifo[10] >> 7;
1484 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1485 fdctrl->config = fdctrl->fifo[11];
1486 fdctrl->precomp_trk = fdctrl->fifo[12];
1487 fdctrl->pwrd = fdctrl->fifo[13];
1488 fdctrl_reset_fifo(fdctrl);
1489 }
1490
1491 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1492 {
1493 FDrive *cur_drv = get_cur_drv(fdctrl);
1494
1495 fdctrl->fifo[0] = 0;
1496 fdctrl->fifo[1] = 0;
1497 /* Drives position */
1498 fdctrl->fifo[2] = drv0(fdctrl)->track;
1499 fdctrl->fifo[3] = drv1(fdctrl)->track;
1500 #if MAX_FD == 4
1501 fdctrl->fifo[4] = drv2(fdctrl)->track;
1502 fdctrl->fifo[5] = drv3(fdctrl)->track;
1503 #else
1504 fdctrl->fifo[4] = 0;
1505 fdctrl->fifo[5] = 0;
1506 #endif
1507 /* timers */
1508 fdctrl->fifo[6] = fdctrl->timer0;
1509 fdctrl->fifo[7] = fdctrl->timer1;
1510 fdctrl->fifo[8] = cur_drv->last_sect;
1511 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1512 (cur_drv->perpendicular << 2);
1513 fdctrl->fifo[10] = fdctrl->config;
1514 fdctrl->fifo[11] = fdctrl->precomp_trk;
1515 fdctrl->fifo[12] = fdctrl->pwrd;
1516 fdctrl->fifo[13] = 0;
1517 fdctrl->fifo[14] = 0;
1518 fdctrl_set_fifo(fdctrl, 15, 1);
1519 }
1520
1521 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1522 {
1523 FDrive *cur_drv = get_cur_drv(fdctrl);
1524
1525 /* XXX: should set main status register to busy */
1526 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1527 qemu_mod_timer(fdctrl->result_timer,
1528 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1529 }
1530
1531 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1532 {
1533 FDrive *cur_drv;
1534
1535 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1536 cur_drv = get_cur_drv(fdctrl);
1537 fdctrl->data_state |= FD_STATE_FORMAT;
1538 if (fdctrl->fifo[0] & 0x80)
1539 fdctrl->data_state |= FD_STATE_MULTI;
1540 else
1541 fdctrl->data_state &= ~FD_STATE_MULTI;
1542 fdctrl->data_state &= ~FD_STATE_SEEK;
1543 cur_drv->bps =
1544 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1545 #if 0
1546 cur_drv->last_sect =
1547 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1548 fdctrl->fifo[3] / 2;
1549 #else
1550 cur_drv->last_sect = fdctrl->fifo[3];
1551 #endif
1552 /* TODO: implement format using DMA expected by the Bochs BIOS
1553 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1554 * the sector with the specified fill byte
1555 */
1556 fdctrl->data_state &= ~FD_STATE_FORMAT;
1557 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1558 }
1559
1560 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1561 {
1562 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1563 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1564 if (fdctrl->fifo[2] & 1)
1565 fdctrl->dor &= ~FD_DOR_DMAEN;
1566 else
1567 fdctrl->dor |= FD_DOR_DMAEN;
1568 /* No result back */
1569 fdctrl_reset_fifo(fdctrl);
1570 }
1571
1572 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1573 {
1574 FDrive *cur_drv;
1575
1576 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1577 cur_drv = get_cur_drv(fdctrl);
1578 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1579 /* 1 Byte status back */
1580 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1581 (cur_drv->track == 0 ? 0x10 : 0x00) |
1582 (cur_drv->head << 2) |
1583 GET_CUR_DRV(fdctrl) |
1584 0x28;
1585 fdctrl_set_fifo(fdctrl, 1, 0);
1586 }
1587
1588 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1589 {
1590 FDrive *cur_drv;
1591
1592 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1593 cur_drv = get_cur_drv(fdctrl);
1594 fd_recalibrate(cur_drv);
1595 fdctrl_reset_fifo(fdctrl);
1596 /* Raise Interrupt */
1597 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1598 }
1599
1600 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1601 {
1602 FDrive *cur_drv = get_cur_drv(fdctrl);
1603
1604 if(fdctrl->reset_sensei > 0) {
1605 fdctrl->fifo[0] =
1606 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1607 fdctrl->reset_sensei--;
1608 } else {
1609 /* XXX: status0 handling is broken for read/write
1610 commands, so we do this hack. It should be suppressed
1611 ASAP */
1612 fdctrl->fifo[0] =
1613 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1614 }
1615
1616 fdctrl->fifo[1] = cur_drv->track;
1617 fdctrl_set_fifo(fdctrl, 2, 0);
1618 fdctrl_reset_irq(fdctrl);
1619 fdctrl->status0 = FD_SR0_RDYCHG;
1620 }
1621
1622 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1623 {
1624 FDrive *cur_drv;
1625
1626 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1627 cur_drv = get_cur_drv(fdctrl);
1628 fdctrl_reset_fifo(fdctrl);
1629 if (fdctrl->fifo[2] > cur_drv->max_track) {
1630 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1631 } else {
1632 cur_drv->track = fdctrl->fifo[2];
1633 /* Raise Interrupt */
1634 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1635 }
1636 }
1637
1638 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1639 {
1640 FDrive *cur_drv = get_cur_drv(fdctrl);
1641
1642 if (fdctrl->fifo[1] & 0x80)
1643 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1644 /* No result back */
1645 fdctrl_reset_fifo(fdctrl);
1646 }
1647
1648 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1649 {
1650 fdctrl->config = fdctrl->fifo[2];
1651 fdctrl->precomp_trk = fdctrl->fifo[3];
1652 /* No result back */
1653 fdctrl_reset_fifo(fdctrl);
1654 }
1655
1656 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1657 {
1658 fdctrl->pwrd = fdctrl->fifo[1];
1659 fdctrl->fifo[0] = fdctrl->fifo[1];
1660 fdctrl_set_fifo(fdctrl, 1, 1);
1661 }
1662
1663 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1664 {
1665 /* No result back */
1666 fdctrl_reset_fifo(fdctrl);
1667 }
1668
1669 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1670 {
1671 FDrive *cur_drv = get_cur_drv(fdctrl);
1672
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1674 /* Command parameters done */
1675 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1676 fdctrl->fifo[0] = fdctrl->fifo[1];
1677 fdctrl->fifo[2] = 0;
1678 fdctrl->fifo[3] = 0;
1679 fdctrl_set_fifo(fdctrl, 4, 1);
1680 } else {
1681 fdctrl_reset_fifo(fdctrl);
1682 }
1683 } else if (fdctrl->data_len > 7) {
1684 /* ERROR */
1685 fdctrl->fifo[0] = 0x80 |
1686 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1687 fdctrl_set_fifo(fdctrl, 1, 1);
1688 }
1689 }
1690
1691 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1692 {
1693 FDrive *cur_drv;
1694
1695 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1696 cur_drv = get_cur_drv(fdctrl);
1697 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1698 cur_drv->track = cur_drv->max_track - 1;
1699 } else {
1700 cur_drv->track += fdctrl->fifo[2];
1701 }
1702 fdctrl_reset_fifo(fdctrl);
1703 /* Raise Interrupt */
1704 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705 }
1706
1707 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1708 {
1709 FDrive *cur_drv;
1710
1711 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1712 cur_drv = get_cur_drv(fdctrl);
1713 if (fdctrl->fifo[2] > cur_drv->track) {
1714 cur_drv->track = 0;
1715 } else {
1716 cur_drv->track -= fdctrl->fifo[2];
1717 }
1718 fdctrl_reset_fifo(fdctrl);
1719 /* Raise Interrupt */
1720 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1721 }
1722
1723 static const struct {
1724 uint8_t value;
1725 uint8_t mask;
1726 const char* name;
1727 int parameters;
1728 void (*handler)(FDCtrl *fdctrl, int direction);
1729 int direction;
1730 } handlers[] = {
1731 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1732 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1733 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1734 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1735 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1736 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1737 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1738 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1739 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1740 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1741 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1742 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1743 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1744 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1745 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1746 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1747 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1748 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1749 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1750 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1751 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1752 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1753 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1754 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1755 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1756 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1757 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1758 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1759 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1760 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1761 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1762 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1763 };
1764 /* Associate command to an index in the 'handlers' array */
1765 static uint8_t command_to_handler[256];
1766
1767 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1768 {
1769 FDrive *cur_drv;
1770 int pos;
1771
1772 /* Reset mode */
1773 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1774 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1775 return;
1776 }
1777 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1778 FLOPPY_ERROR("controller not ready for writing\n");
1779 return;
1780 }
1781 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1782 /* Is it write command time ? */
1783 if (fdctrl->msr & FD_MSR_NONDMA) {
1784 /* FIFO data write */
1785 pos = fdctrl->data_pos++;
1786 pos %= FD_SECTOR_LEN;
1787 fdctrl->fifo[pos] = value;
1788 if (pos == FD_SECTOR_LEN - 1 ||
1789 fdctrl->data_pos == fdctrl->data_len) {
1790 cur_drv = get_cur_drv(fdctrl);
1791 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1792 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1793 return;
1794 }
1795 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1796 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1797 fd_sector(cur_drv));
1798 return;
1799 }
1800 }
1801 /* Switch from transfer mode to status mode
1802 * then from status mode to command mode
1803 */
1804 if (fdctrl->data_pos == fdctrl->data_len)
1805 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1806 return;
1807 }
1808 if (fdctrl->data_pos == 0) {
1809 /* Command */
1810 pos = command_to_handler[value & 0xff];
1811 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1812 fdctrl->data_len = handlers[pos].parameters + 1;
1813 }
1814
1815 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1816 fdctrl->fifo[fdctrl->data_pos++] = value;
1817 if (fdctrl->data_pos == fdctrl->data_len) {
1818 /* We now have all parameters
1819 * and will be able to treat the command
1820 */
1821 if (fdctrl->data_state & FD_STATE_FORMAT) {
1822 fdctrl_format_sector(fdctrl);
1823 return;
1824 }
1825
1826 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1827 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1828 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1829 }
1830 }
1831
1832 static void fdctrl_result_timer(void *opaque)
1833 {
1834 FDCtrl *fdctrl = opaque;
1835 FDrive *cur_drv = get_cur_drv(fdctrl);
1836
1837 /* Pretend we are spinning.
1838 * This is needed for Coherent, which uses READ ID to check for
1839 * sector interleaving.
1840 */
1841 if (cur_drv->last_sect != 0) {
1842 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1843 }
1844 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1845 }
1846
1847 /* Init functions */
1848 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1849 {
1850 unsigned int i;
1851 FDrive *drive;
1852
1853 for (i = 0; i < MAX_FD; i++) {
1854 drive = &fdctrl->drives[i];
1855
1856 if (drive->bs) {
1857 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1858 error_report("fdc doesn't support drive option werror");
1859 return -1;
1860 }
1861 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1862 error_report("fdc doesn't support drive option rerror");
1863 return -1;
1864 }
1865 }
1866
1867 fd_init(drive);
1868 fd_revalidate(drive);
1869 if (drive->bs) {
1870 bdrv_set_removable(drive->bs, 1);
1871 }
1872 }
1873 return 0;
1874 }
1875
1876 FDCtrl *fdctrl_init_isa(DriveInfo **fds)
1877 {
1878 ISADevice *dev;
1879
1880 dev = isa_create("isa-fdc");
1881 if (fds[0]) {
1882 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1883 }
1884 if (fds[1]) {
1885 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1886 }
1887 qdev_init_nofail(&dev->qdev);
1888 return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
1889 }
1890
1891 FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1892 target_phys_addr_t mmio_base, DriveInfo **fds)
1893 {
1894 FDCtrl *fdctrl;
1895 DeviceState *dev;
1896 FDCtrlSysBus *sys;
1897
1898 dev = qdev_create(NULL, "sysbus-fdc");
1899 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1900 fdctrl = &sys->state;
1901 fdctrl->dma_chann = dma_chann; /* FIXME */
1902 if (fds[0]) {
1903 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1904 }
1905 if (fds[1]) {
1906 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1907 }
1908 qdev_init_nofail(dev);
1909 sysbus_connect_irq(&sys->busdev, 0, irq);
1910 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1911
1912 return fdctrl;
1913 }
1914
1915 FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1916 DriveInfo **fds, qemu_irq *fdc_tc)
1917 {
1918 DeviceState *dev;
1919 FDCtrlSysBus *sys;
1920 FDCtrl *fdctrl;
1921
1922 dev = qdev_create(NULL, "SUNW,fdtwo");
1923 if (fds[0]) {
1924 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1925 }
1926 qdev_init_nofail(dev);
1927 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1928 fdctrl = &sys->state;
1929 sysbus_connect_irq(&sys->busdev, 0, irq);
1930 sysbus_mmio_map(&sys->busdev, 0, io_base);
1931 *fdc_tc = qdev_get_gpio_in(dev, 0);
1932
1933 return fdctrl;
1934 }
1935
1936 static int fdctrl_init_common(FDCtrl *fdctrl)
1937 {
1938 int i, j;
1939 static int command_tables_inited = 0;
1940
1941 /* Fill 'command_to_handler' lookup table */
1942 if (!command_tables_inited) {
1943 command_tables_inited = 1;
1944 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1945 for (j = 0; j < sizeof(command_to_handler); j++) {
1946 if ((j & handlers[i].mask) == handlers[i].value) {
1947 command_to_handler[j] = i;
1948 }
1949 }
1950 }
1951 }
1952
1953 FLOPPY_DPRINTF("init controller\n");
1954 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1955 fdctrl->fifo_size = 512;
1956 fdctrl->result_timer = qemu_new_timer(vm_clock,
1957 fdctrl_result_timer, fdctrl);
1958
1959 fdctrl->version = 0x90; /* Intel 82078 controller */
1960 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1961 fdctrl->num_floppies = MAX_FD;
1962
1963 if (fdctrl->dma_chann != -1)
1964 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1965 return fdctrl_connect_drives(fdctrl);
1966 }
1967
1968 static int isabus_fdc_init1(ISADevice *dev)
1969 {
1970 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1971 FDCtrl *fdctrl = &isa->state;
1972 int iobase = 0x3f0;
1973 int isairq = 6;
1974 int dma_chann = 2;
1975 int ret;
1976
1977 register_ioport_read(iobase + 0x01, 5, 1,
1978 &fdctrl_read_port, fdctrl);
1979 register_ioport_read(iobase + 0x07, 1, 1,
1980 &fdctrl_read_port, fdctrl);
1981 register_ioport_write(iobase + 0x01, 5, 1,
1982 &fdctrl_write_port, fdctrl);
1983 register_ioport_write(iobase + 0x07, 1, 1,
1984 &fdctrl_write_port, fdctrl);
1985 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1986 fdctrl->dma_chann = dma_chann;
1987
1988 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1989 ret = fdctrl_init_common(fdctrl);
1990
1991 return ret;
1992 }
1993
1994 static int sysbus_fdc_init1(SysBusDevice *dev)
1995 {
1996 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1997 FDCtrl *fdctrl = &sys->state;
1998 int io;
1999 int ret;
2000
2001 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
2002 sysbus_init_mmio(dev, 0x08, io);
2003 sysbus_init_irq(dev, &fdctrl->irq);
2004 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2005 fdctrl->dma_chann = -1;
2006
2007 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2008 ret = fdctrl_init_common(fdctrl);
2009
2010 return ret;
2011 }
2012
2013 static int sun4m_fdc_init1(SysBusDevice *dev)
2014 {
2015 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2016 int io;
2017
2018 io = cpu_register_io_memory(fdctrl_mem_read_strict,
2019 fdctrl_mem_write_strict, fdctrl);
2020 sysbus_init_mmio(dev, 0x08, io);
2021 sysbus_init_irq(dev, &fdctrl->irq);
2022 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2023
2024 fdctrl->sun4m = 1;
2025 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2026 return fdctrl_init_common(fdctrl);
2027 }
2028
2029 static const VMStateDescription vmstate_isa_fdc ={
2030 .name = "fdc",
2031 .version_id = 2,
2032 .minimum_version_id = 2,
2033 .fields = (VMStateField []) {
2034 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2035 VMSTATE_END_OF_LIST()
2036 }
2037 };
2038
2039 static ISADeviceInfo isa_fdc_info = {
2040 .init = isabus_fdc_init1,
2041 .qdev.name = "isa-fdc",
2042 .qdev.size = sizeof(FDCtrlISABus),
2043 .qdev.no_user = 1,
2044 .qdev.vmsd = &vmstate_isa_fdc,
2045 .qdev.reset = fdctrl_external_reset_isa,
2046 .qdev.props = (Property[]) {
2047 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2048 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2049 DEFINE_PROP_END_OF_LIST(),
2050 },
2051 };
2052
2053 static const VMStateDescription vmstate_sysbus_fdc ={
2054 .name = "fdc",
2055 .version_id = 2,
2056 .minimum_version_id = 2,
2057 .fields = (VMStateField []) {
2058 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2059 VMSTATE_END_OF_LIST()
2060 }
2061 };
2062
2063 static SysBusDeviceInfo sysbus_fdc_info = {
2064 .init = sysbus_fdc_init1,
2065 .qdev.name = "sysbus-fdc",
2066 .qdev.size = sizeof(FDCtrlSysBus),
2067 .qdev.vmsd = &vmstate_sysbus_fdc,
2068 .qdev.reset = fdctrl_external_reset_sysbus,
2069 .qdev.props = (Property[]) {
2070 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2071 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2072 DEFINE_PROP_END_OF_LIST(),
2073 },
2074 };
2075
2076 static SysBusDeviceInfo sun4m_fdc_info = {
2077 .init = sun4m_fdc_init1,
2078 .qdev.name = "SUNW,fdtwo",
2079 .qdev.size = sizeof(FDCtrlSysBus),
2080 .qdev.vmsd = &vmstate_sysbus_fdc,
2081 .qdev.reset = fdctrl_external_reset_sysbus,
2082 .qdev.props = (Property[]) {
2083 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2084 DEFINE_PROP_END_OF_LIST(),
2085 },
2086 };
2087
2088 static void fdc_register_devices(void)
2089 {
2090 isa_qdev_register(&isa_fdc_info);
2091 sysbus_register_withprop(&sysbus_fdc_info);
2092 sysbus_register_withprop(&sun4m_fdc_info);
2093 }
2094
2095 device_init(fdc_register_devices)
Stefan Hajnoczi's patches