hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21
  22 #define MP_MISC_BASE            0x80002000
  23 #define MP_MISC_SIZE            0x00001000
  24
  25 #define MP_ETH_BASE             0x80008000
  26 #define MP_ETH_SIZE             0x00001000
  27
  28 #define MP_WLAN_BASE            0x8000C000
  29 #define MP_WLAN_SIZE            0x00000800
  30
  31 #define MP_UART1_BASE           0x8000C840
  32 #define MP_UART2_BASE           0x8000C940
  33
  34 #define MP_GPIO_BASE            0x8000D000
  35 #define MP_GPIO_SIZE            0x00001000
  36
  37 #define MP_FLASHCFG_BASE        0x90006000
  38 #define MP_FLASHCFG_SIZE        0x00001000
  39
  40 #define MP_AUDIO_BASE           0x90007000
  41
  42 #define MP_PIC_BASE             0x90008000
  43 #define MP_PIC_SIZE             0x00001000
  44
  45 #define MP_PIT_BASE             0x90009000
  46 #define MP_PIT_SIZE             0x00001000
  47
  48 #define MP_LCD_BASE             0x9000c000
  49 #define MP_LCD_SIZE             0x00001000
  50
  51 #define MP_SRAM_BASE            0xC0000000
  52 #define MP_SRAM_SIZE            0x00020000
  53
  54 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  55 #define MP_FLASH_SIZE_MAX       32*1024*1024
  56
  57 #define MP_TIMER1_IRQ           4
  58 #define MP_TIMER2_IRQ           5
  59 #define MP_TIMER3_IRQ           6
  60 #define MP_TIMER4_IRQ           7
  61 #define MP_EHCI_IRQ             8
  62 #define MP_ETH_IRQ              9
  63 #define MP_UART1_IRQ            11
  64 #define MP_UART2_IRQ            11
  65 #define MP_GPIO_IRQ             12
  66 #define MP_RTC_IRQ              28
  67 #define MP_AUDIO_IRQ            30
  68
  69 /* Wolfson 8750 I2C address */
  70 #define MP_WM_ADDR              0x34
  71
  72 /* Ethernet register offsets */
  73 #define MP_ETH_SMIR             0x010
  74 #define MP_ETH_PCXR             0x408
  75 #define MP_ETH_SDCMR            0x448
  76 #define MP_ETH_ICR              0x450
  77 #define MP_ETH_IMR              0x458
  78 #define MP_ETH_FRDP0            0x480
  79 #define MP_ETH_FRDP1            0x484
  80 #define MP_ETH_FRDP2            0x488
  81 #define MP_ETH_FRDP3            0x48C
  82 #define MP_ETH_CRDP0            0x4A0
  83 #define MP_ETH_CRDP1            0x4A4
  84 #define MP_ETH_CRDP2            0x4A8
  85 #define MP_ETH_CRDP3            0x4AC
  86 #define MP_ETH_CTDP0            0x4E0
  87 #define MP_ETH_CTDP1            0x4E4
  88 #define MP_ETH_CTDP2            0x4E8
  89 #define MP_ETH_CTDP3            0x4EC
  90
  91 /* MII PHY access */
  92 #define MP_ETH_SMIR_DATA        0x0000FFFF
  93 #define MP_ETH_SMIR_ADDR        0x03FF0000
  94 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  95 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  96
  97 /* PHY registers */
  98 #define MP_ETH_PHY1_BMSR        0x00210000
  99 #define MP_ETH_PHY1_PHYSID1     0x00410000
 100 #define MP_ETH_PHY1_PHYSID2     0x00610000
 101
 102 #define MP_PHY_BMSR_LINK        0x0004
 103 #define MP_PHY_BMSR_AUTONEG     0x0008
 104
 105 #define MP_PHY_88E3015          0x01410E20
 106
 107 /* TX descriptor status */
 108 #define MP_ETH_TX_OWN           (1 << 31)
 109
 110 /* RX descriptor status */
 111 #define MP_ETH_RX_OWN           (1 << 31)
 112
 113 /* Interrupt cause/mask bits */
 114 #define MP_ETH_IRQ_RX_BIT       0
 115 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 116 #define MP_ETH_IRQ_TXHI_BIT     2
 117 #define MP_ETH_IRQ_TXLO_BIT     3
 118
 119 /* Port config bits */
 120 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 121
 122 /* SDMA command bits */
 123 #define MP_ETH_CMD_TXHI         (1 << 23)
 124 #define MP_ETH_CMD_TXLO         (1 << 22)
 125
 126 typedef struct mv88w8618_tx_desc {
 127     uint32_t cmdstat;
 128     uint16_t res;
 129     uint16_t bytes;
 130     uint32_t buffer;
 131     uint32_t next;
 132 } mv88w8618_tx_desc;
 133
 134 typedef struct mv88w8618_rx_desc {
 135     uint32_t cmdstat;
 136     uint16_t bytes;
 137     uint16_t buffer_size;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_rx_desc;
 141
 142 typedef struct mv88w8618_eth_state {
 143     SysBusDevice busdev;
 144     qemu_irq irq;
 145     uint32_t smir;
 146     uint32_t icr;
 147     uint32_t imr;
 148     int mmio_index;
 149     int vlan_header;
 150     uint32_t tx_queue[2];
 151     uint32_t rx_queue[4];
 152     uint32_t frx_queue[4];
 153     uint32_t cur_rx[4];
 154     VLANClientState *vc;
 155 } mv88w8618_eth_state;
 156
 157 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 158 {
 159     cpu_to_le32s(&desc->cmdstat);
 160     cpu_to_le16s(&desc->bytes);
 161     cpu_to_le16s(&desc->buffer_size);
 162     cpu_to_le32s(&desc->buffer);
 163     cpu_to_le32s(&desc->next);
 164     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 165 }
 166
 167 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 168 {
 169     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 170     le32_to_cpus(&desc->cmdstat);
 171     le16_to_cpus(&desc->bytes);
 172     le16_to_cpus(&desc->buffer_size);
 173     le32_to_cpus(&desc->buffer);
 174     le32_to_cpus(&desc->next);
 175 }
 176
 177 static int eth_can_receive(VLANClientState *vc)
 178 {
 179     return 1;
 180 }
 181
 182 static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
 183 {
 184     mv88w8618_eth_state *s = vc->opaque;
 185     uint32_t desc_addr;
 186     mv88w8618_rx_desc desc;
 187     int i;
 188
 189     for (i = 0; i < 4; i++) {
 190         desc_addr = s->cur_rx[i];
 191         if (!desc_addr) {
 192             continue;
 193         }
 194         do {
 195             eth_rx_desc_get(desc_addr, &desc);
 196             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 197                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 198                                           buf, size);
 199                 desc.bytes = size + s->vlan_header;
 200                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 201                 s->cur_rx[i] = desc.next;
 202
 203                 s->icr |= MP_ETH_IRQ_RX;
 204                 if (s->icr & s->imr) {
 205                     qemu_irq_raise(s->irq);
 206                 }
 207                 eth_rx_desc_put(desc_addr, &desc);
 208                 return size;
 209             }
 210             desc_addr = desc.next;
 211         } while (desc_addr != s->rx_queue[i]);
 212     }
 213     return size;
 214 }
 215
 216 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 217 {
 218     cpu_to_le32s(&desc->cmdstat);
 219     cpu_to_le16s(&desc->res);
 220     cpu_to_le16s(&desc->bytes);
 221     cpu_to_le32s(&desc->buffer);
 222     cpu_to_le32s(&desc->next);
 223     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 224 }
 225
 226 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 227 {
 228     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 229     le32_to_cpus(&desc->cmdstat);
 230     le16_to_cpus(&desc->res);
 231     le16_to_cpus(&desc->bytes);
 232     le32_to_cpus(&desc->buffer);
 233     le32_to_cpus(&desc->next);
 234 }
 235
 236 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 237 {
 238     uint32_t desc_addr = s->tx_queue[queue_index];
 239     mv88w8618_tx_desc desc;
 240     uint8_t buf[2048];
 241     int len;
 242
 243     if (!desc_addr) {
 244         return;
 245     }
 246     do {
 247         eth_tx_desc_get(desc_addr, &desc);
 248         if (desc.cmdstat & MP_ETH_TX_OWN) {
 249             len = desc.bytes;
 250             if (len < 2048) {
 251                 cpu_physical_memory_read(desc.buffer, buf, len);
 252                 qemu_send_packet(s->vc, buf, len);
 253             }
 254             desc.cmdstat &= ~MP_ETH_TX_OWN;
 255             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 256             eth_tx_desc_put(desc_addr, &desc);
 257         }
 258         desc_addr = desc.next;
 259     } while (desc_addr != s->tx_queue[queue_index]);
 260 }
 261
 262 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 263 {
 264     mv88w8618_eth_state *s = opaque;
 265
 266     switch (offset) {
 267     case MP_ETH_SMIR:
 268         if (s->smir & MP_ETH_SMIR_OPCODE) {
 269             switch (s->smir & MP_ETH_SMIR_ADDR) {
 270             case MP_ETH_PHY1_BMSR:
 271                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 272                        MP_ETH_SMIR_RDVALID;
 273             case MP_ETH_PHY1_PHYSID1:
 274                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 275             case MP_ETH_PHY1_PHYSID2:
 276                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 277             default:
 278                 return MP_ETH_SMIR_RDVALID;
 279             }
 280         }
 281         return 0;
 282
 283     case MP_ETH_ICR:
 284         return s->icr;
 285
 286     case MP_ETH_IMR:
 287         return s->imr;
 288
 289     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 290         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 291
 292     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 293         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 294
 295     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 296         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 297
 298     default:
 299         return 0;
 300     }
 301 }
 302
 303 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 304                                 uint32_t value)
 305 {
 306     mv88w8618_eth_state *s = opaque;
 307
 308     switch (offset) {
 309     case MP_ETH_SMIR:
 310         s->smir = value;
 311         break;
 312
 313     case MP_ETH_PCXR:
 314         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 315         break;
 316
 317     case MP_ETH_SDCMR:
 318         if (value & MP_ETH_CMD_TXHI) {
 319             eth_send(s, 1);
 320         }
 321         if (value & MP_ETH_CMD_TXLO) {
 322             eth_send(s, 0);
 323         }
 324         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 325             qemu_irq_raise(s->irq);
 326         }
 327         break;
 328
 329     case MP_ETH_ICR:
 330         s->icr &= value;
 331         break;
 332
 333     case MP_ETH_IMR:
 334         s->imr = value;
 335         if (s->icr & s->imr) {
 336             qemu_irq_raise(s->irq);
 337         }
 338         break;
 339
 340     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 341         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 342         break;
 343
 344     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 345         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 346             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 347         break;
 348
 349     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 350         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 351         break;
 352     }
 353 }
 354
 355 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 356     mv88w8618_eth_read,
 357     mv88w8618_eth_read,
 358     mv88w8618_eth_read
 359 };
 360
 361 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 362     mv88w8618_eth_write,
 363     mv88w8618_eth_write,
 364     mv88w8618_eth_write
 365 };
 366
 367 static void eth_cleanup(VLANClientState *vc)
 368 {
 369     mv88w8618_eth_state *s = vc->opaque;
 370
 371     cpu_unregister_io_memory(s->mmio_index);
 372
 373     qemu_free(s);
 374 }
 375
 376 static int mv88w8618_eth_init(SysBusDevice *dev)
 377 {
 378     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 379
 380     sysbus_init_irq(dev, &s->irq);
 381     s->vc = qdev_get_vlan_client(&dev->qdev,
 382                                  eth_can_receive, eth_receive, NULL,
 383                                  eth_cleanup, s);
 384     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 385                                            mv88w8618_eth_writefn, s);
 386     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 387     return 0;
 388 }
 389
 390 /* LCD register offsets */
 391 #define MP_LCD_IRQCTRL          0x180
 392 #define MP_LCD_IRQSTAT          0x184
 393 #define MP_LCD_SPICTRL          0x1ac
 394 #define MP_LCD_INST             0x1bc
 395 #define MP_LCD_DATA             0x1c0
 396
 397 /* Mode magics */
 398 #define MP_LCD_SPI_DATA         0x00100011
 399 #define MP_LCD_SPI_CMD          0x00104011
 400 #define MP_LCD_SPI_INVALID      0x00000000
 401
 402 /* Commmands */
 403 #define MP_LCD_INST_SETPAGE0    0xB0
 404 /* ... */
 405 #define MP_LCD_INST_SETPAGE7    0xB7
 406
 407 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 408
 409 typedef struct musicpal_lcd_state {
 410     SysBusDevice busdev;
 411     uint32_t brightness;
 412     uint32_t mode;
 413     uint32_t irqctrl;
 414     int page;
 415     int page_off;
 416     DisplayState *ds;
 417     uint8_t video_ram[128*64/8];
 418 } musicpal_lcd_state;
 419
 420 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 421 {
 422     switch (s->brightness) {
 423     case 7:
 424         return col;
 425     case 0:
 426         return 0;
 427     default:
 428         return (col * s->brightness) / 7;
 429     }
 430 }
 431
 432 #define SET_LCD_PIXEL(depth, type) \
 433 static inline void glue(set_lcd_pixel, depth) \
 434         (musicpal_lcd_state *s, int x, int y, type col) \
 435 { \
 436     int dx, dy; \
 437     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 438 \
 439     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 440         for (dx = 0; dx < 3; dx++, pixel++) \
 441             *pixel = col; \
 442 }
 443 SET_LCD_PIXEL(8, uint8_t)
 444 SET_LCD_PIXEL(16, uint16_t)
 445 SET_LCD_PIXEL(32, uint32_t)
 446
 447 #include "pixel_ops.h"
 448
 449 static void lcd_refresh(void *opaque)
 450 {
 451     musicpal_lcd_state *s = opaque;
 452     int x, y, col;
 453
 454     switch (ds_get_bits_per_pixel(s->ds)) {
 455     case 0:
 456         return;
 457 #define LCD_REFRESH(depth, func) \
 458     case depth: \
 459         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 460                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 461                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 462         for (x = 0; x < 128; x++) { \
 463             for (y = 0; y < 64; y++) { \
 464                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 465                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 466                 } else { \
 467                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 468                 } \
 469             } \
 470         } \
 471         break;
 472     LCD_REFRESH(8, rgb_to_pixel8)
 473     LCD_REFRESH(16, rgb_to_pixel16)
 474     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 475                      rgb_to_pixel32bgr : rgb_to_pixel32))
 476     default:
 477         hw_error("unsupported colour depth %i\n",
 478                   ds_get_bits_per_pixel(s->ds));
 479     }
 480
 481     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 482 }
 483
 484 static void lcd_invalidate(void *opaque)
 485 {
 486 }
 487
 488 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 489 {
 490     musicpal_lcd_state *s = opaque;
 491     s->brightness &= ~(1 << irq);
 492     s->brightness |= level << irq;
 493 }
 494
 495 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 496 {
 497     musicpal_lcd_state *s = opaque;
 498
 499     switch (offset) {
 500     case MP_LCD_IRQCTRL:
 501         return s->irqctrl;
 502
 503     default:
 504         return 0;
 505     }
 506 }
 507
 508 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 509                                uint32_t value)
 510 {
 511     musicpal_lcd_state *s = opaque;
 512
 513     switch (offset) {
 514     case MP_LCD_IRQCTRL:
 515         s->irqctrl = value;
 516         break;
 517
 518     case MP_LCD_SPICTRL:
 519         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 520             s->mode = value;
 521         } else {
 522             s->mode = MP_LCD_SPI_INVALID;
 523         }
 524         break;
 525
 526     case MP_LCD_INST:
 527         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 528             s->page = value - MP_LCD_INST_SETPAGE0;
 529             s->page_off = 0;
 530         }
 531         break;
 532
 533     case MP_LCD_DATA:
 534         if (s->mode == MP_LCD_SPI_CMD) {
 535             if (value >= MP_LCD_INST_SETPAGE0 &&
 536                 value <= MP_LCD_INST_SETPAGE7) {
 537                 s->page = value - MP_LCD_INST_SETPAGE0;
 538                 s->page_off = 0;
 539             }
 540         } else if (s->mode == MP_LCD_SPI_DATA) {
 541             s->video_ram[s->page*128 + s->page_off] = value;
 542             s->page_off = (s->page_off + 1) & 127;
 543         }
 544         break;
 545     }
 546 }
 547
 548 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 549     musicpal_lcd_read,
 550     musicpal_lcd_read,
 551     musicpal_lcd_read
 552 };
 553
 554 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 555     musicpal_lcd_write,
 556     musicpal_lcd_write,
 557     musicpal_lcd_write
 558 };
 559
 560 static int musicpal_lcd_init(SysBusDevice *dev)
 561 {
 562     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 563     int iomemtype;
 564
 565     s->brightness = 7;
 566
 567     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 568                                        musicpal_lcd_writefn, s);
 569     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 570
 571     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 572                                  NULL, NULL, s);
 573     qemu_console_resize(s->ds, 128*3, 64*3);
 574
 575     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 576
 577     return 0;
 578 }
 579
 580 /* PIC register offsets */
 581 #define MP_PIC_STATUS           0x00
 582 #define MP_PIC_ENABLE_SET       0x08
 583 #define MP_PIC_ENABLE_CLR       0x0C
 584
 585 typedef struct mv88w8618_pic_state
 586 {
 587     SysBusDevice busdev;
 588     uint32_t level;
 589     uint32_t enabled;
 590     qemu_irq parent_irq;
 591 } mv88w8618_pic_state;
 592
 593 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 594 {
 595     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 596 }
 597
 598 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 599 {
 600     mv88w8618_pic_state *s = opaque;
 601
 602     if (level) {
 603         s->level |= 1 << irq;
 604     } else {
 605         s->level &= ~(1 << irq);
 606     }
 607     mv88w8618_pic_update(s);
 608 }
 609
 610 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 611 {
 612     mv88w8618_pic_state *s = opaque;
 613
 614     switch (offset) {
 615     case MP_PIC_STATUS:
 616         return s->level & s->enabled;
 617
 618     default:
 619         return 0;
 620     }
 621 }
 622
 623 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 624                                 uint32_t value)
 625 {
 626     mv88w8618_pic_state *s = opaque;
 627
 628     switch (offset) {
 629     case MP_PIC_ENABLE_SET:
 630         s->enabled |= value;
 631         break;
 632
 633     case MP_PIC_ENABLE_CLR:
 634         s->enabled &= ~value;
 635         s->level &= ~value;
 636         break;
 637     }
 638     mv88w8618_pic_update(s);
 639 }
 640
 641 static void mv88w8618_pic_reset(void *opaque)
 642 {
 643     mv88w8618_pic_state *s = opaque;
 644
 645     s->level = 0;
 646     s->enabled = 0;
 647 }
 648
 649 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 650     mv88w8618_pic_read,
 651     mv88w8618_pic_read,
 652     mv88w8618_pic_read
 653 };
 654
 655 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 656     mv88w8618_pic_write,
 657     mv88w8618_pic_write,
 658     mv88w8618_pic_write
 659 };
 660
 661 static int mv88w8618_pic_init(SysBusDevice *dev)
 662 {
 663     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 664     int iomemtype;
 665
 666     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 667     sysbus_init_irq(dev, &s->parent_irq);
 668     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 669                                        mv88w8618_pic_writefn, s);
 670     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 671
 672     qemu_register_reset(mv88w8618_pic_reset, s);
 673     return 0;
 674 }
 675
 676 /* PIT register offsets */
 677 #define MP_PIT_TIMER1_LENGTH    0x00
 678 /* ... */
 679 #define MP_PIT_TIMER4_LENGTH    0x0C
 680 #define MP_PIT_CONTROL          0x10
 681 #define MP_PIT_TIMER1_VALUE     0x14
 682 /* ... */
 683 #define MP_PIT_TIMER4_VALUE     0x20
 684 #define MP_BOARD_RESET          0x34
 685
 686 /* Magic board reset value (probably some watchdog behind it) */
 687 #define MP_BOARD_RESET_MAGIC    0x10000
 688
 689 typedef struct mv88w8618_timer_state {
 690     ptimer_state *ptimer;
 691     uint32_t limit;
 692     int freq;
 693     qemu_irq irq;
 694 } mv88w8618_timer_state;
 695
 696 typedef struct mv88w8618_pit_state {
 697     SysBusDevice busdev;
 698     mv88w8618_timer_state timer[4];
 699     uint32_t control;
 700 } mv88w8618_pit_state;
 701
 702 static void mv88w8618_timer_tick(void *opaque)
 703 {
 704     mv88w8618_timer_state *s = opaque;
 705
 706     qemu_irq_raise(s->irq);
 707 }
 708
 709 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 710                                  uint32_t freq)
 711 {
 712     QEMUBH *bh;
 713
 714     sysbus_init_irq(dev, &s->irq);
 715     s->freq = freq;
 716
 717     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 718     s->ptimer = ptimer_init(bh);
 719 }
 720
 721 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 722 {
 723     mv88w8618_pit_state *s = opaque;
 724     mv88w8618_timer_state *t;
 725
 726     switch (offset) {
 727     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 728         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 729         return ptimer_get_count(t->ptimer);
 730
 731     default:
 732         return 0;
 733     }
 734 }
 735
 736 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 737                                 uint32_t value)
 738 {
 739     mv88w8618_pit_state *s = opaque;
 740     mv88w8618_timer_state *t;
 741     int i;
 742
 743     switch (offset) {
 744     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 745         t = &s->timer[offset >> 2];
 746         t->limit = value;
 747         ptimer_set_limit(t->ptimer, t->limit, 1);
 748         break;
 749
 750     case MP_PIT_CONTROL:
 751         for (i = 0; i < 4; i++) {
 752             if (value & 0xf) {
 753                 t = &s->timer[i];
 754                 ptimer_set_limit(t->ptimer, t->limit, 0);
 755                 ptimer_set_freq(t->ptimer, t->freq);
 756                 ptimer_run(t->ptimer, 0);
 757             }
 758             value >>= 4;
 759         }
 760         break;
 761
 762     case MP_BOARD_RESET:
 763         if (value == MP_BOARD_RESET_MAGIC) {
 764             qemu_system_reset_request();
 765         }
 766         break;
 767     }
 768 }
 769
 770 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 771     mv88w8618_pit_read,
 772     mv88w8618_pit_read,
 773     mv88w8618_pit_read
 774 };
 775
 776 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 777     mv88w8618_pit_write,
 778     mv88w8618_pit_write,
 779     mv88w8618_pit_write
 780 };
 781
 782 static int mv88w8618_pit_init(SysBusDevice *dev)
 783 {
 784     int iomemtype;
 785     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 786     int i;
 787
 788     /* Letting them all run at 1 MHz is likely just a pragmatic
 789      * simplification. */
 790     for (i = 0; i < 4; i++) {
 791         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 792     }
 793
 794     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 795                                        mv88w8618_pit_writefn, s);
 796     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 797     return 0;
 798 }
 799
 800 /* Flash config register offsets */
 801 #define MP_FLASHCFG_CFGR0    0x04
 802
 803 typedef struct mv88w8618_flashcfg_state {
 804     SysBusDevice busdev;
 805     uint32_t cfgr0;
 806 } mv88w8618_flashcfg_state;
 807
 808 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 809                                         target_phys_addr_t offset)
 810 {
 811     mv88w8618_flashcfg_state *s = opaque;
 812
 813     switch (offset) {
 814     case MP_FLASHCFG_CFGR0:
 815         return s->cfgr0;
 816
 817     default:
 818         return 0;
 819     }
 820 }
 821
 822 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 823                                      uint32_t value)
 824 {
 825     mv88w8618_flashcfg_state *s = opaque;
 826
 827     switch (offset) {
 828     case MP_FLASHCFG_CFGR0:
 829         s->cfgr0 = value;
 830         break;
 831     }
 832 }
 833
 834 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 835     mv88w8618_flashcfg_read,
 836     mv88w8618_flashcfg_read,
 837     mv88w8618_flashcfg_read
 838 };
 839
 840 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 841     mv88w8618_flashcfg_write,
 842     mv88w8618_flashcfg_write,
 843     mv88w8618_flashcfg_write
 844 };
 845
 846 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 847 {
 848     int iomemtype;
 849     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 850
 851     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 852     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 853                                        mv88w8618_flashcfg_writefn, s);
 854     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 855     return 0;
 856 }
 857
 858 /* Misc register offsets */
 859 #define MP_MISC_BOARD_REVISION  0x18
 860
 861 #define MP_BOARD_REVISION       0x31
 862
 863 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
 864 {
 865     switch (offset) {
 866     case MP_MISC_BOARD_REVISION:
 867         return MP_BOARD_REVISION;
 868
 869     default:
 870         return 0;
 871     }
 872 }
 873
 874 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
 875                                 uint32_t value)
 876 {
 877 }
 878
 879 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
 880     musicpal_misc_read,
 881     musicpal_misc_read,
 882     musicpal_misc_read,
 883 };
 884
 885 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
 886     musicpal_misc_write,
 887     musicpal_misc_write,
 888     musicpal_misc_write,
 889 };
 890
 891 static void musicpal_misc_init(void)
 892 {
 893     int iomemtype;
 894
 895     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
 896                                        musicpal_misc_writefn, NULL);
 897     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
 898 }
 899
 900 /* WLAN register offsets */
 901 #define MP_WLAN_MAGIC1          0x11c
 902 #define MP_WLAN_MAGIC2          0x124
 903
 904 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
 905 {
 906     switch (offset) {
 907     /* Workaround to allow loading the binary-only wlandrv.ko crap
 908      * from the original Freecom firmware. */
 909     case MP_WLAN_MAGIC1:
 910         return ~3;
 911     case MP_WLAN_MAGIC2:
 912         return -1;
 913
 914     default:
 915         return 0;
 916     }
 917 }
 918
 919 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
 920                                  uint32_t value)
 921 {
 922 }
 923
 924 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
 925     mv88w8618_wlan_read,
 926     mv88w8618_wlan_read,
 927     mv88w8618_wlan_read,
 928 };
 929
 930 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
 931     mv88w8618_wlan_write,
 932     mv88w8618_wlan_write,
 933     mv88w8618_wlan_write,
 934 };
 935
 936 static int mv88w8618_wlan_init(SysBusDevice *dev)
 937 {
 938     int iomemtype;
 939
 940     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
 941                                        mv88w8618_wlan_writefn, NULL);
 942     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
 943     return 0;
 944 }
 945
 946 /* GPIO register offsets */
 947 #define MP_GPIO_OE_LO           0x008
 948 #define MP_GPIO_OUT_LO          0x00c
 949 #define MP_GPIO_IN_LO           0x010
 950 #define MP_GPIO_IER_LO          0x014
 951 #define MP_GPIO_IMR_LO          0x018
 952 #define MP_GPIO_ISR_LO          0x020
 953 #define MP_GPIO_OE_HI           0x508
 954 #define MP_GPIO_OUT_HI          0x50c
 955 #define MP_GPIO_IN_HI           0x510
 956 #define MP_GPIO_IER_HI          0x514
 957 #define MP_GPIO_IMR_HI          0x518
 958 #define MP_GPIO_ISR_HI          0x520
 959
 960 /* GPIO bits & masks */
 961 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
 962 #define MP_GPIO_I2C_DATA_BIT    29
 963 #define MP_GPIO_I2C_CLOCK_BIT   30
 964
 965 /* LCD brightness bits in GPIO_OE_HI */
 966 #define MP_OE_LCD_BRIGHTNESS    0x0007
 967
 968 typedef struct musicpal_gpio_state {
 969     SysBusDevice busdev;
 970     uint32_t lcd_brightness;
 971     uint32_t out_state;
 972     uint32_t in_state;
 973     uint32_t ier;
 974     uint32_t imr;
 975     uint32_t isr;
 976     qemu_irq irq;
 977     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
 978 } musicpal_gpio_state;
 979
 980 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
 981     int i;
 982     uint32_t brightness;
 983
 984     /* compute brightness ratio */
 985     switch (s->lcd_brightness) {
 986     case 0x00000007:
 987         brightness = 0;
 988         break;
 989
 990     case 0x00020000:
 991         brightness = 1;
 992         break;
 993
 994     case 0x00020001:
 995         brightness = 2;
 996         break;
 997
 998     case 0x00040000:
 999         brightness = 3;
1000         break;
1001
1002     case 0x00010006:
1003         brightness = 4;
1004         break;
1005
1006     case 0x00020005:
1007         brightness = 5;
1008         break;
1009
1010     case 0x00040003:
1011         brightness = 6;
1012         break;
1013
1014     case 0x00030004:
1015     default:
1016         brightness = 7;
1017     }
1018
1019     /* set lcd brightness GPIOs  */
1020     for (i = 0; i <= 2; i++) {
1021         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1022     }
1023 }
1024
1025 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1026 {
1027     musicpal_gpio_state *s = opaque;
1028     uint32_t mask = 1 << pin;
1029     uint32_t delta = level << pin;
1030     uint32_t old = s->in_state & mask;
1031
1032     s->in_state &= ~mask;
1033     s->in_state |= delta;
1034
1035     if ((old ^ delta) &&
1036         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1037         s->isr = mask;
1038         qemu_irq_raise(s->irq);
1039     }
1040 }
1041
1042 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1043 {
1044     musicpal_gpio_state *s = opaque;
1045
1046     switch (offset) {
1047     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1048         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1049
1050     case MP_GPIO_OUT_LO:
1051         return s->out_state & 0xFFFF;
1052     case MP_GPIO_OUT_HI:
1053         return s->out_state >> 16;
1054
1055     case MP_GPIO_IN_LO:
1056         return s->in_state & 0xFFFF;
1057     case MP_GPIO_IN_HI:
1058         return s->in_state >> 16;
1059
1060     case MP_GPIO_IER_LO:
1061         return s->ier & 0xFFFF;
1062     case MP_GPIO_IER_HI:
1063         return s->ier >> 16;
1064
1065     case MP_GPIO_IMR_LO:
1066         return s->imr & 0xFFFF;
1067     case MP_GPIO_IMR_HI:
1068         return s->imr >> 16;
1069
1070     case MP_GPIO_ISR_LO:
1071         return s->isr & 0xFFFF;
1072     case MP_GPIO_ISR_HI:
1073         return s->isr >> 16;
1074
1075     default:
1076         return 0;
1077     }
1078 }
1079
1080 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1081                                 uint32_t value)
1082 {
1083     musicpal_gpio_state *s = opaque;
1084     switch (offset) {
1085     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1086         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1087                          (value & MP_OE_LCD_BRIGHTNESS);
1088         musicpal_gpio_brightness_update(s);
1089         break;
1090
1091     case MP_GPIO_OUT_LO:
1092         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1093         break;
1094     case MP_GPIO_OUT_HI:
1095         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1096         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1097                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1098         musicpal_gpio_brightness_update(s);
1099         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1100         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1101         break;
1102
1103     case MP_GPIO_IER_LO:
1104         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1105         break;
1106     case MP_GPIO_IER_HI:
1107         s->ier = (s->ier & 0xFFFF) | (value << 16);
1108         break;
1109
1110     case MP_GPIO_IMR_LO:
1111         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1112         break;
1113     case MP_GPIO_IMR_HI:
1114         s->imr = (s->imr & 0xFFFF) | (value << 16);
1115         break;
1116     }
1117 }
1118
1119 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1120     musicpal_gpio_read,
1121     musicpal_gpio_read,
1122     musicpal_gpio_read,
1123 };
1124
1125 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1126     musicpal_gpio_write,
1127     musicpal_gpio_write,
1128     musicpal_gpio_write,
1129 };
1130
1131 static void musicpal_gpio_reset(void *opaque)
1132 {
1133     musicpal_gpio_state *s = opaque;
1134
1135     s->lcd_brightness = 0;
1136     s->out_state = 0;
1137     s->in_state = 0xffffffff;
1138     s->ier = 0;
1139     s->imr = 0;
1140     s->isr = 0;
1141 }
1142
1143 static int musicpal_gpio_init(SysBusDevice *dev)
1144 {
1145     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1146     int iomemtype;
1147
1148     sysbus_init_irq(dev, &s->irq);
1149
1150     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1151                                        musicpal_gpio_writefn, s);
1152     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1153
1154     qemu_register_reset(musicpal_gpio_reset, s);
1155     musicpal_gpio_reset(s);
1156
1157     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1158
1159     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1160
1161     return 0;
1162 }
1163
1164 static SysBusDeviceInfo musicpal_gpio_info = {
1165     .init = musicpal_gpio_init,
1166     .qdev.name  = "musicpal_gpio",
1167     .qdev.size  = sizeof(musicpal_gpio_state),
1168     .qdev.reset = musicpal_gpio_reset,
1169 };
1170
1171 /* Keyboard codes & masks */
1172 #define KEY_RELEASED            0x80
1173 #define KEY_CODE                0x7f
1174
1175 #define KEYCODE_TAB             0x0f
1176 #define KEYCODE_ENTER           0x1c
1177 #define KEYCODE_F               0x21
1178 #define KEYCODE_M               0x32
1179
1180 #define KEYCODE_EXTENDED        0xe0
1181 #define KEYCODE_UP              0x48
1182 #define KEYCODE_DOWN            0x50
1183 #define KEYCODE_LEFT            0x4b
1184 #define KEYCODE_RIGHT           0x4d
1185
1186 #define MP_KEY_WHEEL_VOL       (1 << 0)
1187 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1188 #define MP_KEY_WHEEL_NAV       (1 << 2)
1189 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1190 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1191 #define MP_KEY_BTN_MENU        (1 << 5)
1192 #define MP_KEY_BTN_VOLUME      (1 << 6)
1193 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1194
1195 typedef struct musicpal_key_state {
1196     SysBusDevice busdev;
1197     uint32_t kbd_extended;
1198     uint32_t pressed_keys;
1199     qemu_irq out[8];
1200 } musicpal_key_state;
1201
1202 static void musicpal_key_event(void *opaque, int keycode)
1203 {
1204     musicpal_key_state *s = opaque;
1205     uint32_t event = 0;
1206     int i;
1207
1208     if (keycode == KEYCODE_EXTENDED) {
1209         s->kbd_extended = 1;
1210         return;
1211     }
1212
1213     if (s->kbd_extended) {
1214         switch (keycode & KEY_CODE) {
1215         case KEYCODE_UP:
1216             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1217             break;
1218
1219         case KEYCODE_DOWN:
1220             event = MP_KEY_WHEEL_NAV;
1221             break;
1222
1223         case KEYCODE_LEFT:
1224             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1225             break;
1226
1227         case KEYCODE_RIGHT:
1228             event = MP_KEY_WHEEL_VOL;
1229             break;
1230         }
1231     } else {
1232         switch (keycode & KEY_CODE) {
1233         case KEYCODE_F:
1234             event = MP_KEY_BTN_FAVORITS;
1235             break;
1236
1237         case KEYCODE_TAB:
1238             event = MP_KEY_BTN_VOLUME;
1239             break;
1240
1241         case KEYCODE_ENTER:
1242             event = MP_KEY_BTN_NAVIGATION;
1243             break;
1244
1245         case KEYCODE_M:
1246             event = MP_KEY_BTN_MENU;
1247             break;
1248         }
1249         /* Do not repeat already pressed buttons */
1250         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1251             event = 0;
1252         }
1253     }
1254
1255     if (event) {
1256         /* Raise GPIO pin first if repeating a key */
1257         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1258             for (i = 0; i <= 7; i++) {
1259                 if (event & (1 << i)) {
1260                     qemu_set_irq(s->out[i], 1);
1261                 }
1262             }
1263         }
1264         for (i = 0; i <= 7; i++) {
1265             if (event & (1 << i)) {
1266                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1267             }
1268         }
1269         if (keycode & KEY_RELEASED) {
1270             s->pressed_keys &= ~event;
1271         } else {
1272             s->pressed_keys |= event;
1273         }
1274     }
1275
1276     s->kbd_extended = 0;
1277 }
1278
1279 static int musicpal_key_init(SysBusDevice *dev)
1280 {
1281     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1282
1283     sysbus_init_mmio(dev, 0x0, 0);
1284
1285     s->kbd_extended = 0;
1286     s->pressed_keys = 0;
1287
1288     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1289
1290     qemu_add_kbd_event_handler(musicpal_key_event, s);
1291
1292     return 0;
1293 }
1294
1295 static struct arm_boot_info musicpal_binfo = {
1296     .loader_start = 0x0,
1297     .board_id = 0x20e,
1298 };
1299
1300 static void musicpal_init(ram_addr_t ram_size,
1301                const char *boot_device,
1302                const char *kernel_filename, const char *kernel_cmdline,
1303                const char *initrd_filename, const char *cpu_model)
1304 {
1305     CPUState *env;
1306     qemu_irq *cpu_pic;
1307     qemu_irq pic[32];
1308     DeviceState *dev;
1309     DeviceState *i2c_dev;
1310     DeviceState *lcd_dev;
1311     DeviceState *key_dev;
1312 #ifdef HAS_AUDIO
1313     DeviceState *wm8750_dev;
1314     SysBusDevice *s;
1315 #endif
1316     i2c_bus *i2c;
1317     int i;
1318     unsigned long flash_size;
1319     DriveInfo *dinfo;
1320     ram_addr_t sram_off;
1321
1322     if (!cpu_model) {
1323         cpu_model = "arm926";
1324     }
1325     env = cpu_init(cpu_model);
1326     if (!env) {
1327         fprintf(stderr, "Unable to find CPU definition\n");
1328         exit(1);
1329     }
1330     cpu_pic = arm_pic_init_cpu(env);
1331
1332     /* For now we use a fixed - the original - RAM size */
1333     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1334                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1335
1336     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1337     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1338
1339     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1340                                cpu_pic[ARM_PIC_CPU_IRQ]);
1341     for (i = 0; i < 32; i++) {
1342         pic[i] = qdev_get_gpio_in(dev, i);
1343     }
1344     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1345                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1346                           pic[MP_TIMER4_IRQ], NULL);
1347
1348     if (serial_hds[0]) {
1349         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1350                    serial_hds[0], 1);
1351     }
1352     if (serial_hds[1]) {
1353         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1354                    serial_hds[1], 1);
1355     }
1356
1357     /* Register flash */
1358     dinfo = drive_get(IF_PFLASH, 0, 0);
1359     if (dinfo) {
1360         flash_size = bdrv_getlength(dinfo->bdrv);
1361         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1362             flash_size != 32*1024*1024) {
1363             fprintf(stderr, "Invalid flash image size\n");
1364             exit(1);
1365         }
1366
1367         /*
1368          * The original U-Boot accesses the flash at 0xFE000000 instead of
1369          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1370          * image is smaller than 32 MB.
1371          */
1372         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1373                               dinfo->bdrv, 0x10000,
1374                               (flash_size + 0xffff) >> 16,
1375                               MP_FLASH_SIZE_MAX / flash_size,
1376                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1377                               0x5555, 0x2AAA);
1378     }
1379     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1380
1381     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1382     dev = qdev_create(NULL, "mv88w8618_eth");
1383     dev->nd = &nd_table[0];
1384     qdev_init(dev);
1385     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1386     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1387
1388     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1389
1390     musicpal_misc_init();
1391
1392     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1393     i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL);
1394     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1395
1396     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1397     key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1398
1399     /* I2C read data */
1400     qdev_connect_gpio_out(i2c_dev, 0,
1401                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1402     /* I2C data */
1403     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1404     /* I2C clock */
1405     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1406
1407     for (i = 0; i < 3; i++) {
1408         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1409     }
1410     for (i = 0; i < 4; i++) {
1411         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1412     }
1413     for (i = 4; i < 8; i++) {
1414         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1415     }
1416
1417 #ifdef HAS_AUDIO
1418     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1419     dev = qdev_create(NULL, "mv88w8618_audio");
1420     s = sysbus_from_qdev(dev);
1421     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1422     qdev_init(dev);
1423     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1424     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1425 #endif
1426
1427     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1428     musicpal_binfo.kernel_filename = kernel_filename;
1429     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1430     musicpal_binfo.initrd_filename = initrd_filename;
1431     arm_load_kernel(env, &musicpal_binfo);
1432 }
1433
1434 static QEMUMachine musicpal_machine = {
1435     .name = "musicpal",
1436     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1437     .init = musicpal_init,
1438 };
1439
1440 static void musicpal_machine_init(void)
1441 {
1442     qemu_register_machine(&musicpal_machine);
1443 }
1444
1445 machine_init(musicpal_machine_init);
1446
1447 static void musicpal_register_devices(void)
1448 {
1449     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1450                         mv88w8618_pic_init);
1451     sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state),
1452                         mv88w8618_pit_init);
1453     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1454                         mv88w8618_flashcfg_init);
1455     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1456                         mv88w8618_eth_init);
1457     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1458                         mv88w8618_wlan_init);
1459     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1460                         musicpal_lcd_init);
1461     sysbus_register_withprop(&musicpal_gpio_info);
1462     sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state),
1463                         musicpal_key_init);
1464 }
1465
1466 device_init(musicpal_register_devices)