target-ppc/kvm.c

   1 /*
   2  * PowerPC implementation of KVM hooks
   3  *
   4  * Copyright IBM Corp. 2007
   5  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   6  *
   7  * Authors:
   8  *  Jerone Young <jyoung5@us.ibm.com>
   9  *  Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
  10  *  Hollis Blanchard <hollisb@us.ibm.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  13  * See the COPYING file in the top-level directory.
  14  *
  15  */
  16
  17 #include <sys/types.h>
  18 #include <sys/ioctl.h>
  19 #include <sys/mman.h>
  20
  21 #include <linux/kvm.h>
  22
  23 #include "qemu-common.h"
  24 #include "qemu-timer.h"
  25 #include "sysemu.h"
  26 #include "kvm.h"
  27 #include "kvm_ppc.h"
  28 #include "cpu.h"
  29 #include "device_tree.h"
  30
  31 //#define DEBUG_KVM
  32
  33 #ifdef DEBUG_KVM
  34 #define dprintf(fmt, ...) \
  35     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  36 #else
  37 #define dprintf(fmt, ...) \
  38     do { } while (0)
  39 #endif
  40
  41 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  42     KVM_CAP_LAST_INFO
  43 };
  44
  45 static int cap_interrupt_unset = false;
  46 static int cap_interrupt_level = false;
  47 static int cap_segstate;
  48 static int cap_booke_sregs;
  49
  50 /* XXX We have a race condition where we actually have a level triggered
  51  *     interrupt, but the infrastructure can't expose that yet, so the guest
  52  *     takes but ignores it, goes to sleep and never gets notified that there's
  53  *     still an interrupt pending.
  54  *
  55  *     As a quick workaround, let's just wake up again 20 ms after we injected
  56  *     an interrupt. That way we can assure that we're always reinjecting
  57  *     interrupts in case the guest swallowed them.
  58  */
  59 static QEMUTimer *idle_timer;
  60
  61 static void kvm_kick_env(void *env)
  62 {
  63     qemu_cpu_kick(env);
  64 }
  65
  66 int kvm_arch_init(KVMState *s)
  67 {
  68 #ifdef KVM_CAP_PPC_UNSET_IRQ
  69     cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
  70 #endif
  71 #ifdef KVM_CAP_PPC_IRQ_LEVEL
  72     cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
  73 #endif
  74 #ifdef KVM_CAP_PPC_SEGSTATE
  75     cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
  76 #endif
  77 #ifdef KVM_CAP_PPC_BOOKE_SREGS
  78     cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
  79 #endif
  80
  81     if (!cap_interrupt_level) {
  82         fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
  83                         "VM to stall at times!\n");
  84     }
  85
  86     return 0;
  87 }
  88
  89 static int kvm_arch_sync_sregs(CPUState *cenv)
  90 {
  91     struct kvm_sregs sregs;
  92     int ret;
  93
  94     if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
  95         /* What we're really trying to say is "if we're on BookE, we use
  96            the native PVR for now". This is the only sane way to check
  97            it though, so we potentially confuse users that they can run
  98            BookE guests on BookS. Let's hope nobody dares enough :) */
  99         return 0;
 100     } else {
 101         if (!cap_segstate) {
 102             fprintf(stderr, "kvm error: missing PVR setting capability\n");
 103             return -ENOSYS;
 104         }
 105     }
 106
 107     ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs);
 108     if (ret) {
 109         return ret;
 110     }
 111
 112     sregs.pvr = cenv->spr[SPR_PVR];
 113     return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
 114 }
 115
 116 int kvm_arch_init_vcpu(CPUState *cenv)
 117 {
 118     int ret;
 119
 120     ret = kvm_arch_sync_sregs(cenv);
 121     if (ret) {
 122         return ret;
 123     }
 124
 125     idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
 126
 127     return ret;
 128 }
 129
 130 void kvm_arch_reset_vcpu(CPUState *env)
 131 {
 132 }
 133
 134 int kvm_arch_put_registers(CPUState *env, int level)
 135 {
 136     struct kvm_regs regs;
 137     int ret;
 138     int i;
 139
 140     ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 141     if (ret < 0)
 142         return ret;
 143
 144     regs.ctr = env->ctr;
 145     regs.lr  = env->lr;
 146     regs.xer = env->xer;
 147     regs.msr = env->msr;
 148     regs.pc = env->nip;
 149
 150     regs.srr0 = env->spr[SPR_SRR0];
 151     regs.srr1 = env->spr[SPR_SRR1];
 152
 153     regs.sprg0 = env->spr[SPR_SPRG0];
 154     regs.sprg1 = env->spr[SPR_SPRG1];
 155     regs.sprg2 = env->spr[SPR_SPRG2];
 156     regs.sprg3 = env->spr[SPR_SPRG3];
 157     regs.sprg4 = env->spr[SPR_SPRG4];
 158     regs.sprg5 = env->spr[SPR_SPRG5];
 159     regs.sprg6 = env->spr[SPR_SPRG6];
 160     regs.sprg7 = env->spr[SPR_SPRG7];
 161
 162     regs.pid = env->spr[SPR_BOOKE_PID];
 163
 164     for (i = 0;i < 32; i++)
 165         regs.gpr[i] = env->gpr[i];
 166
 167     ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 168     if (ret < 0)
 169         return ret;
 170
 171     return ret;
 172 }
 173
 174 int kvm_arch_get_registers(CPUState *env)
 175 {
 176     struct kvm_regs regs;
 177     struct kvm_sregs sregs;
 178     uint32_t cr;
 179     int i, ret;
 180
 181     ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 182     if (ret < 0)
 183         return ret;
 184
 185     cr = regs.cr;
 186     for (i = 7; i >= 0; i--) {
 187         env->crf[i] = cr & 15;
 188         cr >>= 4;
 189     }
 190
 191     env->ctr = regs.ctr;
 192     env->lr = regs.lr;
 193     env->xer = regs.xer;
 194     env->msr = regs.msr;
 195     env->nip = regs.pc;
 196
 197     env->spr[SPR_SRR0] = regs.srr0;
 198     env->spr[SPR_SRR1] = regs.srr1;
 199
 200     env->spr[SPR_SPRG0] = regs.sprg0;
 201     env->spr[SPR_SPRG1] = regs.sprg1;
 202     env->spr[SPR_SPRG2] = regs.sprg2;
 203     env->spr[SPR_SPRG3] = regs.sprg3;
 204     env->spr[SPR_SPRG4] = regs.sprg4;
 205     env->spr[SPR_SPRG5] = regs.sprg5;
 206     env->spr[SPR_SPRG6] = regs.sprg6;
 207     env->spr[SPR_SPRG7] = regs.sprg7;
 208
 209     env->spr[SPR_BOOKE_PID] = regs.pid;
 210
 211     for (i = 0;i < 32; i++)
 212         env->gpr[i] = regs.gpr[i];
 213
 214     if (cap_booke_sregs) {
 215         ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 216         if (ret < 0) {
 217             return ret;
 218         }
 219
 220 #ifdef KVM_CAP_PPC_BOOKE_SREGS
 221         if (sregs.u.e.features & KVM_SREGS_E_BASE) {
 222             env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
 223             env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
 224             env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
 225             env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
 226             env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
 227             env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
 228             env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
 229             env->spr[SPR_DECR] = sregs.u.e.dec;
 230             env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
 231             env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
 232             env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
 233         }
 234
 235         if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
 236             env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
 237             env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
 238             env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
 239             env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
 240             env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
 241         }
 242
 243         if (sregs.u.e.features & KVM_SREGS_E_64) {
 244             env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
 245         }
 246
 247         if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
 248             env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
 249         }
 250
 251         if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
 252             env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
 253             env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
 254             env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
 255             env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
 256             env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
 257             env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
 258             env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
 259             env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
 260             env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
 261             env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
 262             env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
 263             env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
 264             env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
 265             env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
 266             env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
 267             env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
 268
 269             if (sregs.u.e.features & KVM_SREGS_E_SPE) {
 270                 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
 271                 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
 272                 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
 273             }
 274
 275             if (sregs.u.e.features & KVM_SREGS_E_PM) {
 276                 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
 277             }
 278
 279             if (sregs.u.e.features & KVM_SREGS_E_PC) {
 280                 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
 281                 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
 282             }
 283         }
 284
 285         if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
 286             env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
 287             env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
 288             env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
 289             env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
 290             env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
 291             env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
 292             env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
 293             env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
 294             env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
 295             env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
 296         }
 297
 298         if (sregs.u.e.features & KVM_SREGS_EXP) {
 299             env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
 300         }
 301
 302         if (sregs.u.e.features & KVM_SREGS_E_PD) {
 303             env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
 304             env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
 305         }
 306
 307         if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
 308             env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
 309             env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
 310             env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
 311
 312             if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
 313                 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
 314                 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
 315             }
 316         }
 317 #endif
 318     }
 319
 320     if (cap_segstate) {
 321         ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 322         if (ret < 0) {
 323             return ret;
 324         }
 325
 326 #ifdef KVM_CAP_PPC_SEGSTATE
 327         ppc_store_sdr1(env, sregs.u.s.sdr1);
 328
 329         /* Sync SLB */
 330 #ifdef TARGET_PPC64
 331         for (i = 0; i < 64; i++) {
 332             ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,
 333                                sregs.u.s.ppc64.slb[i].slbv);
 334         }
 335 #endif
 336
 337         /* Sync SRs */
 338         for (i = 0; i < 16; i++) {
 339             env->sr[i] = sregs.u.s.ppc32.sr[i];
 340         }
 341
 342         /* Sync BATs */
 343         for (i = 0; i < 8; i++) {
 344             env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
 345             env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
 346             env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
 347             env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
 348         }
 349 #endif
 350     }
 351
 352     return 0;
 353 }
 354
 355 int kvmppc_set_interrupt(CPUState *env, int irq, int level)
 356 {
 357     unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
 358
 359     if (irq != PPC_INTERRUPT_EXT) {
 360         return 0;
 361     }
 362
 363     if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
 364         return 0;
 365     }
 366
 367     kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq);
 368
 369     return 0;
 370 }
 371
 372 #if defined(TARGET_PPCEMB)
 373 #define PPC_INPUT_INT PPC40x_INPUT_INT
 374 #elif defined(TARGET_PPC64)
 375 #define PPC_INPUT_INT PPC970_INPUT_INT
 376 #else
 377 #define PPC_INPUT_INT PPC6xx_INPUT_INT
 378 #endif
 379
 380 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 381 {
 382     int r;
 383     unsigned irq;
 384
 385     /* PowerPC Qemu tracks the various core input pins (interrupt, critical
 386      * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
 387     if (!cap_interrupt_level &&
 388         run->ready_for_interrupt_injection &&
 389         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 390         (env->irq_input_state & (1<<PPC_INPUT_INT)))
 391     {
 392         /* For now KVM disregards the 'irq' argument. However, in the
 393          * future KVM could cache it in-kernel to avoid a heavyweight exit
 394          * when reading the UIC.
 395          */
 396         irq = KVM_INTERRUPT_SET;
 397
 398         dprintf("injected interrupt %d\n", irq);
 399         r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
 400         if (r < 0)
 401             printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 402
 403         /* Always wake up soon in case the interrupt was level based */
 404         qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) +
 405                        (get_ticks_per_sec() / 50));
 406     }
 407
 408     /* We don't know if there are more interrupts pending after this. However,
 409      * the guest will return to userspace in the course of handling this one
 410      * anyways, so we will get a chance to deliver the rest. */
 411 }
 412
 413 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 414 {
 415 }
 416
 417 int kvm_arch_process_async_events(CPUState *env)
 418 {
 419     return 0;
 420 }
 421
 422 static int kvmppc_handle_halt(CPUState *env)
 423 {
 424     if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
 425         env->halted = 1;
 426         env->exception_index = EXCP_HLT;
 427     }
 428
 429     return 0;
 430 }
 431
 432 /* map dcr access to existing qemu dcr emulation */
 433 static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data)
 434 {
 435     if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
 436         fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
 437
 438     return 0;
 439 }
 440
 441 static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data)
 442 {
 443     if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
 444         fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
 445
 446     return 0;
 447 }
 448
 449 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 450 {
 451     int ret;
 452
 453     switch (run->exit_reason) {
 454     case KVM_EXIT_DCR:
 455         if (run->dcr.is_write) {
 456             dprintf("handle dcr write\n");
 457             ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
 458         } else {
 459             dprintf("handle dcr read\n");
 460             ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
 461         }
 462         break;
 463     case KVM_EXIT_HLT:
 464         dprintf("handle halt\n");
 465         ret = kvmppc_handle_halt(env);
 466         break;
 467     default:
 468         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
 469         ret = -1;
 470         break;
 471     }
 472
 473     return ret;
 474 }
 475
 476 static int read_cpuinfo(const char *field, char *value, int len)
 477 {
 478     FILE *f;
 479     int ret = -1;
 480     int field_len = strlen(field);
 481     char line[512];
 482
 483     f = fopen("/proc/cpuinfo", "r");
 484     if (!f) {
 485         return -1;
 486     }
 487
 488     do {
 489         if(!fgets(line, sizeof(line), f)) {
 490             break;
 491         }
 492         if (!strncmp(line, field, field_len)) {
 493             strncpy(value, line, len);
 494             ret = 0;
 495             break;
 496         }
 497     } while(*line);
 498
 499     fclose(f);
 500
 501     return ret;
 502 }
 503
 504 uint32_t kvmppc_get_tbfreq(void)
 505 {
 506     char line[512];
 507     char *ns;
 508     uint32_t retval = get_ticks_per_sec();
 509
 510     if (read_cpuinfo("timebase", line, sizeof(line))) {
 511         return retval;
 512     }
 513
 514     if (!(ns = strchr(line, ':'))) {
 515         return retval;
 516     }
 517
 518     ns++;
 519
 520     retval = atoi(ns);
 521     return retval;
 522 }
 523
 524 int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
 525 {
 526     uint32_t *hc = (uint32_t*)buf;
 527
 528 #ifdef KVM_CAP_PPC_GET_PVINFO
 529     struct kvm_ppc_pvinfo pvinfo;
 530
 531     if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
 532         !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) {
 533         memcpy(buf, pvinfo.hcall, buf_len);
 534
 535         return 0;
 536     }
 537 #endif
 538
 539     /*
 540      * Fallback to always fail hypercalls:
 541      *
 542      *     li r3, -1
 543      *     nop
 544      *     nop
 545      *     nop
 546      */
 547
 548     hc[0] = 0x3860ffff;
 549     hc[1] = 0x60000000;
 550     hc[2] = 0x60000000;
 551     hc[3] = 0x60000000;
 552
 553     return 0;
 554 }
 555
 556 bool kvm_arch_stop_on_emulation_error(CPUState *env)
 557 {
 558     return true;
 559 }
 560
 561 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 562 {
 563     return 1;
 564 }
 565
 566 int kvm_arch_on_sigbus(int code, void *addr)
 567 {
 568     return 1;
 569 }