sh4/r2d: update pci, usb and kernel management
[qemu/sh4.git] / target-arm / machine.c
blob42ff5844c9f58e20970558aabb59f3549a886959
1 #include "hw/hw.h"
2 #include "hw/boards.h"
4 void register_machines(void)
6 qemu_register_machine(&integratorcp_machine);
7 qemu_register_machine(&versatilepb_machine);
8 qemu_register_machine(&versatileab_machine);
9 qemu_register_machine(&realview_machine);
10 qemu_register_machine(&akitapda_machine);
11 qemu_register_machine(&spitzpda_machine);
12 qemu_register_machine(&borzoipda_machine);
13 qemu_register_machine(&terrierpda_machine);
14 qemu_register_machine(&palmte_machine);
15 qemu_register_machine(&n800_machine);
16 qemu_register_machine(&n810_machine);
17 qemu_register_machine(&lm3s811evb_machine);
18 qemu_register_machine(&lm3s6965evb_machine);
19 qemu_register_machine(&connex_machine);
20 qemu_register_machine(&verdex_machine);
21 qemu_register_machine(&mainstone2_machine);
22 qemu_register_machine(&musicpal_machine);
23 qemu_register_machine(&tosapda_machine);
26 void cpu_save(QEMUFile *f, void *opaque)
28 int i;
29 CPUARMState *env = (CPUARMState *)opaque;
31 for (i = 0; i < 16; i++) {
32 qemu_put_be32(f, env->regs[i]);
34 qemu_put_be32(f, cpsr_read(env));
35 qemu_put_be32(f, env->spsr);
36 for (i = 0; i < 6; i++) {
37 qemu_put_be32(f, env->banked_spsr[i]);
38 qemu_put_be32(f, env->banked_r13[i]);
39 qemu_put_be32(f, env->banked_r14[i]);
41 for (i = 0; i < 5; i++) {
42 qemu_put_be32(f, env->usr_regs[i]);
43 qemu_put_be32(f, env->fiq_regs[i]);
45 qemu_put_be32(f, env->cp15.c0_cpuid);
46 qemu_put_be32(f, env->cp15.c0_cachetype);
47 qemu_put_be32(f, env->cp15.c1_sys);
48 qemu_put_be32(f, env->cp15.c1_coproc);
49 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
50 qemu_put_be32(f, env->cp15.c2_base0);
51 qemu_put_be32(f, env->cp15.c2_base1);
52 qemu_put_be32(f, env->cp15.c2_mask);
53 qemu_put_be32(f, env->cp15.c2_data);
54 qemu_put_be32(f, env->cp15.c2_insn);
55 qemu_put_be32(f, env->cp15.c3);
56 qemu_put_be32(f, env->cp15.c5_insn);
57 qemu_put_be32(f, env->cp15.c5_data);
58 for (i = 0; i < 8; i++) {
59 qemu_put_be32(f, env->cp15.c6_region[i]);
61 qemu_put_be32(f, env->cp15.c6_insn);
62 qemu_put_be32(f, env->cp15.c6_data);
63 qemu_put_be32(f, env->cp15.c9_insn);
64 qemu_put_be32(f, env->cp15.c9_data);
65 qemu_put_be32(f, env->cp15.c13_fcse);
66 qemu_put_be32(f, env->cp15.c13_context);
67 qemu_put_be32(f, env->cp15.c13_tls1);
68 qemu_put_be32(f, env->cp15.c13_tls2);
69 qemu_put_be32(f, env->cp15.c13_tls3);
70 qemu_put_be32(f, env->cp15.c15_cpar);
72 qemu_put_be32(f, env->features);
74 if (arm_feature(env, ARM_FEATURE_VFP)) {
75 for (i = 0; i < 16; i++) {
76 CPU_DoubleU u;
77 u.d = env->vfp.regs[i];
78 qemu_put_be32(f, u.l.upper);
79 qemu_put_be32(f, u.l.lower);
81 for (i = 0; i < 16; i++) {
82 qemu_put_be32(f, env->vfp.xregs[i]);
85 /* TODO: Should use proper FPSCR access functions. */
86 qemu_put_be32(f, env->vfp.vec_len);
87 qemu_put_be32(f, env->vfp.vec_stride);
89 if (arm_feature(env, ARM_FEATURE_VFP3)) {
90 for (i = 16; i < 32; i++) {
91 CPU_DoubleU u;
92 u.d = env->vfp.regs[i];
93 qemu_put_be32(f, u.l.upper);
94 qemu_put_be32(f, u.l.lower);
99 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
100 for (i = 0; i < 16; i++) {
101 qemu_put_be64(f, env->iwmmxt.regs[i]);
103 for (i = 0; i < 16; i++) {
104 qemu_put_be32(f, env->iwmmxt.cregs[i]);
108 if (arm_feature(env, ARM_FEATURE_M)) {
109 qemu_put_be32(f, env->v7m.other_sp);
110 qemu_put_be32(f, env->v7m.vecbase);
111 qemu_put_be32(f, env->v7m.basepri);
112 qemu_put_be32(f, env->v7m.control);
113 qemu_put_be32(f, env->v7m.current_sp);
114 qemu_put_be32(f, env->v7m.exception);
118 int cpu_load(QEMUFile *f, void *opaque, int version_id)
120 CPUARMState *env = (CPUARMState *)opaque;
121 int i;
123 if (version_id != CPU_SAVE_VERSION)
124 return -EINVAL;
126 for (i = 0; i < 16; i++) {
127 env->regs[i] = qemu_get_be32(f);
129 cpsr_write(env, qemu_get_be32(f), 0xffffffff);
130 env->spsr = qemu_get_be32(f);
131 for (i = 0; i < 6; i++) {
132 env->banked_spsr[i] = qemu_get_be32(f);
133 env->banked_r13[i] = qemu_get_be32(f);
134 env->banked_r14[i] = qemu_get_be32(f);
136 for (i = 0; i < 5; i++) {
137 env->usr_regs[i] = qemu_get_be32(f);
138 env->fiq_regs[i] = qemu_get_be32(f);
140 env->cp15.c0_cpuid = qemu_get_be32(f);
141 env->cp15.c0_cachetype = qemu_get_be32(f);
142 env->cp15.c1_sys = qemu_get_be32(f);
143 env->cp15.c1_coproc = qemu_get_be32(f);
144 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
145 env->cp15.c2_base0 = qemu_get_be32(f);
146 env->cp15.c2_base1 = qemu_get_be32(f);
147 env->cp15.c2_mask = qemu_get_be32(f);
148 env->cp15.c2_data = qemu_get_be32(f);
149 env->cp15.c2_insn = qemu_get_be32(f);
150 env->cp15.c3 = qemu_get_be32(f);
151 env->cp15.c5_insn = qemu_get_be32(f);
152 env->cp15.c5_data = qemu_get_be32(f);
153 for (i = 0; i < 8; i++) {
154 env->cp15.c6_region[i] = qemu_get_be32(f);
156 env->cp15.c6_insn = qemu_get_be32(f);
157 env->cp15.c6_data = qemu_get_be32(f);
158 env->cp15.c9_insn = qemu_get_be32(f);
159 env->cp15.c9_data = qemu_get_be32(f);
160 env->cp15.c13_fcse = qemu_get_be32(f);
161 env->cp15.c13_context = qemu_get_be32(f);
162 env->cp15.c13_tls1 = qemu_get_be32(f);
163 env->cp15.c13_tls2 = qemu_get_be32(f);
164 env->cp15.c13_tls3 = qemu_get_be32(f);
165 env->cp15.c15_cpar = qemu_get_be32(f);
167 env->features = qemu_get_be32(f);
169 if (arm_feature(env, ARM_FEATURE_VFP)) {
170 for (i = 0; i < 16; i++) {
171 CPU_DoubleU u;
172 u.l.upper = qemu_get_be32(f);
173 u.l.lower = qemu_get_be32(f);
174 env->vfp.regs[i] = u.d;
176 for (i = 0; i < 16; i++) {
177 env->vfp.xregs[i] = qemu_get_be32(f);
180 /* TODO: Should use proper FPSCR access functions. */
181 env->vfp.vec_len = qemu_get_be32(f);
182 env->vfp.vec_stride = qemu_get_be32(f);
184 if (arm_feature(env, ARM_FEATURE_VFP3)) {
185 for (i = 0; i < 16; i++) {
186 CPU_DoubleU u;
187 u.l.upper = qemu_get_be32(f);
188 u.l.lower = qemu_get_be32(f);
189 env->vfp.regs[i] = u.d;
194 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
195 for (i = 0; i < 16; i++) {
196 env->iwmmxt.regs[i] = qemu_get_be64(f);
198 for (i = 0; i < 16; i++) {
199 env->iwmmxt.cregs[i] = qemu_get_be32(f);
203 if (arm_feature(env, ARM_FEATURE_M)) {
204 env->v7m.other_sp = qemu_get_be32(f);
205 env->v7m.vecbase = qemu_get_be32(f);
206 env->v7m.basepri = qemu_get_be32(f);
207 env->v7m.control = qemu_get_be32(f);
208 env->v7m.current_sp = qemu_get_be32(f);
209 env->v7m.exception = qemu_get_be32(f);
212 return 0;