4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
34 # define PCI_DPRINTF(format, ...) do { } while (0)
40 pci_set_irq_fn set_irq
;
41 pci_map_irq_fn map_irq
;
42 pci_hotplug_fn hotplug
;
43 uint32_t config_reg
; /* XXX: suppress */
45 PCIDevice
*devices
[256];
46 PCIDevice
*parent_dev
;
48 /* The bus IRQ state is the logical OR of the connected devices.
49 Keep a count of the number of devices with raised IRQs. */
54 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
56 static struct BusInfo pci_bus_info
= {
58 .size
= sizeof(PCIBus
),
59 .print_dev
= pcibus_dev_print
,
60 .props
= (Property
[]) {
61 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
62 DEFINE_PROP_END_OF_LIST()
66 static void pci_update_mappings(PCIDevice
*d
);
67 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
69 target_phys_addr_t pci_mem_base
;
70 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
71 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
72 static PCIBus
*first_bus
;
74 static const VMStateDescription vmstate_pcibus
= {
77 .minimum_version_id
= 1,
78 .minimum_version_id_old
= 1,
79 .fields
= (VMStateField
[]) {
80 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
81 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
86 static int pci_bar(PCIDevice
*d
, int reg
)
90 if (reg
!= PCI_ROM_SLOT
)
91 return PCI_BASE_ADDRESS_0
+ reg
* 4;
93 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
94 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
97 static void pci_device_reset(PCIDevice
*dev
)
101 memset(dev
->irq_state
, 0, sizeof dev
->irq_state
);
102 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
104 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
105 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
106 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
107 if (!dev
->io_regions
[r
].size
) {
110 pci_set_long(dev
->config
+ pci_bar(dev
, r
), dev
->io_regions
[r
].type
);
112 pci_update_mappings(dev
);
115 static void pci_bus_reset(void *opaque
)
117 PCIBus
*bus
= opaque
;
120 for (i
= 0; i
< bus
->nirq
; i
++) {
121 bus
->irq_count
[i
] = 0;
123 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
124 if (bus
->devices
[i
]) {
125 pci_device_reset(bus
->devices
[i
]);
130 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
131 const char *name
, int devfn_min
)
135 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
136 bus
->devfn_min
= devfn_min
;
137 bus
->next
= first_bus
;
139 vmstate_register(nbus
++, &vmstate_pcibus
, bus
);
140 qemu_register_reset(pci_bus_reset
, bus
);
143 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
147 bus
= qemu_mallocz(sizeof(*bus
));
148 bus
->qbus
.qdev_allocated
= 1;
149 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
153 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
154 void *irq_opaque
, int nirq
)
156 bus
->set_irq
= set_irq
;
157 bus
->map_irq
= map_irq
;
158 bus
->irq_opaque
= irq_opaque
;
160 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
163 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
)
165 bus
->qbus
.allow_hotplug
= 1;
166 bus
->hotplug
= hotplug
;
169 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
170 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
171 void *irq_opaque
, int devfn_min
, int nirq
)
175 bus
= pci_bus_new(parent
, name
, devfn_min
);
176 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
180 static void pci_register_secondary_bus(PCIBus
*bus
,
182 pci_map_irq_fn map_irq
,
185 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
186 bus
->map_irq
= map_irq
;
187 bus
->parent_dev
= dev
;
188 bus
->next
= dev
->bus
->next
;
189 dev
->bus
->next
= bus
;
192 int pci_bus_num(PCIBus
*s
)
195 return 0; /* pci host bridge */
196 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
199 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
201 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
202 uint8_t config
[PCI_CONFIG_SPACE_SIZE
];
205 assert(size
== sizeof config
);
206 qemu_get_buffer(f
, config
, sizeof config
);
207 for (i
= 0; i
< sizeof config
; ++i
)
208 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
])
210 memcpy(s
->config
, config
, sizeof config
);
212 pci_update_mappings(s
);
217 /* just put buffer */
218 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
220 const uint8_t *v
= pv
;
221 qemu_put_buffer(f
, v
, size
);
224 static VMStateInfo vmstate_info_pci_config
= {
225 .name
= "pci config",
226 .get
= get_pci_config_device
,
227 .put
= put_pci_config_device
,
230 const VMStateDescription vmstate_pci_device
= {
233 .minimum_version_id
= 1,
234 .minimum_version_id_old
= 1,
235 .fields
= (VMStateField
[]) {
236 VMSTATE_INT32_LE(version_id
, PCIDevice
),
237 VMSTATE_SINGLE(config
, PCIDevice
, 0, vmstate_info_pci_config
,
238 typeof_field(PCIDevice
,config
)),
239 VMSTATE_INT32_ARRAY_V(irq_state
, PCIDevice
, PCI_NUM_PINS
, 2),
240 VMSTATE_END_OF_LIST()
244 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
246 vmstate_save_state(f
, &vmstate_pci_device
, s
);
249 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
251 return vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
254 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
258 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
259 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
260 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
265 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
267 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
272 unsigned long dom
= 0, bus
= 0;
276 val
= strtoul(p
, &e
, 16);
282 val
= strtoul(p
, &e
, 16);
289 val
= strtoul(p
, &e
, 16);
295 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
303 /* Note: QEMU doesn't implement domains other than 0 */
304 if (dom
!= 0 || pci_find_bus(bus
) == NULL
)
313 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
316 /* strip legacy tag */
317 if (!strncmp(addr
, "pci_addr=", 9)) {
320 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
321 monitor_printf(mon
, "Invalid pci address\n");
327 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
334 return pci_find_bus(0);
337 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
342 return pci_find_bus(bus
);
345 static void pci_init_cmask(PCIDevice
*dev
)
347 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
348 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
349 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
350 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
351 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
352 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
353 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
354 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
357 static void pci_init_wmask(PCIDevice
*dev
)
360 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
361 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
362 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
363 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
364 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
365 dev
->wmask
[i
] = 0xff;
368 /* -1 for devfn means auto assign */
369 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
370 const char *name
, int devfn
,
371 PCIConfigReadFunc
*config_read
,
372 PCIConfigWriteFunc
*config_write
)
375 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
376 if (!bus
->devices
[devfn
])
381 } else if (bus
->devices
[devfn
]) {
385 pci_dev
->devfn
= devfn
;
386 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
387 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
388 pci_set_default_subsystem_id(pci_dev
);
389 pci_init_cmask(pci_dev
);
390 pci_init_wmask(pci_dev
);
393 config_read
= pci_default_read_config
;
395 config_write
= pci_default_write_config
;
396 pci_dev
->config_read
= config_read
;
397 pci_dev
->config_write
= config_write
;
398 bus
->devices
[devfn
] = pci_dev
;
399 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
400 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
404 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
405 int instance_size
, int devfn
,
406 PCIConfigReadFunc
*config_read
,
407 PCIConfigWriteFunc
*config_write
)
411 pci_dev
= qemu_mallocz(instance_size
);
412 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
413 config_read
, config_write
);
416 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
418 return addr
+ pci_mem_base
;
421 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
426 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
427 r
= &pci_dev
->io_regions
[i
];
428 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
430 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
431 isa_unassign_ioport(r
->addr
, r
->size
);
433 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
440 static int pci_unregister_device(DeviceState
*dev
)
442 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
443 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
447 ret
= info
->exit(pci_dev
);
451 pci_unregister_io_regions(pci_dev
);
453 qemu_free_irqs(pci_dev
->irq
);
454 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
458 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
459 pcibus_t size
, int type
,
460 PCIMapIORegionFunc
*map_func
)
466 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
469 if (size
& (size
-1)) {
470 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
471 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
475 r
= &pci_dev
->io_regions
[region_num
];
476 r
->addr
= PCI_BAR_UNMAPPED
;
479 r
->map_func
= map_func
;
482 addr
= pci_bar(pci_dev
, region_num
);
483 if (region_num
== PCI_ROM_SLOT
) {
484 /* ROM enable bit is writeable */
485 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
487 pci_set_long(pci_dev
->config
+ addr
, type
);
488 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
489 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
490 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
491 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
493 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
494 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
498 static void pci_update_mappings(PCIDevice
*d
)
502 pcibus_t last_addr
, new_addr
;
504 cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
505 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
506 r
= &d
->io_regions
[i
];
508 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
509 if (cmd
& PCI_COMMAND_IO
) {
510 new_addr
= pci_get_long(d
->config
+ pci_bar(d
, i
));
511 new_addr
= new_addr
& ~(r
->size
- 1);
512 last_addr
= new_addr
+ r
->size
- 1;
513 /* NOTE: we have only 64K ioports on PC */
514 if (last_addr
<= new_addr
|| new_addr
== 0 ||
515 last_addr
>= 0x10000) {
516 new_addr
= PCI_BAR_UNMAPPED
;
519 new_addr
= PCI_BAR_UNMAPPED
;
522 if (cmd
& PCI_COMMAND_MEMORY
) {
523 if (r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
524 new_addr
= pci_get_quad(d
->config
+ pci_bar(d
, i
));
526 new_addr
= pci_get_long(d
->config
+ pci_bar(d
, i
));
528 /* the ROM slot has a specific enable bit */
529 if (i
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
))
531 new_addr
= new_addr
& ~(r
->size
- 1);
532 last_addr
= new_addr
+ r
->size
- 1;
533 /* NOTE: we do not support wrapping */
534 /* XXX: as we cannot support really dynamic
535 mappings, we handle specific values as invalid
537 if (last_addr
<= new_addr
|| new_addr
== 0 ||
538 last_addr
== PCI_BAR_UNMAPPED
||
540 /* Now pcibus_t is 64bit.
541 * Check if 32 bit BAR wrap around explicitly.
542 * Without this, PC ide doesn't work well.
543 * TODO: remove this work around.
545 (!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) &&
546 last_addr
>= UINT32_MAX
) ||
549 * OS is allowed to set BAR beyond its addressable
550 * bits. For example, 32 bit OS can set 64bit bar
553 last_addr
>= TARGET_PHYS_ADDR_MAX
) {
554 new_addr
= PCI_BAR_UNMAPPED
;
558 new_addr
= PCI_BAR_UNMAPPED
;
561 /* now do the real mapping */
562 if (new_addr
!= r
->addr
) {
563 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
564 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
566 /* NOTE: specific hack for IDE in PC case:
567 only one byte must be mapped. */
568 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
569 if (class == 0x0101 && r
->size
== 4) {
570 isa_unassign_ioport(r
->addr
+ 2, 1);
572 isa_unassign_ioport(r
->addr
, r
->size
);
575 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
578 qemu_unregister_coalesced_mmio(r
->addr
, r
->size
);
582 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
583 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
590 uint32_t pci_default_read_config(PCIDevice
*d
,
591 uint32_t address
, int len
)
594 assert(len
== 1 || len
== 2 || len
== 4);
595 len
= MIN(len
, PCI_CONFIG_SPACE_SIZE
- address
);
596 memcpy(&val
, d
->config
+ address
, len
);
597 return le32_to_cpu(val
);
600 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
602 uint8_t orig
[PCI_CONFIG_SPACE_SIZE
];
605 /* not efficient, but simple */
606 memcpy(orig
, d
->config
, PCI_CONFIG_SPACE_SIZE
);
607 for(i
= 0; i
< l
&& addr
< PCI_CONFIG_SPACE_SIZE
; val
>>= 8, ++i
, ++addr
) {
608 uint8_t wmask
= d
->wmask
[addr
];
609 d
->config
[addr
] = (d
->config
[addr
] & ~wmask
) | (val
& wmask
);
611 if (memcmp(orig
+ PCI_BASE_ADDRESS_0
, d
->config
+ PCI_BASE_ADDRESS_0
, 24)
612 || ((orig
[PCI_COMMAND
] ^ d
->config
[PCI_COMMAND
])
613 & (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
)))
614 pci_update_mappings(d
);
617 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
621 int config_addr
, bus_num
;
624 PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
627 bus_num
= (addr
>> 16) & 0xff;
628 while (s
&& pci_bus_num(s
) != bus_num
)
632 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
635 config_addr
= addr
& 0xff;
636 PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
637 pci_dev
->name
, config_addr
, val
, len
);
638 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
641 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
645 int config_addr
, bus_num
;
648 bus_num
= (addr
>> 16) & 0xff;
649 while (s
&& pci_bus_num(s
) != bus_num
)
653 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
670 config_addr
= addr
& 0xff;
671 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
672 PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
673 pci_dev
->name
, config_addr
, val
, len
);
676 PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
682 /***********************************************************/
683 /* generic PCI irq support */
685 /* 0 <= irq_num <= 3. level must be 0 or 1 */
686 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
688 PCIDevice
*pci_dev
= opaque
;
692 change
= level
- pci_dev
->irq_state
[irq_num
];
696 pci_dev
->irq_state
[irq_num
] = level
;
699 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
702 pci_dev
= bus
->parent_dev
;
704 bus
->irq_count
[irq_num
] += change
;
705 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
708 /***********************************************************/
709 /* monitor info on PCI */
716 static const pci_class_desc pci_class_descriptions
[] =
718 { 0x0100, "SCSI controller"},
719 { 0x0101, "IDE controller"},
720 { 0x0102, "Floppy controller"},
721 { 0x0103, "IPI controller"},
722 { 0x0104, "RAID controller"},
723 { 0x0106, "SATA controller"},
724 { 0x0107, "SAS controller"},
725 { 0x0180, "Storage controller"},
726 { 0x0200, "Ethernet controller"},
727 { 0x0201, "Token Ring controller"},
728 { 0x0202, "FDDI controller"},
729 { 0x0203, "ATM controller"},
730 { 0x0280, "Network controller"},
731 { 0x0300, "VGA controller"},
732 { 0x0301, "XGA controller"},
733 { 0x0302, "3D controller"},
734 { 0x0380, "Display controller"},
735 { 0x0400, "Video controller"},
736 { 0x0401, "Audio controller"},
738 { 0x0480, "Multimedia controller"},
739 { 0x0500, "RAM controller"},
740 { 0x0501, "Flash controller"},
741 { 0x0580, "Memory controller"},
742 { 0x0600, "Host bridge"},
743 { 0x0601, "ISA bridge"},
744 { 0x0602, "EISA bridge"},
745 { 0x0603, "MC bridge"},
746 { 0x0604, "PCI bridge"},
747 { 0x0605, "PCMCIA bridge"},
748 { 0x0606, "NUBUS bridge"},
749 { 0x0607, "CARDBUS bridge"},
750 { 0x0608, "RACEWAY bridge"},
752 { 0x0c03, "USB controller"},
756 static void pci_info_device(PCIDevice
*d
)
758 Monitor
*mon
= cur_mon
;
761 const pci_class_desc
*desc
;
763 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
765 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
766 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
767 monitor_printf(mon
, " ");
768 desc
= pci_class_descriptions
;
769 while (desc
->desc
&& class != desc
->class)
772 monitor_printf(mon
, "%s", desc
->desc
);
774 monitor_printf(mon
, "Class %04x", class);
776 monitor_printf(mon
, ": PCI device %04x:%04x\n",
777 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
778 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
780 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
781 monitor_printf(mon
, " IRQ %d.\n",
782 d
->config
[PCI_INTERRUPT_LINE
]);
784 if (class == 0x0604) {
785 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
787 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
788 r
= &d
->io_regions
[i
];
790 monitor_printf(mon
, " BAR%d: ", i
);
791 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
792 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
793 " [0x%04"FMT_PCIBUS
"].\n",
794 r
->addr
, r
->addr
+ r
->size
- 1);
796 const char *type
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
?
798 const char *prefetch
=
799 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
?
800 " prefetchable" : "";
802 monitor_printf(mon
, "%s%s memory at 0x%08"FMT_PCIBUS
803 " [0x%08"FMT_PCIBUS
"].\n",
805 r
->addr
, r
->addr
+ r
->size
- 1);
809 monitor_printf(mon
, " id \"%s\"\n", d
->qdev
.id
? d
->qdev
.id
: "");
810 if (class == 0x0604 && d
->config
[0x19] != 0) {
811 pci_for_each_device(d
->config
[0x19], pci_info_device
);
815 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
817 PCIBus
*bus
= first_bus
;
821 while (bus
&& pci_bus_num(bus
) != bus_num
)
824 for(devfn
= 0; devfn
< 256; devfn
++) {
825 d
= bus
->devices
[devfn
];
832 void pci_info(Monitor
*mon
)
834 pci_for_each_device(0, pci_info_device
);
837 static const char * const pci_nic_models
[] = {
849 static const char * const pci_nic_names
[] = {
861 /* Initialize a PCI NIC. */
862 /* FIXME callers should check for failure, but don't */
863 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
864 const char *default_devaddr
)
866 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
873 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
877 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
879 qemu_error("Invalid PCI device address %s for device %s\n",
880 devaddr
, pci_nic_names
[i
]);
884 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
885 dev
= &pci_dev
->qdev
;
887 dev
->id
= qemu_strdup(nd
->name
);
888 qdev_set_nic_properties(dev
, nd
);
889 if (qdev_init(dev
) < 0)
894 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
895 const char *default_devaddr
)
899 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
902 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
915 static void pci_bridge_write_config(PCIDevice
*d
,
916 uint32_t address
, uint32_t val
, int len
)
918 pci_default_write_config(d
, address
, val
, len
);
921 PCIBus
*pci_find_bus(int bus_num
)
923 PCIBus
*bus
= first_bus
;
925 while (bus
&& pci_bus_num(bus
) != bus_num
)
931 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
)
933 PCIBus
*bus
= pci_find_bus(bus_num
);
938 return bus
->devices
[PCI_DEVFN(slot
, function
)];
941 static int pci_bridge_initfn(PCIDevice
*dev
)
943 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
945 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
946 pci_config_set_device_id(s
->dev
.config
, s
->did
);
948 /* TODO: intial value
950 * According to PCI bridge spec, after reset
951 * bus master bit is off
952 * memory space enable bit is off
953 * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
954 * the reset value should be zero unless the boot pin is tied high
955 * (which is tru) and thus it should be PCI_COMMAND_MEMORY.
957 * For now, don't touch the value.
958 * Later command register will be set to zero and apb_pci.c will
959 * override the value.
960 * Same for latency timer, and multi function bit of header type.
962 pci_set_word(dev
->config
+ PCI_COMMAND
,
963 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
965 pci_set_word(dev
->config
+ PCI_STATUS
,
966 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
967 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
968 dev
->config
[PCI_LATENCY_TIMER
] = 0x10;
969 dev
->config
[PCI_HEADER_TYPE
] =
970 PCI_HEADER_TYPE_MULTI_FUNCTION
| PCI_HEADER_TYPE_BRIDGE
;
971 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
972 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
976 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
977 pci_map_irq_fn map_irq
, const char *name
)
982 dev
= pci_create(bus
, devfn
, "pci-bridge");
983 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
984 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
985 qdev_init_nofail(&dev
->qdev
);
987 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
988 pci_register_secondary_bus(&s
->bus
, &s
->dev
, map_irq
, name
);
992 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
994 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
995 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
999 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1000 devfn
= pci_dev
->devfn
;
1001 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1002 info
->config_read
, info
->config_write
);
1004 rc
= info
->init(pci_dev
);
1007 if (qdev
->hotplugged
)
1008 bus
->hotplug(pci_dev
, 1);
1012 static int pci_unplug_device(DeviceState
*qdev
)
1014 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1016 dev
->bus
->hotplug(dev
, 0);
1020 void pci_qdev_register(PCIDeviceInfo
*info
)
1022 info
->qdev
.init
= pci_qdev_init
;
1023 info
->qdev
.unplug
= pci_unplug_device
;
1024 info
->qdev
.exit
= pci_unregister_device
;
1025 info
->qdev
.bus_info
= &pci_bus_info
;
1026 qdev_register(&info
->qdev
);
1029 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1031 while (info
->qdev
.name
) {
1032 pci_qdev_register(info
);
1037 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1041 dev
= qdev_create(&bus
->qbus
, name
);
1042 qdev_prop_set_uint32(dev
, "addr", devfn
);
1043 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1046 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1048 PCIDevice
*dev
= pci_create(bus
, devfn
, name
);
1049 qdev_init_nofail(&dev
->qdev
);
1053 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1055 int offset
= PCI_CONFIG_HEADER_SIZE
;
1057 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
1060 else if (i
- offset
+ 1 == size
)
1065 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1070 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1073 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1074 prev
= next
+ PCI_CAP_LIST_NEXT
)
1075 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1083 /* Reserve space and add capability to the linked list in pci config space */
1084 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1086 uint8_t offset
= pci_find_space(pdev
, size
);
1087 uint8_t *config
= pdev
->config
+ offset
;
1090 config
[PCI_CAP_LIST_ID
] = cap_id
;
1091 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1092 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1093 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1094 memset(pdev
->used
+ offset
, 0xFF, size
);
1095 /* Make capability read-only by default */
1096 memset(pdev
->wmask
+ offset
, 0, size
);
1097 /* Check capability by default */
1098 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1102 /* Unlink capability from the pci config space. */
1103 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1105 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1108 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1109 /* Make capability writeable again */
1110 memset(pdev
->wmask
+ offset
, 0xff, size
);
1111 /* Clear cmask as device-specific registers can't be checked */
1112 memset(pdev
->cmask
+ offset
, 0, size
);
1113 memset(pdev
->used
+ offset
, 0, size
);
1115 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1116 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1119 /* Reserve space for capability at a known offset (to call after load). */
1120 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1122 memset(pdev
->used
+ offset
, 0xff, size
);
1125 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1127 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1130 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1132 PCIDevice
*d
= (PCIDevice
*)dev
;
1133 const pci_class_desc
*desc
;
1138 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1139 desc
= pci_class_descriptions
;
1140 while (desc
->desc
&& class != desc
->class)
1143 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1145 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1148 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1149 "pci id %04x:%04x (sub %04x:%04x)\n",
1151 pci_bus_num(d
->bus
), PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1152 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1153 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1154 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1155 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1156 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1157 r
= &d
->io_regions
[i
];
1160 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1161 " [0x%"FMT_PCIBUS
"]\n",
1163 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1164 r
->addr
, r
->addr
+ r
->size
- 1);
1168 static PCIDeviceInfo bridge_info
= {
1169 .qdev
.name
= "pci-bridge",
1170 .qdev
.size
= sizeof(PCIBridge
),
1171 .init
= pci_bridge_initfn
,
1172 .config_write
= pci_bridge_write_config
,
1173 .qdev
.props
= (Property
[]) {
1174 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1175 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1176 DEFINE_PROP_END_OF_LIST(),
1180 static void pci_register_devices(void)
1182 pci_qdev_register(&bridge_info
);
1185 device_init(pci_register_devices
)