hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8 #include "memory.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78
  79 #define FMT_PCIBUS                      PRIx64
  80
  81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  82                                 uint32_t address, uint32_t data, int len);
  83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  84                                    uint32_t address, int len);
  85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  86                                 pcibus_t addr, pcibus_t size, int type);
  87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  88
  89 typedef struct PCIIORegion {
  90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  92     pcibus_t size;
  93     pcibus_t filtered_size;
  94     uint8_t type;
  95     PCIMapIORegionFunc *map_func;
  96     MemoryRegion *memory;
  97     MemoryRegion *address_space;
  98 } PCIIORegion;
  99
 100 #define PCI_ROM_SLOT 6
 101 #define PCI_NUM_REGIONS 7
 102
 103 #include "pci_regs.h"
 104
 105 /* PCI HEADER_TYPE */
 106 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 107
 108 /* Size of the standard PCI config header */
 109 #define PCI_CONFIG_HEADER_SIZE 0x40
 110 /* Size of the standard PCI config space */
 111 #define PCI_CONFIG_SPACE_SIZE 0x100
 112 /* Size of the standart PCIe config space: 4KB */
 113 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 114
 115 #define PCI_NUM_PINS 4 /* A-D */
 116
 117 /* Bits in cap_present field. */
 118 enum {
 119     QEMU_PCI_CAP_MSI = 0x1,
 120     QEMU_PCI_CAP_MSIX = 0x2,
 121     QEMU_PCI_CAP_EXPRESS = 0x4,
 122
 123     /* multifunction capable device */
 124 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 125     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 126
 127     /* command register SERR bit enabled */
 128 #define QEMU_PCI_CAP_SERR_BITNR 4
 129     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 130 };
 131
 132 struct PCIDevice {
 133     DeviceState qdev;
 134     /* PCI config space */
 135     uint8_t *config;
 136
 137     /* Used to enable config checks on load. Note that writable bits are
 138      * never checked even if set in cmask. */
 139     uint8_t *cmask;
 140
 141     /* Used to implement R/W bytes */
 142     uint8_t *wmask;
 143
 144     /* Used to implement RW1C(Write 1 to Clear) bytes */
 145     uint8_t *w1cmask;
 146
 147     /* Used to allocate config space for capabilities. */
 148     uint8_t *used;
 149
 150     /* the following fields are read only */
 151     PCIBus *bus;
 152     uint32_t devfn;
 153     char name[64];
 154     PCIIORegion io_regions[PCI_NUM_REGIONS];
 155
 156     /* do not access the following fields */
 157     PCIConfigReadFunc *config_read;
 158     PCIConfigWriteFunc *config_write;
 159
 160     /* IRQ objects for the INTA-INTD pins.  */
 161     qemu_irq *irq;
 162
 163     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 164     uint8_t irq_state;
 165
 166     /* Capability bits */
 167     uint32_t cap_present;
 168
 169     /* Offset of MSI-X capability in config space */
 170     uint8_t msix_cap;
 171
 172     /* MSI-X entries */
 173     int msix_entries_nr;
 174
 175     /* Space to store MSIX table */
 176     uint8_t *msix_table_page;
 177     /* MMIO index used to map MSIX table and pending bit entries. */
 178     MemoryRegion msix_mmio;
 179     /* Reference-count for entries actually in use by driver. */
 180     unsigned *msix_entry_used;
 181     /* Region including the MSI-X table */
 182     uint32_t msix_bar_size;
 183     /* Version id needed for VMState */
 184     int32_t version_id;
 185
 186     /* Offset of MSI capability in config space */
 187     uint8_t msi_cap;
 188
 189     /* PCI Express */
 190     PCIExpressDevice exp;
 191
 192     /* Location of option rom */
 193     char *romfile;
 194     bool has_rom;
 195     MemoryRegion rom;
 196     uint32_t rom_bar;
 197 };
 198
 199 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 200                                int instance_size, int devfn,
 201                                PCIConfigReadFunc *config_read,
 202                                PCIConfigWriteFunc *config_write);
 203
 204 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 205                             pcibus_t size, uint8_t type,
 206                             PCIMapIORegionFunc *map_func);
 207 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
 208                              uint8_t attr, MemoryRegion *memory);
 209 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 210
 211 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 212                        uint8_t offset, uint8_t size);
 213
 214 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 215
 216 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 217
 218 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 219
 220
 221 uint32_t pci_default_read_config(PCIDevice *d,
 222                                  uint32_t address, int len);
 223 void pci_default_write_config(PCIDevice *d,
 224                               uint32_t address, uint32_t val, int len);
 225 void pci_device_save(PCIDevice *s, QEMUFile *f);
 226 int pci_device_load(PCIDevice *s, QEMUFile *f);
 227
 228 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 229 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 230
 231 typedef enum {
 232     PCI_HOTPLUG_DISABLED,
 233     PCI_HOTPLUG_ENABLED,
 234     PCI_COLDPLUG_ENABLED,
 235 } PCIHotplugState;
 236
 237 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 238                               PCIHotplugState state);
 239 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 240                          const char *name,
 241                          MemoryRegion *address_space_mem,
 242                          MemoryRegion *address_space_io,
 243                          uint8_t devfn_min);
 244 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 245                     MemoryRegion *address_space_mem,
 246                     MemoryRegion *address_space_io,
 247                     uint8_t devfn_min);
 248 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 249                   void *irq_opaque, int nirq);
 250 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 251 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 252 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 253                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 254                          void *irq_opaque,
 255                          MemoryRegion *address_space_mem,
 256                          MemoryRegion *address_space_io,
 257                          uint8_t devfn_min, int nirq);
 258 void pci_device_reset(PCIDevice *dev);
 259 void pci_bus_reset(PCIBus *bus);
 260
 261 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 262
 263 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 264                         const char *default_devaddr);
 265 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 266                                const char *default_devaddr);
 267 int pci_bus_num(PCIBus *s);
 268 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 269 PCIBus *pci_find_root_bus(int domain);
 270 int pci_find_domain(const PCIBus *bus);
 271 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 272 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 273 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 274 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 275
 276 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 277                       unsigned int *slotp, unsigned int *funcp);
 278 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 279                      unsigned *slotp);
 280
 281 void do_pci_info_print(Monitor *mon, const QObject *data);
 282 void do_pci_info(Monitor *mon, QObject **ret_data);
 283 void pci_bridge_update_mappings(PCIBus *b);
 284
 285 void pci_device_deassert_intx(PCIDevice *dev);
 286
 287 static inline void
 288 pci_set_byte(uint8_t *config, uint8_t val)
 289 {
 290     *config = val;
 291 }
 292
 293 static inline uint8_t
 294 pci_get_byte(const uint8_t *config)
 295 {
 296     return *config;
 297 }
 298
 299 static inline void
 300 pci_set_word(uint8_t *config, uint16_t val)
 301 {
 302     cpu_to_le16wu((uint16_t *)config, val);
 303 }
 304
 305 static inline uint16_t
 306 pci_get_word(const uint8_t *config)
 307 {
 308     return le16_to_cpupu((const uint16_t *)config);
 309 }
 310
 311 static inline void
 312 pci_set_long(uint8_t *config, uint32_t val)
 313 {
 314     cpu_to_le32wu((uint32_t *)config, val);
 315 }
 316
 317 static inline uint32_t
 318 pci_get_long(const uint8_t *config)
 319 {
 320     return le32_to_cpupu((const uint32_t *)config);
 321 }
 322
 323 static inline void
 324 pci_set_quad(uint8_t *config, uint64_t val)
 325 {
 326     cpu_to_le64w((uint64_t *)config, val);
 327 }
 328
 329 static inline uint64_t
 330 pci_get_quad(const uint8_t *config)
 331 {
 332     return le64_to_cpup((const uint64_t *)config);
 333 }
 334
 335 static inline void
 336 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 337 {
 338     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 339 }
 340
 341 static inline void
 342 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 343 {
 344     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 345 }
 346
 347 static inline void
 348 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 349 {
 350     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 351 }
 352
 353 static inline void
 354 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 355 {
 356     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 357 }
 358
 359 static inline void
 360 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 361 {
 362     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 363 }
 364
 365 static inline void
 366 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 367 {
 368     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 369 }
 370
 371 /*
 372  * helper functions to do bit mask operation on configuration space.
 373  * Just to set bit, use test-and-set and discard returned value.
 374  * Just to clear bit, use test-and-clear and discard returned value.
 375  * NOTE: They aren't atomic.
 376  */
 377 static inline uint8_t
 378 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 379 {
 380     uint8_t val = pci_get_byte(config);
 381     pci_set_byte(config, val & ~mask);
 382     return val & mask;
 383 }
 384
 385 static inline uint8_t
 386 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 387 {
 388     uint8_t val = pci_get_byte(config);
 389     pci_set_byte(config, val | mask);
 390     return val & mask;
 391 }
 392
 393 static inline uint16_t
 394 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 395 {
 396     uint16_t val = pci_get_word(config);
 397     pci_set_word(config, val & ~mask);
 398     return val & mask;
 399 }
 400
 401 static inline uint16_t
 402 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 403 {
 404     uint16_t val = pci_get_word(config);
 405     pci_set_word(config, val | mask);
 406     return val & mask;
 407 }
 408
 409 static inline uint32_t
 410 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 411 {
 412     uint32_t val = pci_get_long(config);
 413     pci_set_long(config, val & ~mask);
 414     return val & mask;
 415 }
 416
 417 static inline uint32_t
 418 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 419 {
 420     uint32_t val = pci_get_long(config);
 421     pci_set_long(config, val | mask);
 422     return val & mask;
 423 }
 424
 425 static inline uint64_t
 426 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 427 {
 428     uint64_t val = pci_get_quad(config);
 429     pci_set_quad(config, val & ~mask);
 430     return val & mask;
 431 }
 432
 433 static inline uint64_t
 434 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 435 {
 436     uint64_t val = pci_get_quad(config);
 437     pci_set_quad(config, val | mask);
 438     return val & mask;
 439 }
 440
 441 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 442 typedef struct {
 443     DeviceInfo qdev;
 444     pci_qdev_initfn init;
 445     PCIUnregisterFunc *exit;
 446     PCIConfigReadFunc *config_read;
 447     PCIConfigWriteFunc *config_write;
 448
 449     uint16_t vendor_id;
 450     uint16_t device_id;
 451     uint8_t revision;
 452     uint16_t class_id;
 453     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 454     uint16_t subsystem_id;              /* only for header type = 0 */
 455
 456     /*
 457      * pci-to-pci bridge or normal device.
 458      * This doesn't mean pci host switch.
 459      * When card bus bridge is supported, this would be enhanced.
 460      */
 461     int is_bridge;
 462
 463     /* pcie stuff */
 464     int is_express;   /* is this device pci express? */
 465
 466     /* device isn't hot-pluggable */
 467     int no_hotplug;
 468
 469     /* rom bar */
 470     const char *romfile;
 471 } PCIDeviceInfo;
 472
 473 void pci_qdev_register(PCIDeviceInfo *info);
 474 void pci_qdev_register_many(PCIDeviceInfo *info);
 475
 476 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 477                                     const char *name);
 478 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 479                                            bool multifunction,
 480                                            const char *name);
 481 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 482                                         bool multifunction,
 483                                         const char *name);
 484 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 485 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 486 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 487
 488 static inline int pci_is_express(const PCIDevice *d)
 489 {
 490     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 491 }
 492
 493 static inline uint32_t pci_config_size(const PCIDevice *d)
 494 {
 495     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 496 }
 497
 498 #endif