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hw/char: shakti_uart: Register device in 'input' category
2021-10-06 Bin Menghw/char: shakti_uart: Register device in 'input' category
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/char: ibex_uart: Register device in 'input' category
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Frank Changtarget/riscv: Set mstatus_hs.[SD|FS] bits if Clean...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichdisas/riscv: Add Zb[abcs] instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove RVB (replaced by Zb[abcs])
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2021-10-06 Philipp Tomsichtarget/riscv: Add zext.h instructions to Zbb, removing...
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2021-10-06 Philipp Tomsichtarget/riscv: Add rev8 instruction, removing grev/grevi
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2021-10-06 Philipp Tomsichtarget/riscv: Add a REQUIRE_32BIT macro
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2021-10-06 Philipp Tomsichtarget/riscv: Add orc.b instruction for Zbb, removing...
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbb-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add instructions of the Zbc-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbs-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Remove shift-one instructions (proposed...
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2021-10-06 Philipp Tomsichtarget/riscv: Remove the W-form instructions from Zbs
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zba-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
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2021-10-06 Philipp Tomsichtarget/riscv: clwz must ignore high bits (use shift...
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2021-10-06 Philipp Tomsichtarget/riscv: fix clzw implementation to operate on...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Introduce temporary in gen_add_uw()
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Bin Mengtarget/riscv: csr: Rename HCOUNTEREN_CY and friends
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Frank Changtarget/riscv: Backup/restore mstatus.SD bit when virtual...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Bin Mengdocs/system/riscv: sifive_u: Update U-Boot instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: don't set Control.error if 0 bytes...
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2021-09-20 Green Wanhw/dma: sifive_pdma: allow non-multiple transaction...
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2021-09-20 Frank Changhw/dma: sifive_pdma: claim bit must be set before DMA...
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2021-09-20 Frank Changhw/dma: sifive_pdma: reset Next* registers when Control...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Add optional ACLINT support to virt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Re-factor FDT generation
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Upgrade the SiFive CLINT implementation to...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Rename sifive_clint sources to riscv_aclint...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francissifive_u: Connect the SiFive PWM device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/timer: Add SiFive PWM support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_timer: Convert the timer to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_plic: Convert the PLIC to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_plic: Convert the PLIC to use RISC-V...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 LIU Zhiweitarget/riscv: Fix satp write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVV
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Tidy trans_rvh.c.inc
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVD
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVF
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2021-09-01 Richard Hendersontarget/riscv: Use gen_shift_imm_fn for slli_uw
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVA
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2021-09-01 Richard Hendersontarget/riscv: Reorg csr instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Fix hgeie, hgeip
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get, dest}_gpr for integer load...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use get_gpr in branches
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use extracts for sraiw and srliw
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use DisasExtend in shift operations
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_unary
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVB
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVM
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2021-09-01 Richard Hendersontarget/riscv: Use gen_arith for mulh and mulhu
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2021-09-01 Richard Hendersontarget/riscv: Remove gen_arith_div*
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_arith*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Introduce DisasExtend and new helpers
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Clean up division helpers
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontests/tcg/riscv64: Add test for division
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2021-09-01 Richard Hendersontarget/riscv: Use tcg_constant_*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/registerfields: Use 64-bit bitfield for FIELD_DP64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/core/register: Add more 64-bit utilities
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 David Hoppenbrouwershw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Peter Maydellhw/riscv/virt.c: Assemble plic_hart_config string with...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Add User CSRs read-only check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Don't wrongly override isa version
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Mengtarget/riscv: Correct a comment in riscv_csrrw()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Menghw/riscv: virt: Move flash node to root
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Vijai Kumar Khw/char: Add config for shakti uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the flash alias
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francischar: ibex_uart: Update the register layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Menghw/riscv: sifive_u: Make sure firmware info is 8-byte...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Menghw/riscv: sifive_u: Correct the CLINT timebase frequency
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Update Microchip Icicle Kit for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Jose Martinstarget/riscv: hardwire bits in hideleg and hedeleg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Add documentation for virt machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengdocs/system: riscv: Fix CLINT name in the sifive_u doc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Bin Mengtarget/riscv: csr: Remove redundant check in fp csr...
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2021-07-14 Bin Mengtarget/riscv: pmp: Fix some typos
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2021-06-24 Alistair Francishw/riscv: OpenTitan: Connect the mtime and mtimecmp...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/timer: Initial commit of Ibex Timer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
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2021-06-24 Lukas Jüngerhw/char: QOMify sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Lukas Jüngerhw/char: Consistent function names for sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Bin Mengtarget/riscv: gdbstub: Fix dynamic CSR XML generation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: add b-ext version cpu option
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: support and turn on B-extension...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: add/shift with prefix zero-extend
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: address calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2021-06-07 Kito Chengtarget/riscv: rvb: rotate (left/right)
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2021-06-07 Kito Chengtarget/riscv: rvb: shift ones
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Ray Wang's QEMU Repository