2021-10-06 | Bin Meng | hw/char: shakti_uart: Register device in 'input' category Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Bin Meng | hw/char: ibex_uart: Register device in 'input' category Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Frank Chang | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | disas/riscv: Add Zb[abcs] instructions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Remove RVB (replaced by Zb[abcs]) Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add zext.h instructions to Zbb, removing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add rev8 instruction, removing grev/grevi Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add a REQUIRE_32BIT macro Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add orc.b instruction for Zbb, removing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Reassign instructions to the Zbb-extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add instructions of the Zbc-extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Reassign instructions to the Zbs-extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Remove shift-one instructions (proposed... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Remove the W-form instructions from Zbs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Reassign instructions to the Zba-extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: clwz must ignore high bits (use shift... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: fix clzw implementation to operate on... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-10-06 | Philipp Tomsich | target/riscv: Introduce temporary in gen_add_uw() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-21 | Alistair Francis | hw/riscv: opentitan: Correct the USB Dev address Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-21 | Bin Meng | target/riscv: csr: Rename HCOUNTEREN_CY and friends Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-21 | Frank Chang | target/riscv: Backup/restore mstatus.SD bit when virtual... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Bin Meng | docs/system/riscv: sifive_u: Update U-Boot instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Frank Chang | hw/dma: sifive_pdma: don't set Control.error if 0 bytes... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Green Wan | hw/dma: sifive_pdma: allow non-multiple transaction... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Frank Chang | hw/dma: sifive_pdma: claim bit must be set before DMA... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Frank Chang | hw/dma: sifive_pdma: reset Next* registers when Control... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Anup Patel | hw/riscv: virt: Add optional ACLINT support to virt... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Anup Patel | hw/riscv: virt: Re-factor FDT generation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Anup Patel | hw/intc: Upgrade the SiFive CLINT implementation to... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Anup Patel | hw/intc: Rename sifive_clint sources to riscv_aclint... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | sifive_u: Connect the SiFive PWM device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | hw/timer: Add SiFive PWM support Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | hw/intc: ibex_timer: Convert the timer to use RISC... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | hw/intc: sifive_plic: Convert the PLIC to use RISC... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | hw/intc: ibex_plic: Convert the PLIC to use RISC-V... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | hw/intc: sifive_clint: Use RISC-V CPU GPIO lines Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | target/riscv: Expose interrupt pending bits as GPIO... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | LIU Zhiwei | target/riscv: Fix satp write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-20 | Alistair Francis | target/riscv: Update the ePMP CSR address Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use {get,dest}_gpr for RVV Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Tidy trans_rvh.c.inc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use {get,dest}_gpr for RVD Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use {get,dest}_gpr for RVF Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use gen_shift_imm_fn for slli_uw Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use {get,dest}_gpr for RVA Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Reorg csr instructions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Fix hgeie, hgeip Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use {get, dest}_gpr for integer load... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use get_gpr in branches Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use extracts for sraiw and srliw Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use DisasExtend in shift operations Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Add DisasExtend to gen_unary Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Move gen_* helpers for RVB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Move gen_* helpers for RVM Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use gen_arith for mulh and mulhu Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Remove gen_arith_div* Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Add DisasExtend to gen_arith* Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Introduce DisasExtend and new helpers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Clean up division helpers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | tests/tcg/riscv64: Add test for division Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Richard Henderson | target/riscv: Use tcg_constant_* Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Joe Komlodi | hw/registerfields: Use 64-bit bitfield for FIELD_DP64 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Joe Komlodi | hw/core/register: Add more 64-bit utilities Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | David Hoppenbrouwers | hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Peter Maydell | hw/riscv/virt.c: Assemble plic_hart_config string with... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | LIU Zhiwei | target/riscv: Add User CSRs read-only check Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | LIU Zhiwei | target/riscv: Don't wrongly override isa version Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Bin Meng | target/riscv: Correct a comment in riscv_csrrw() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Bin Meng | hw/riscv: virt: Move flash node to root Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-09-01 | Vijai Kumar K | hw/char: Add config for shakti uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Alistair Francis | hw/riscv/boot: Check the error of fdt_pack() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Alistair Francis | hw/riscv: opentitan: Add the flash alias Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Alistair Francis | hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Alistair Francis | char: ibex_uart: Update the register layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | hw/riscv: sifive_u: Make sure firmware info is 8-byte... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | hw/riscv: sifive_u: Correct the CLINT timebase frequency Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Update Microchip Icicle Kit for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Jose Martins | target/riscv: hardwire bits in hideleg and hedeleg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Add documentation for virt machine Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | docs/system: riscv: Fix CLINT name in the sifive_u doc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | target/riscv: csr: Remove redundant check in fp csr... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-07-14 | Bin Meng | target/riscv: pmp: Fix some typos Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | hw/riscv: OpenTitan: Connect the mtime and mtimecmp... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | hw/timer: Initial commit of Ibex Timer Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | hw/char/ibex_uart: Make the register layout private Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Lukas Jünger | hw/char: QOMify sifive_uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Lukas Jünger | hw/char: Consistent function names for sifive_uart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Bin Meng | target/riscv: gdbstub: Fix dynamic CSR XML generation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-24 | Alistair Francis | target/riscv: Use target_ulong for the DisasContext... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: add b-ext version cpu option Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: support and turn on B-extension... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: add/shift with prefix zero-extend Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: address calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: generalized or-combine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Frank Chang | target/riscv: rvb: generalized reverse Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: rotate (left/right) Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-06-07 | Kito Cheng | target/riscv: rvb: shift ones Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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