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2020-09-09	Bin Meng	hw/dma: Add SiFive platform DMA controller emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/sd: Add Cadence SDHCI emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/char: Add Microchip PolarFire SoC MMUART emulation Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: Initial support for Microchip PolarFire SoC... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	target/riscv: cpu: Set reset vector based on the configured... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	hw/riscv: hart: Add a new 'resetvec' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-09-09	Bin Meng	target/riscv: cpu: Add a new 'resetvec' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	gitlab-ci/opensbi: Update GitLab CI to build generic... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: spike: Change the default bios to use generic... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: Use pre-built bios image of generic platform... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	roms/Makefile: Build the generic platform for RISC... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	roms/opensbi: Upgrade from v0.7 to v0.8 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	configure: Create symbolic links for pc-bios/*.elf... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-22	Bin Meng	hw/riscv: sifive_u: Add a dummy L2 cache controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-21	Bin Meng	hw/sd: Correct the maximum size of a Standard Capacity... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-08-21	Bin Meng	hw/sd: Fix incorrect populated function switch status... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-07-22	Bin Meng	hw/riscv: sifive_e: Correct debug block size Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-07-14	Bin Meng	hw/riscv: Modify MROM size to end at 0x10000 Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-07-14	Bin Meng	hw/riscv: virt: Sort the SoC memmap table entries Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-07-14	Bin Meng	MAINTAINERS: Add an entry for OpenSBI firmware Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add a dummy DDR memory controller... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Sort the SoC memmap table entries Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Support different boot source per... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive: Change SiFive E/U CPU reset vector... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	target/riscv: Rename IBEX CPU init routine Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add a new property msel for MSEL... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Rename serial property get/set... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Add reset functionality Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Do not blindly trigger output... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Hook a GPIO controller Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Add a new 'ngpio' property Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_gpio: Clean up the codes Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Generate device tree node for OTP Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_u: Simplify the GEM IRQ connect code... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: opentitan: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	hw/riscv: sifive_e: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Keep the CPU init routine names consistent Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the imacu CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the gcsu CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-19	Bin Meng	riscv: Generalize CPU init routine for the base CPU Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	hw/riscv: virt: Remove the riscv_ prefix of the machine... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	hw/riscv: sifive_u: Remove the riscv_ prefix of the... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	riscv: Change the default behavior if no -bios option... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-06-03	Bin Meng	riscv: Suppress the error report for QEMU testing with... Signed-off-by: Bin Meng <bin.meng@windriver.com>	commit \| commitdiff \| tree
2020-04-29	Bin Meng	roms: opensbi: Upgrade from v0.6 to v0.7 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-04-29	Bin Meng	hw/riscv: Generate correct "mmu-type" for 32-bit machines Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-04-29	Bin Meng	riscv/sifive_u: Add a serial property to the sifive_u... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-03-17	Bin Meng	gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-03-17	Bin Meng	riscv: sifive_u: Update BIOS_FILENAME for 32-bit Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-03-17	Bin Meng	roms: opensbi: Add 32-bit firmware image for sifive_u... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-03-17	Bin Meng	roms: opensbi: Upgrade from v0.5 to v0.6 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-03-03	Bin Meng	hw: net: cadence_gem: Fix build errors in DB_PRINT() Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2020-02-27	Bin Meng	riscv: virt: Allow PCI address 0 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: sifive_u: Add ethernet0 to the aliases node Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: hw: Drop "clock-frequency" property of cpu nodes Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-10-28	Bin Meng	riscv: Skip checking CSR privilege level in debugger... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update model and compatible strings... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Remove handcrafted clock nodes for... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Fix broken GEM support Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Instantiate OTP memory with a serial... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Implement a model for SiFive FU540 OTP Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Update default bios for sifive_u machine Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Change UART node name in device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update UART base addresses and IRQs Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Reference PRCI clocks in UART and... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Add PRCI block to the SoC Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Generate hfclk and rtcclk nodes Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Implement PRCI model for FU540 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update PLIC hart topology configuration... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Update hart configuration to reflect... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Set the minimum number of cpus to 2 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Add a "hartid-base" property to RISC-V... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hart: Extract hart realize to a separate routine Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a sifive_cpu.h to include both E and U cpu... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: Drop sifive_mmio_emulate() Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Update the PRCI register block... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_e: prci: Fix a typo of hfxosccfg register... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_u: Remove the unnecessary include of... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: roms: Remove executable attribute of opensbi... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove the unnecessary include of target... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Change create_fdt() to return void Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove not needed PLIC properties in device... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Use qemu_fdt_setprop_cell() for property... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove superfluous "linux, phandle" property Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hw: Remove duplicated "hw/hw.h" inclusion Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: sifive_test: Add reset functionality Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: hmp: Add a command to show virtual memory mappings Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Resolve full path of the given bios image Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: Add a helper routine for finding firmware Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-09-17	Bin Meng	riscv: rv32: Root page table address can be larger... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-08-13	Bin Meng	riscv: roms: Fix make rules for building sifive_u bios Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Update the plic hart config to support... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-06-27	Bin Meng	riscv: sifive_u: Do not create hard-coded phandles... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-06-24	Bin Meng	riscv: virt: Correct pci "bus-range" encoding Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-03-19	Bin Meng	riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree
2019-03-19	Bin Meng	riscv: sifive_uart: Generate TX interrupt Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	commit \| commitdiff \| tree

Ray Wang's QEMU Repository

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