| commit | a9ec1c76d57491602b4d3b521f898905825ca848 | |
| author | Bin Meng <bmeng.cn@gmail.com> | |
| Sun, 17 Mar 2019 08:03:11 +0000 (17 01:03 -0700) | ||
| committer | Palmer Dabbelt <palmer@sifive.com> | |
| Tue, 19 Mar 2019 12:18:42 +0000 (19 05:18 -0700) | ||
| tree | c92ba2a23b71389ac9c5f68db0d60aca5d381396 | treesnapshot (tar.gz zip) |
| parent | 4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354 | commitdiff |
riscv: sifive_u: Correct UART0's IRQ in the device tree
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| hw/riscv/sifive_u.c | diffblobblamehistory |